Physical memory protection modes

[Joseph Rahmeh]

Hi all,

 

Regarding the A field of the PMPCFG registers, the privileged spec, section 3.6.1,  says:

When G ≥ 1, the NA4 mode is not selectable.

Would it be possible to make the spec more specific?  What should happen if software attempted to select NA4 when G >= 1? Do we replace NA4 with OFF, or with NAPOT?

 

Similarly, if software tries to select a PMP mode (the “A” field in PMPCFG) that is not implemented?  Should the hardware replace that with an implemented mode or should it always replace with OFF?  Must the OFF code always be implemented if any code is implemented?

 

Joe Rahmeh

 

[Allen Baum]

All the fields are WARL, so whatever you attempt to write, the result will be some legal value.

The spec also says that implementations get to decide legal values based on the state of the hart and the value being written - but don't specify what that mapping should be. Compliance has defined some mappings it will support (and no others), so you should look at https://riscv-config.readthedocs.io/en/latest/yaml-specs.html#warl-field-definition

An easy default is to just inhibit the write to the field, leaving the old (legal) value if you attempt to write one that is illegal.

I don't think that riscv-config YAML defines the "G" property, but it will have to get defined at some point, and the formal model will need to incorporate it into its code.

--
You received this message because you are subscribed to the Google Groups "RISC-V ISA Dev" group.
To unsubscribe from this group and stop receiving emails from it, send an email to isa-dev+u...@groups.riscv.org.
To view this discussion on the web visit https://groups.google.com/a/groups.riscv.org/d/msgid/isa-dev/71BE0C15-665C-4933-9BE1-D72AB5180352%40contoso.com.