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Lots of early computers used this technique; the DEC PDP-10 comes to mind.There was an option you could buy that implemented the GPRs separately in logic instead of main memory to increase performance- but you could still address them as main memory (so RR ops actually used memory addresses; I don't recall that there were separate RR ops)One trick used to increase performance was to load small, short loops into the register file and execute out of it!
I think early low-end IBM 360s might have done this also.But, in this case, you want to essentially remove the "addresses" of the register file from the address map. That shouldn't be difficult,e.g. the Sifive memory map has holes at the bottom of memory to catch null pointer references,so SW that tries to access that range with a load/store would trap, You'd need to suppress that trap if HW were accessing it as a register, as opposed to a load/store'/or iFetch, though.
I've seen this used on 8 bit microcontrollers such as the ones from Microchip. Not really sure if it fits in with the riscv instruction design because that means 3 memory accesses for most instructions plus the instruction fetch itself.
olof.k: It would be interesting to know which FPGAs are using that resource count. It's noticed that number can very alot even between different models by the same company.
I'm thinking of how an instruction like "add t0, t1, t2" would work. I would think it would be 3 access through your dbus and 1 access through your ibus from the instruction itself. Both funnel though your serving_arbiter. So I think that would be 4 sram accesses for this instruction.
Hey there isa-devils!I have this idea for a new extension intended for the smallest of cores in the most deeply embedded systems for replacing 8-bit CPUs, complex FSMs and such with RISC-V. The general idea of the extension is to memory-map the register file in RAM (hence Z RF in RAM). I'm not a toolchain guy though, so I thought I'd throw it out here to get some feeling for the general interest and if this makes any sense at all.For some background, I'm the designer of the award-winning SERV, the world's smallest RISC-V CPU (https://github.com/olofk/serv). SERV is around 2.1kGE or 100-200LUT on various FPGA implementations. This means that memory size is the dominating factor here. On FPGA, which has fixed size SRAM typically 1kB-8kB, we can save a whole SRAM by using a slice of the data/instruction memory for the RF (to give you an idea of how many SERV cores that can be fit into various FPGAs this way, you can look at https://corescore.store/). For ASIC we get some saving as well because we don't need additional control logic if we use the same memory for RF and instructions/data. And in both cases we can easily reclaim 64 bytes of RAM by just compiling our code with RV32E and use the storage normally used for x16-x31. For the kind of applications I'm envisioning this could be a signicant amount of memory. If we have a hand-written piece of assembler that only uses 4 regs then we have a whooping 112 bytes of additional RAM at our disposal.None of the above requires a new extension. We just need to make sure SW doesn't touch the memory used by the RF, but I'm wondering whether to take this one step further. I'm not a compiler guy though, so I have no idea if any of these things make sense or would be terribly compilated
First thing I'm thinking of is whether we could/should add something to the compiler/linker that automatically finds out which is the highest-numbered register used and then allows the rest to be used as RAM. Perhaps a flag to set the maximum reg number?. I have recently learned about -ffixed-reg, but also that it might not be so easy to use with an ABI. Should this be discussed as part of the effort to ratify the RV32E extension perhaps? Can we do something clever by using sh/sb to change value of a half/quarter register?
The second thing is that if we have memory-mapped RF, someone mentioned we could also consider adding a CSR to indicate the base address. Having that writable could e.g. enable shadow register files for fast context switching. Again, does that make sense? Would it just be terribly complicated to implement support for?
I briefly discussed this during my presentation at the RISC-V Summit last week (https://award-winning.me/serv-32-bit-is-the-new-8-bit) but never found the time to discuss it in detail with anyone there so I'm hoping to get some comments this way instead. So....what do you think?
//Olof
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I've seen this used on 8 bit microcontrollers such as the ones from Microchip. Not really sure if it fits in with the riscv instruction design because that means 3 memory accesses for most instructions plus the instruction fetch itself.
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I'm not sure we want to trap. Partly because I believe that systems small enough to benefit from thiswouldn't necessarily be able to do something meaningful on an illegal access and partly becauseit would allow doing byte accesses on registers...if that would be of any use. Or maybe not.
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I’m curious why you would want to move the X registers to sram?
What is the goal?
I agree the core size is smaller (remove core flops vs. add sram bytes – significant in chip size??), but the increase in power consumption from accessing memory more often would seem to be a bigger concern.
Jeff
From: Iztok Jeras <iztok...@gmail.com>
Sent: Wednesday, January 4, 2023 8:36 AM
To: Allen Baum <allen...@esperantotech.com>
Cc: Olof Kindgren <olof.k...@gmail.com>; RISC-V ISA Dev <isa...@groups.riscv.org>
Subject: [EXT] Re: [isa-dev] Thoughts on a Zrfinram extension
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I’m curious why you would want to move the X registers to sram?
What is the goal?
I agree the core size is smaller (remove core flops vs. add sram bytes – significant in chip size??), but the increase in power consumption from accessing memory more often would seem to be a bigger concern.
Hi Olof,
I watched your presentation. Really great work.
In many super low end applications that I have experience with, power is more important than area. I can see now your use case is area is more important than power, so many more accesses to sram is not an issue.
In these super low end applications I have experience with, I have seen RISC-V ISA used with 8 (7 really due to X0) implemented X-registers built with flip flops. I assume they were programming in pure assembly for this use case. It would be nice if the compiler could handle this, but have my doubts it would ever happen.
Jeff
Hi Olof,
I watched your presentation. Really great work.
In many super low end applications that I have experience with, power is more important than area. I can see now your use case is area is more important than power, so many more accesses to sram is not an issue.
In these super low end applications I have experience with, I have seen RISC-V ISA used with 8 (7 really due to X0) implemented X-registers built with flip flops. I assume they were programming in pure assembly for this use case. It would be nice if the compiler could handle this, but have my doubts it would ever happen.
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Apologies if veering off-topic but...
> Please remember that we already have a RISC-V member that is shipping a 2KRam part that has RV32E
I presume that's actually "some draft version of RV32E"?
Or was it ratified in time for this silicon?
If not, then yet another tools mess like the draft V extension in silicon to come, I presume? :-(