RISC-V for safety related applications

[Markus Kreidl]

Hi all,

my Name is Markus I work for a research company in Austria (www.opentech.at) and we are working
on a project called SIL2LinuxMP with the goal to realize safety related applications based on
Linux based operating system on multi- core hardware platforms.
The lack of information about IP cores makes it basically impossible  to use available
CPUs for this kind of mission. 

We are looking for people/companies with a similar intention and try to setup a working group to
make risc-v fit for safety related applications.

If you are interested please let me know, my mail mkreidl at opentech at.

regards
Markus

[Luke Kenneth Casson Leighton]

Hi marcus the formal verification of the core is critical, hilarious stories about commercial companies complaining that all their other customers have trusted their proprietary verified cores so why the hell are you asking for the verilog source and the full source of the verification suite??

oink :)

Clifford Wolf has one formal verification tool, and Bluespec are developing another, they both did talks at barcelona, apologies not at laptop otherwise I would look up references.

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[Allen Baum]

You need to think twice or more before you send sarcastic reply  emails. My native language is English, and I had to read it 3 times before I figured out you were not mocking him.

Safety Critical applications have many requirements above and beyond opcode level architectural requirements, and the verification test suites ( formal or not) don't test for the kinds of microarchitectural features.that are required.

-Allen

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[Markus Kreidl]

I took me 3 times too but the smiley helped (my native language is
German) and I was happy somebody responded :)

@Luke Thanks for the links I will check them properly.

As Allen said safety Critical applications have many requirements.
Many people just think in random but not in systematic faults also
certain units
have to be testable like the ECC of caches. My first intention was to
gather people who are interested and have the same problems.

/Markus

[Luke Kenneth Casson Leighton]

On Fri, May 25, 2018 at 6:37 AM, Markus Kreidl <markus...@gmail.com> wrote:
> I took me 3 times too but the smiley helped (my native language is
> German) and I was happy somebody responded :)

appreciated the heads-up (to allen as well), apologies it was really
quite a late-night reply.

> @Luke Thanks for the links I will check them properly.

https://github.com/rsnikhil/Bluespec_BSV_Formal_Semantics/
https://github.com/cliffordwolf/riscv-formal

> As Allen said safety Critical applications have many requirements.
> Many people just think in random but not in systematic faults also
> certain units
> have to be testable like the ECC of caches. My first intention was to
> gather people who are interested and have the same problems.

i met someone at barcelona as well who is from uni-heidelberg, he is
interested in formal-verification of F.P. units. i overheard him
talking with krste, krste mentioned that the IEEE 754 formal
verification suite is... well, i can't recall if you used the word
"mess" or not, krste...

it's a start.

l.

[Paul Chaffey]

Hello all,

yes please add me to any ISO 26262 and ASIL related topics. Any ECC and parity added via Rocketchip to a RISC-V would be an extremely interesting thing.

I think that Google might be doing something here also... But this is a Rumor so lets not start another fake news thread!

What I would like in an ideal world is a small embedded RISC-V with ECC and parity (on address bus) and also perhaps a few strategically placed safety FF's which would be able to achieve ASIL B (90% coverage for faults).

regards, Paul

(Infineon)

[Madhu]

We have been developing fault tolerant cores but it has been a low key effort till now.

https://ieeexplore.ieee.org/document/7422253/

But we will soon be increasing our effort to develop cores

with in-core fault tolerance and multi-core SoCs with lockstep support.

Along with associated redundancy in the Tile-link fabric for redundancy

and ECC support.

We will probably leverage the formal spec work and bluespec to also explore

proving the correctness of our cores. The Rodin environment may be useful

in this regard. We plan to stick to our in-order cores.

These cores are planned to be used for our ASIl-D/ISO26262 work and also 

for our autonomous vehicle platform. We supply cores for rector safety controls

and aerospace applications ,

so we need to do this ! 

We will need a WG at some point to focus on this work. This cannot be pulled off by

one team.

Also looking at using SEL4 for AUTOSAR applications.

If that does work, we plan to develop a rust based MK OS. We have started

working with some auto OEMs in this area. Preliminary discussions to see what a

complete platform should entail - cores, SoC fabrics, OS and verification environment.

[Christopher Celio]

Any ECC and parity added via Rocketchip to a RISC-V would be an extremely interesting thing.

On this topic, there's work by Rafael Tonetto, et. al. to evaluate fault sensitivity using RISC-V BOOM as their RTL model (which itself is built on top of rocket-chip). 

"Precise evaluation of the fault sensitivity of OoO superscalar processors"

https://ieeexplore.ieee.org/abstract/document/8342082/ [paper]

http://www.lume.ufrgs.br/handle/10183/169905 [thesis]

-Chris

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