32 bit relative jump

[b little]

According to riscv.spec v2.2, AUIPC and JALR are combined to enable 32-bit absolute relative jump.

But you could only add unsigned immediate to pc using AUIPC, how could this enable 32-bit negative jump?

[Rishiyur Nikhil]

If the MSB of the 20b immediate in AUIPC is 1, it represents a negative number.

In RV32, that bit becomes bit [31] of the offset, which is the sign bit.

In RV64, that bit is sign-extended to bit [63] (see line 1, p31, user ISA spec v2.2).

Nikhil

On Tue, Aug 7, 2018 at 5:45 AM, b little <ror...@gmail.com> wrote:

According to riscv.spec v2.2, AUIPC and JALR are combined to enable 32-bit absolute relative jump.

But you could only add unsigned immediate to pc using AUIPC, how could this enable 32-bit negative jump?

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[b little]

So if I'm trying to generate instructions that do a 32 bit relative-offset, I can just encode the higher 20bit in auipc, and the lower 12bit in jalr? 

在 2018年8月7日星期二 UTC+1上午11:30:39，nikhil写道：

If the MSB of the 20b immediate in AUIPC is 1, it represents a negative number.

In RV32, that bit becomes bit [31] of the offset, which is the sign bit.

In RV64, that bit is sign-extended to bit [63] (see line 1, p31, user ISA spec v2.2).

Nikhil

On Tue, Aug 7, 2018 at 5:45 AM, b little <ror...@gmail.com> wrote:

According to riscv.spec v2.2, AUIPC and JALR are combined to enable 32-bit absolute relative jump.

But you could only add unsigned immediate to pc using AUIPC, how could this enable 32-bit negative jump?

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[Michael Clark]

On 7/08/2018, at 9:45 PM, b little <ror...@gmail.com> wrote:

According to riscv.spec v2.2, AUIPC and JALR are combined to enable 32-bit absolute relative jump.

But you could only add unsigned immediate to pc using AUIPC, how could this enable 32-bit negative jump?

AUIPC adds a sign extended 20-bit immediate, sign_extend(bits[31:12]), to the program counter and stores the result in rd. The range is +/-2GiB from the program counter. 

Note: 0x800 is added to the relative offset to the target address before taking bits[31:12], as the lower 12 bits are also added signed, using ADDI which adds a signed 12-bit immediate, bits[11:0], giving it ~11 bits of range, plus sign for direction, in two’s complement.

The problem is the lo12 is also signed and thus requires pre-adjustment to hi20 to get the full reach. Once you get your head around it, it’s pretty simple.

It is described in PC-Relative Offsets (in the context of relocations) here:

https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#relocations

The wording could be refined, however AUIPC is documented as being signed in the Base ISA docs.

[Michael Clark]

> On 7/08/2018, at 10:35 PM, b little <ror...@gmail.com> wrote:
>
> So if I'm trying to generate instructions that do a 32 bit relative-offset, I can just encode the higher 20bit in auipc, and the lower 12bit in jalr?

JALR has a signed 12-bit immediate, hence you would add 0x800 to the offset from the AUIPC instruction before taking bits[32:12] and use the resulting offset for calculating the signed offset for the JALR.

The address computation is described in the link I sent in my previous email.

[b little]

I understand now.

The calculation method confirms the control flow of the assembly code I was examining.

Thank you so much, the link and the explanation are very helpful : D

在 2018年8月7日星期二 UTC+1上午11:50:37，Michael Clark写道：