Trivial floating point implementation in SystemVerilog

[iztok.jeras]

Is there a trivial (combinatorial, non synthesizable) floating point implementation in SystemVerilog?
I need just a placeholder so I can run riscv_arch_test, to test my instruction decoder.
In the C extension, there are many sequences which map into either F or I, depending on XWIDTH. And i would like to make sure I decoded the right instruction.

Regards,

Iztok Jeras

[Krste Asanovic]

Berkeley HardFloat

Krste

--
You received this message because you are subscribed to the Google Groups "RISC-V HW Dev" group.
To unsubscribe from this group and stop receiving emails from it, send an email to hw-dev+un...@groups.riscv.org.
To view this discussion on the web visit https://groups.google.com/a/groups.riscv.org/d/msgid/hw-dev/f7adb6a6-7453-4c77-8ca4-a483ff6a3f98n%40groups.riscv.org.