How to integrate Rocket-chip on a custom SoC

[재민김]

Hi.
When I generate Rocket Chip, not only CPU but the memory sub system is generated which includes Bootrom, PLIC, ... etc. However, I'd like to remove all these internal memories and connect Rocket Chip to a custom SoC system bus which then connects to all external memories including bootrom, ram, flash and other device memories. Is it possible to reconfigure RocketChip configuration so that it generates memory map without any internal memories?
(I've tried simply modifying the memory map in the config file which did not work.)

Thank you.
With regards,
Jamie Kim

[Wei Song]

Hello Jamie,

In lowRISC, we had done similar. You can have a look of http://www.lowrisc.org/docs/debug-v0.3/soc_struct/
Now we get a boot BRAM, flash, uart, SD card (SPI) on a NASTI (AXI) bus.
We also have some instructions about how to add a new SystemVerilog slave device on the NASTI(AXI) bus. http://www.lowrisc.org/docs/debug-v0.3/add_device/
However, our Rocket-chip is not synced with the latest rocket-chip repo (updated to May 2016).

-Wei

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[Bernd]

I use the latest rocket-chip repository. I modified src/main/scala/rocketchip/Config.scala (based on TinyConfig) in order to get an additional uncached MMIO-AXI bus, which will finally be connected to an AXI-to-AHB bridge.

 

class WithExtMMIOAXIChannels(n: Int) extends Config (

  (pname, site, here) => pname match {

    case NExtMMIOAXIChannels => n

  }

)

class CYC2DE1Config extends Config (

  new WithExtMMIOAXIChannels(1) ++ new WithExtMemSize(0x1000) ++

  new WithSmallCores ++ new WithRV32 ++

  new WithStatelessBridge ++ new BaseConfig

)

The module 'Top'  and 'Periphery' have now additional signals (io_mmio_axi_0_*) but module 'DefaultCoreplex' has not (only io_mem_0_*).

How can I map the entire external I/O range to MMIO?

[Bernd]

Sorry, I meant an AXI-to-APB bridge.

[재민김]

I see the same problem. More fundamentally, are there any documents that describes the full set of cofigurations in Rocketchip? While Rocketchip does so much things, there seems to be so little documentation that describes what it does.

2016. 9. 11. 오후 10:40에 "Bernd" <bernd....@gmail.com>님이 작성:

Sorry, I meant an AXI-to-APB bridge.

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[Bernd Beuster]

After much tinkering, I came up with the following configuration.

class WithExtMMIOAXIChannels extends Config (

  (pname, site, here) => pname match {

      case TLId => "MMIO_Outermost"

      case NExtMMIOAXIChannels => 1

      case ExtMMIOPorts => Seq(AddrMapEntry("MyExtIO", MemRange(0x50000000, 0x10000000, MemAttr(AddrMapProt.RW))))

  }

)

class MyConfig extends Config (

  new WithExtMemSize(0x1000) ++

  new WithExtMMIOAXIChannels ++

  new WithSmallCores ++ new WithRV32 ++

  new WithStatelessBridge ++ new BaseConfig

)

Simulation will show, if it works.

[Evgeni Krimer]

Hi,

Can you please elaborate on
>   case TLId => "MMIO_Outermost"

How is it used?

I've got this to work:

class WithExtMMIOAXIChannels extends Config (

  (pname, site, here) => pname match {

     case NExtMMIOAXIChannels => 1

      case ExtMMIOPorts => Seq(AddrMapEntry("MyExtIO", MemRange(0x60000000, 0x10000000, MemAttr(AddrMapProt.RW, false))))

  }

)

But want to make sure I didn't miss anything important.

Thanks,
Evgeni

[Bernd Beuster]

Without defining TLid I got the following exception. 

Caused by: cde.ParameterUndefinedException: Parameter TLId undefined.

I updated to the newest master branch and got the same error. I wonder how your config seems to work?

[Evgeni Krimer]

This is what I am using :

class WithMyMMIO extends Config (

 (pname, site, here) => pname match {

     case NExtMMIOAXIChannels => 1

     case ExtMMIOPorts => Seq(AddrMapEntry("MyExtIO", MemRange(0x60000000, 0x10000000, MemAttr(AddrMapProt.RW, false))))

 }

)

 

class MyConfig extends Config(

  new WithMyMMIO ++

  new DefaultConfig

)

I am at https://github.com/ucb-bar/rocket-chip/commit/61cbe6164d9a10a661884938740d4cd5520548c8

[재민김]

I was out of office for a week. I'll get back after I go back to office and do some excercise

2016. 9. 21. 오전 3:05에 "Bernd Beuster" <bernd....@gmail.com>님이 작성:

Without defining TLid I got the following exception. 

Caused by: cde.ParameterUndefinedException: Parameter TLId undefined.

I updated to the newest master branch and got the same error. I wonder how your config seems to work?

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