Updated Rocket Core Specification Note

[adaptiveprocessor]

Hi all,

I have read this document;

http://www-inst.eecs.berkeley.edu/~cs250/fa13/handouts/lab2-riscv.pdf

But this is too old, does anyone know newest version of rocket specification note?

If I need more detail information, should I read code in chisel description at the repository, or is there other resource?

Best Regards,

S.Takano

[Andrew Waterman]

Hi Takano-san,

The lowRISC documentation (http://www.lowrisc.org/docs/) is more up-to-date.  If that doesn't help, please feel free to post specific questions to the rocket-chip github issue tracker.

Andrew

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[adaptiveprocessor]

Dear Waterman-san,

Thank you very musch for your quick replying.

I know lowRISC since it is in OpenCores site, but I do not know the LowRISC is fully coded with Chisel (I need my own extension and want not to take a risk by using not standard model).

Is the LowRISC completely compatible with Rocket microprocessor in now?, if not is there a list of difference betweeen them?

Anyway, again, thank you very much, I try to read it.

Best Regards,

S.Takano

On Thursday, January 11, 2018 at 5:43:09 PM UTC+9, waterman wrote:

Hi Takano-san,

The lowRISC documentation (http://www.lowrisc.org/docs/) is more up-to-date.  If that doesn't help, please feel free to post specific questions to the rocket-chip github issue tracker.

Andrew

On Thu, Jan 11, 2018 at 12:37 AM, adaptiveprocessor <adaptive...@gmail.com> wrote:

Hi all,

I have read this document;

http://www-inst.eecs.berkeley.edu/~cs250/fa13/handouts/lab2-riscv.pdf

But this is too old, does anyone know newest version of rocket specification note?

If I need more detail information, should I read code in chisel description at the repository, or is there other resource?

Best Regards,

S.Takano

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[Dr Jonathan Kimmitt]

Dear Takano-san,

The lowrisc.org system is based on an older version of Rocket that uses Tilelink-1, the latest Rocket uses Tilelink-2. L2 cache for Tilelink-2 has not been released yet.

Also the lowrisc system has hardware security extensions and customisations for use on FPGA, such as Xilinx DDR control. This periphery uses AXI compatible bus and

is not coherent like Tilelink. The latest Rocket also includes compressed instructions and run/halt debugging and a newer version of the privilege spec. Tilelink-2 addresses

bugs in Tilelink-1 that are mostly to do with SMP. In general the method of customising Chisel is not portable between old and new versions of Rocket. Either way it will be

a considerable learning curve.

Regards,

Jonathan

To view this discussion on the web visit https://groups.google.com/a/groups.riscv.org/d/msgid/hw-dev/d2d4e629-4576-4b4f-8812-fc3cfdf12d6b%40groups.riscv.org.

[adaptiveprocessor]

Dear Kimmitt-san,

Thank you for your replying makes clear a little bit.

I want to replace cache memory with local memory in each tile and want a message passing.

Many processes (threads) are in its own memory image and does share address of its virtual address.

External memory is single address space, but threads live in it at first.

And my first target is FPGA platform (not ASIC at start line), so I think cache memory is not necessary but it is an option.

If you know about a link of rocket core and router microarchitecture specification documents having latest information, please let me know.

Best Regards,

S.Takano

[Stefan O'Rear]

On Thu, Jan 11, 2018 at 10:45 AM, adaptiveprocessor
<adaptive...@gmail.com> wrote:
> If you know about a link of rocket core and router microarchitecture
> specification documents having latest information, please let me know.

There is to the best of my knowledge no router and no up to date
rocket core microarchitecture specification document.

For functional (not microarchitectural) documentation you may have
luck with the documentation SiFive has written for their rocket-chip
derived deliverables; for instance Chapter 3 of
https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf#page=12 .

-s

[高野茂幸]

Dear Stefan-san,

Thanks for the information.

Regarding Sifive site, I do not know it’s index page, so I cannot seek in the site.
Do you have any idea to access all resources in the site?

Best Regards,
S.Takano

2018年1月12日(金) 12:32 Stefan O'Rear <sor...@gmail.com>:

[Stefan O'Rear]

On Thu, Jan 11, 2018 at 11:41 PM, 高野茂幸 <adaptive...@gmail.com> wrote:
> Dear Stefan-san,
>
> Thanks for the information.
>
> Regarding Sifive site, I do not know it’s index page, so I cannot seek in
> the site.
> Do you have any idea to access all resources in the site?

Apologies, should have linked that earlier. The index page is
https://www.sifive.com/documentation/ .

-s