DAC presentation slides (survey results on RISC V implementations)

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Guy Lemieux

non lue,
23 juin 2017, 12:40:0123/06/2017
à RISC-V ISA Dev,RISC-V HW Dev
Hi,

I'm attaching my DAC presentation which includes the survey results on various RISC V implementations that are available in the ecosystem. These slides will be available on the DAC website in a few months (!).

I'll forward the detailed survey results to the RISC V Marketting Committee. I know they are planning their own survey, and these results will help their planning.

A big thank you to all who filled out the survey, and thanks to Andrew Waterman, Krste Asanovic and Yunsup Lee for sharing their slides and providing feedback on my slides.

Ciao,
Guy
2017-06-20 DAC VectorBlox RISC V pdf.pdf

Ouabache Designworks

non lue,
23 juin 2017, 13:22:3723/06/2017
à Guy Lemieux,RISC-V ISA Dev,RISC-V HW Dev

John Eaton

Tommy Thorn

non lue,
23 juin 2017, 13:24:0023/06/2017
à Ouabache Designworks,Guy Lemieux,RISC-V ISA Dev,RISC-V HW Dev
Arrghh.  It's missing an 'm' :(


On Fri, Jun 23, 2017 at 10:22 AM, Ouabache Designworks <z3qm...@gmail.com> wrote:

John Eaton

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高野茂幸

non lue,
23 juin 2017, 14:29:0823/06/2017
à Guy Lemieux,RISC-V HW Dev,RISC-V ISA Dev
Hi Guy-San,

I am interested in how implementing an xnor and pop count in your Binary NN Accelerator
Is cross point and inverter select corresponds the xnor?
Or inherently not implementation of xnor and pop count?

Best Regards,

S.Takano


2017年6月24日(土) 1:40 Guy Lemieux <glem...@vectorblox.com>:
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Samuel Falvo II

non lue,
24 juin 2017, 00:08:1324/06/2017
à Guy Lemieux,RISC-V ISA Dev,RISC-V HW Dev
kresetelcomputer.github.io/krestel

My repo is misspelled quite badly; this is the correct URL:

kestrelcomputer.github.io/kestrel

(As a useful mnemonic, just remember it's named after a bird of prey. :) )
> --
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> "RISC-V ISA Dev" group.
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> https://groups.google.com/a/groups.riscv.org/d/msgid/isa-dev/CALo5CZyUN%3DmR1FrG4YoRBXnjWNATfTtoTRdAC9%3D8WFtKDZnorw%40mail.gmail.com.



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Guy Lemieux

non lue,
30 juin 2017, 17:31:2130/06/2017
à RISC-V ISA Dev,RISC-V HW Dev
My apologies for the project URL typos ... they are now fixed and I am re-posting the final slides here.

Thanks for filling in the surveys!

Guy



On Fri, Jun 23, 2017 at 9:08 PM, Samuel Falvo II <sam....@gmail.com> wrote:
kresetelcomputer.github.io/krestel

My repo is misspelled quite badly; this is the correct URL:

kestrelcomputer.github.io/kestrel

(As a useful mnemonic, just remember it's named after a bird of prey.  :) )


On Fri, Jun 23, 2017 at 9:38 AM, Guy Lemieux <glem...@vectorblox.com> wrote:
> Hi,
>
> I'm attaching my DAC presentation which includes the survey results on
> various RISC V implementations that are available in the ecosystem. These
> slides will be available on the DAC website in a few months (!).
>
> I'll forward the detailed survey results to the RISC V Marketting Committee.
> I know they are planning their own survey, and these results will help their
> planning.
>
> A big thank you to all who filled out the survey, and thanks to Andrew
> Waterman, Krste Asanovic and Yunsup Lee for sharing their slides and
> providing feedback on my slides.
>
> Ciao,
> Guy
>
> --
> You received this message because you are subscribed to the Google Groups
> "RISC-V ISA Dev" group.
> To unsubscribe from this group and stop receiving emails from it, send an



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Samuel A. Falvo II

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2017-06-20 DAC VectorBlox RISC V pdf.pdf

Guy Lemieux

non lue,
4 juil. 2017, 03:40:4204/07/2017
à 高野茂幸,RISC-V HW Dev,RISC-V ISA Dev
It's not based on XNOR/popcount. It's for binary weights with uint8 activations.

Details on the binary-weight accelerator are in the attached paper.
The paper will soon be posted to arxiv.org here:
https://arxiv.org/html/1704.08802

Guy
olaf2017-lemieux.pdf

高野茂幸

non lue,
4 juil. 2017, 05:43:2004/07/2017
à Guy Lemieux,RISC-V HW Dev,RISC-V ISA Dev
Hi Guy-san,

Thank you for sharing your paper.
I read several binary CNN papers, then I wonder how interface present API and the accelerators or simply it is not programmable accelerators.

Best Regards,
S.Takano

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