TileLink and Diplomacy in Rocket Chip

[fswo...@gmail.com]

Hi,

I'm new to RISC-V and to hardware development altogether. Right now I'm trying to familiarize myself with Diplomacy/TileLink approach in Rocket Chip (which is way harder than in probably should've been because of total absence of source code comments in Rocket Chip repo).

As such, I was hoping for a kickstart. Could you please advise me on how to:

1. Increase number of TileLink busses inside Rocket Chip configuration?
   
2. Keep track of (e.g. log?) the Diplomacy negotiation process?
   

Thanks.

[Megan Wachs]

Not sure about logging the negotiation process, but you may want to look at the graphml produced when you build your verilog (actually the firrtl). You can open it up in a program like yEdand it gives you a view of all the diplomatic nodes in the system.

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Megan A. Wachs

Technical Director | SiFive, Inc 

1875 South Grant Street
Suite 600
San Mateo, CA 94402

me...@sifive.com

[Muhammad Ali Akhtar]

Megan,

First of all, thanks for the response. but you used bunch of words that are completely new to me so would really appreciate little more help.

graphml----> what is it? where is it produced? in "generated-src directory"?
   

Muhammad Ali Akhtar
Principal Design Engineer
http://www.linkedin.com/in/muhammadakhtar

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