Would experts explain how Rocket-chip DecodeLogic works?

david mlw

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Jul 12, 2018, 5:11:42 AM7/12/18

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DecodeLogic is invoked twice, in IDecode.scala:

  def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]) = {
    val decoder = DecodeLogic(inst, default, table)
    val sigs = Seq(legal, fp, rocc, branch, jal, jalr, rxs2, rxs1, sel_alu2,
                   sel_alu1, sel_imm, alu_dw, alu_fn, mem, mem_cmd, mem_type,
                   rfs1, rfs2, rfs3, wfd, mul, div, wxd, csr, fence_i, fence, amo, dp)
    sigs zip decoder map {case(s,d) => s := d}
    this
  }

and FPU.scala:

  val decoder = DecodeLogic(io.inst, default, insns)
  val s = io.sigs
  val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12,
                 s.swap23, s.singleIn, s.singleOut, s.fromint, s.toint,
                 s.fastpipe, s.fma, s.div, s.sqrt, s.wflags)
  sigs zip decoder map {case(s,d) => s := d}

and object DecodeLogic is defined in Decode.scala, returning a sequence of UInt.

def apply(addr: UInt, default: Seq[BitPat], mappingIn: Iterable[(BitPat, Seq[BitPat])]): Seq[UInt]

Apparently, DecodeLogic returns different sequence in IDecode and FPU, but how?

Christopher Celio

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Jul 12, 2018, 4:27:42 PM7/12/18

to david mlw, RISC-V HW Dev

DecodeLogic invokes a Quine-Mccluskey algorithm to perform logic minimization that maps a set of keys to output signals, where the input table is allowed to use 0, 1, and dontCare.

-Chris

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Edmond Cote

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Jul 12, 2018, 6:30:54 PM7/12/18

to Christopher Celio, david mlw, RISC-V HW Dev

Apologies in advance for the tangent...

I have always looked at this algorithm and thought, gee what a neat/verification friendly way of specifying control logic for decode, but never dove into the "why"...

Assuming that the output of the algorithm (Verilog RTL) is fed into a commercial synthesis tool that itself implements its own logic minimization algorithms ...

My question is whether pre-minimizing the control logic leads to better QoR than using a synthesis tool alone (i.e. by supplying one huge "always" block / behavioral Verilog combo. modeling)? Perhaps its a limitation in Chisel that cannot emit such always blocks, and I'm reaching now, that would enable (provide hints to) the synthesis tool to perform similar optimizations?

-Ed

On Thu, Jul 12, 2018 at 1:27 PM Christopher Celio <ce...@berkeley.edu> wrote:

DecodeLogic invokes a Quine-Mccluskey algorithm to perform logic minimization that maps a set of keys to output signals, where the input table is allowed to use 0, 1, and dontCare.

-Chris

On Thu, Jul 12, 2018 at 2:11 AM, david mlw <davi...@gmail.com> wrote:

DecodeLogic is invoked twice, in IDecode.scala:

def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]) = { val decoder = DecodeLogic(inst, default, table) val sigs = Seq(legal, fp, rocc, branch, jal, jalr, rxs2, rxs1, sel_alu2, sel_alu1, sel_imm, alu_dw, alu_fn, mem, mem_cmd, mem_type, rfs1, rfs2, rfs3, wfd, mul, div, wxd, csr, fence_i, fence, amo, dp) sigs zip decoder map {case(s,d) => s := d} this }

and FPU.scala:
val decoder = DecodeLogic(io.inst, default, insns) val s = io.sigs val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12, s.swap23, s.singleIn, s.singleOut, s.fromint, s.toint, s.fastpipe, s.fma, s.div, s.sqrt, s.wflags) sigs zip decoder map {case(s,d) => s := d}

and object DecodeLogic is defined in Decode.scala, returning a sequence of UInt.
def apply(addr: UInt, default: Seq[BitPat], mappingIn: Iterable[(BitPat, Seq[BitPat])]): Seq[UInt]

Apparently, DecodeLogic returns different sequence in IDecode and FPU, but how?

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Christopher Celio

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Jul 12, 2018, 6:37:53 PM7/12/18

to Edmond Cote, david mlw, RISC-V HW Dev

Interesting question Edmond.

The issue here is that in Chisel we have eschewed the usage of 1'hx in the language (with some very constrained exceptions). Therefore, we can't feed regular case statements with 1'hx and let the verilog optimization tools do their thing.

rocket.DecodeLogic was a way to "have our cake and eat it too" -- we could get the logic minimization benefits of a DontCare by calling a special function which will ONLY generate 0s and 1s as its output, and we don't have to pay for all the other pain points brought about by the 1'hx semantics elsewhere in the design flow.

-Chris

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david mlw

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Jul 12, 2018, 11:00:03 PM7/12/18

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I See.

Instructions.scala defines the instruction pattern. The table in Decode is a mapping from instruction to result signals. And DecodeLogic optimizes the mapping logic.

Back to my question, IDecode and FPU get different results because they input different table, and the the table is listed in the signal order, so that the "A zig B map" works.

And to response your discussion. it is better to leave the implementation of a decoder mapping to case/casex as an infrastructure of CHISEL or pass to the later synthesis tools through CHISEL, which is easy understanding and better for future optimization.

Liwei

在 2018年7月13日星期五 UTC+8上午4:27:42，celio写道：

DecodeLogic invokes a Quine-Mccluskey algorithm to perform logic minimization that maps a set of keys to output signals, where the input table is allowed to use 0, 1, and dontCare.

-Chris

On Thu, Jul 12, 2018 at 2:11 AM, david mlw <davi...@gmail.com> wrote:

DecodeLogic is invoked twice, in IDecode.scala:

def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]) = { val decoder = DecodeLogic(inst, default, table) val sigs = Seq(legal, fp, rocc, branch, jal, jalr, rxs2, rxs1, sel_alu2, sel_alu1, sel_imm, alu_dw, alu_fn, mem, mem_cmd, mem_type, rfs1, rfs2, rfs3, wfd, mul, div, wxd, csr, fence_i, fence, amo, dp) sigs zip decoder map {case(s,d) => s := d} this }

and FPU.scala:
val decoder = DecodeLogic(io.inst, default, insns) val s = io.sigs val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12, s.swap23, s.singleIn, s.singleOut, s.fromint, s.toint, s.fastpipe, s.fma, s.div, s.sqrt, s.wflags) sigs zip decoder map {case(s,d) => s := d}

and object DecodeLogic is defined in Decode.scala, returning a sequence of UInt.
def apply(addr: UInt, default: Seq[BitPat], mappingIn: Iterable[(BitPat, Seq[BitPat])]): Seq[UInt]

Apparently, DecodeLogic returns different sequence in IDecode and FPU, but how?

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Zhanglei Wang

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May 29, 2019, 4:19:45 AM5/29/19

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Sorry for digging up a pretty old thread. But DecodeLogic is really interesting for a Chisel newbie like me :)

I noticed there is caches:Map[UInt,Map[Term,Bool]] in DecodeTable. I wonder how it can be synthesized?

Thanks!

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