Rocket Chip's build flow is a bit messy so your confusion is understandable.
I'll start with SBT and Make because that is the legacy Rocket Chip build flow. SBT is the most popular build tool in the Scala community, and as Rocket Chip is primarily Scala code, it is the most natural tool to use. Things get tricky though, because unlike in normal Scala projects where pretty much everything runs on the JVM, Rocket Chip generates Verilog which then needs to tie into more traditional hardware flows. SBT is really a JVM-specific tool and isn't all that well suited for calling Verilog simulators, synthesis tools and the like. Thus, Rocket Chip also has a Make flow for handling all of that. The separation of what is SBT vs. what is Make is super inelegant due to historic limitations, so unfortunately SBT has to be called twice (once to build FIRRTL on it's own, then again to build all of the rest of the Scala).
Wake is a new build tool from SiFive that is trying to solve the kind of problems I just described in the Make and SBT flow. Hardware design is fundamentally composed of many languages and many flows, and Wake is intended to provide a common build orchestration level to manage these many languages and flows. Wake has many great aspects, but it is new and has far less documentation and integration than Make or SBT.
I am in the process of cleaning up the Make/SBT flow while bumping Chisel and FIRRTL to the next major Chisel version 3.4. This should clean up the use from the Makefile perspective because the entire Scala build will be managed by SBT. Keep an eye on
https://github.com/chipsalliance/rocket-chip/pull/2617