Facilitating 32 bit host build of tools

[Tommy Murphy]

Hi there

By default the sources at https:://github.com/riscv/riscv-gnu-toolchain will not build in 32 bit host mode.

The build fails on riscv-binutils-gdb/sim/riscv/sim-main.c due to the issue described here:

https://groups.google.com/a/groups.riscv.org/forum/#!msg/sw-dev/Ejcaqshly3o/KhP_qaSbHQAJ

That post also links to a patch to allow compilation in 32 bit mode to proceed but (a) I don't know if it's completely correct and self contained (the description suggests that it may only work with specific compilation flags) and (b) I don't know if this has been submitted for inclusion in the master sources. 

Would it be possible to have this or another patch applied to enable 32 bit compilation of the tools without the need to patch locally?

Apologies but I don't know enough about the gdb/sim code to suggest a fix.

Thanks a lot

Regards

Tommy Murphy

Microsemi

[Kito Cheng]

Fix has been merged into master branch for riscv-gnu-toolchain,

and I've test on CentOS 6/i686, it's can build without any patch now :)

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[Tommy Murphy]

That's great - thanks a lot Kito. :-)

[Vania Joloboff]

Hi

The spec says that
"there are many possible ways to encode a NOP"

but it is not clear to me whether instructions
that are meaningless when specifying register x0 as destination
are interpreted as NOP or raise an illegal instruction exception ?

e.g. add x0, x5, x7

Does somebody know the answer ?

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[Richard Herveille]

Having x0 as a destination is not per sé meaningless.

It is perfectly legal to have x0 as a destination register.

Therefore those instructions are not ‘illegal’.

Richard

ROA LOGIC

Design Services and Silicon Proven IP

Richard Herveille

Managing Director

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richard....@roalogic.com

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