Cool. Now who's going to volunteer to make a 128-bit toolchain? :)
On Tue, Dec 20, 2016 at 1:56 AM, Fabrice Bellard <fab...@bellard.org> wrote:
> Hi,
>
> I just released RISCVEMU, a 128 bit RISC-V emulator (RV128IMAFDQC base
> ISA). It is available at:
>
> http://bellard.org/riscvemu/
>
> Best regards,
>
> Fabrice.
>
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We will need an assembler and linker.There is a model where the assembler selects 64-bit shifts and adds by default. i.e. add, addi are 64-bit and addq addiq are 128-bit, similarly for shifts. i.e. sllq, slliq, srlq, srliq for 128-bit. This would allow us to assemble output from a 64-bit compiler with an 128-bit assembler and 64-bit linker. Loads and stores already have width.This model would be 64-bit ELF with 64-bit codegen and 128-bit inline asm, builtins, etc (fast memcpy, inline asm for bigint and crypto).
On 21 Dec 2016, at 3:05 PM, Madhu Macaque Labs <ma...@macaque.in> wrote:
That is going to be a pain ! We do need 128 bit support but only for specific addressing modes,planning to use some hacks for that. How much effort does it take to get GCC to support128 bit ? If if its not too major a conceptual problem, I can take a stab at it. Helpshaving tons of interns ! And what would pointer sizes be ?
On Wed, Dec 21, 2016 at 5:27 AM, Andrew Waterman <and...@sifive.com> wrote:
Cool. Now who's going to volunteer to make a 128-bit toolchain? :)
On Tue, Dec 20, 2016 at 1:56 AM, Fabrice Bellard <fab...@bellard.org> wrote:
> Hi,
>
> I just released RISCVEMU, a 128 bit RISC-V emulator (RV128IMAFDQC base
> ISA). It is available at:
>
> http://bellard.org/riscvemu/
>
> Best regards,
>
> Fabrice.
>
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--Regards,Madhu
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It sure sounds like a single-level store with a channel controller. The file system would easily fit in there as well, a la the IBM i-system and Atlas.
FYI, IBM’s i-system has a fully-developed security system that works with its 64-bit-addressed single-level store. It’s also old, already successfully ported from a 48-bit single-level store, and it’s been in long-term serial production. So it’s not only fully debugged, the patents might be expired. i-systems have been using 64-bit Power cores for the last 15-20 years.
From: ron minnich [mailto:rmin...@gmail.com]
…
If you can find the docs (I can't) …
On Wed, Dec 21, 2016 at 8:14 AM John Leidel <john....@gmail.com> wrote:
Madhu, we've been toying with some partitioned address space methods using the RV128 model for GoblinCore. ..
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"A LDU (load double unsigned) instruction is added using the existing LOAD major opcode, alongwith new LQ and SQ instructions to load and store quadword values. SQ is added to the STOREmajor opcode, while LQ is added to the MISC-MEM major opcode.”
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