RISCVEMU: 128 bit RISC-V emulator

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Fabrice Bellard

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Dec 20, 2016, 12:14:20 PM12/20/16
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Hi,

I just released RISCVEMU, a 128 bit RISC-V emulator (RV128IMAFDQC base
ISA). It is available at:

http://bellard.org/riscvemu/

Best regards,

Fabrice.

Andrew Waterman

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Dec 20, 2016, 6:57:56 PM12/20/16
to Fabrice Bellard, RISC-V SW Dev
Cool. Now who's going to volunteer to make a 128-bit toolchain? :)
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Madhu Macaque Labs

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Dec 20, 2016, 9:05:45 PM12/20/16
to Andrew Waterman, Fabrice Bellard, RISC-V SW Dev
That is going to be a pain ! We do need 128 bit support but only for specific addressing modes,
planning to use some hacks for that.  How much effort does it take to get GCC to support
128 bit ? If if its not too major a conceptual problem, I can take a stab at it. Helps
having tons of  interns ! And what would pointer sizes be ?

On Wed, Dec 21, 2016 at 5:27 AM, Andrew Waterman <and...@sifive.com> wrote:
Cool.  Now who's going to volunteer to make a 128-bit toolchain? :)

On Tue, Dec 20, 2016 at 1:56 AM, Fabrice Bellard <fab...@bellard.org> wrote:
> Hi,
>
> I just released RISCVEMU, a 128 bit RISC-V emulator (RV128IMAFDQC base
> ISA). It is available at:
>
> http://bellard.org/riscvemu/
>
> Best regards,
>
> Fabrice.
>
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Michael Clark

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Dec 20, 2016, 9:22:18 PM12/20/16
to Madhu Macaque Labs, Andrew Waterman, Fabrice Bellard, RISC-V SW Dev
We will need an assembler and linker.

There is a model where the assembler selects 64-bit shifts and adds by default. i.e. add, addi are 64-bit and addq addiq are 128-bit, similarly for shifts. i.e. sllq, slliq, srlq, srliq for 128-bit. This would allow us to assemble output from a 64-bit compiler with an 128-bit assembler and 64-bit linker. Loads and stores already have width.

This model would be 64-bit ELF with 64-bit codegen and 128-bit inline asm, builtins, etc (fast memcpy, inline asm for bigint and crypto).

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Madhu Macaque Labs

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Dec 20, 2016, 9:37:01 PM12/20/16
to Michael Clark, Andrew Waterman, Fabrice Bellard, RISC-V SW Dev
This will work but does not meet the needs of those who want adressing greater than 64
bit for pers. mem type applications. But for  those kind of apps I guess we will have to
have dedicated functions and have some inline assembly instead of full toolchain
support.

On Wed, Dec 21, 2016 at 7:52 AM, Michael Clark <michae...@mac.com> wrote:
We will need an assembler and linker.

There is a model where the assembler selects 64-bit shifts and adds by default. i.e. add, addi are 64-bit and addq addiq are 128-bit, similarly for shifts. i.e. sllq, slliq, srlq, srliq for 128-bit. This would allow us to assemble output from a 64-bit compiler with an 128-bit assembler and 64-bit linker. Loads and stores already have width.

This model would be 64-bit ELF with 64-bit codegen and 128-bit inline asm, builtins, etc (fast memcpy, inline asm for bigint and crypto).

On 21 Dec 2016, at 3:05 PM, Madhu Macaque Labs <ma...@macaque.in> wrote:

That is going to be a pain ! We do need 128 bit support but only for specific addressing modes,
planning to use some hacks for that.  How much effort does it take to get GCC to support
128 bit ? If if its not too major a conceptual problem, I can take a stab at it. Helps
having tons of  interns ! And what would pointer sizes be ?
On Wed, Dec 21, 2016 at 5:27 AM, Andrew Waterman <and...@sifive.com> wrote:
Cool.  Now who's going to volunteer to make a 128-bit toolchain? :)

On Tue, Dec 20, 2016 at 1:56 AM, Fabrice Bellard <fab...@bellard.org> wrote:
> Hi,
>
> I just released RISCVEMU, a 128 bit RISC-V emulator (RV128IMAFDQC base
> ISA). It is available at:
>
> http://bellard.org/riscvemu/
>
> Best regards,
>
> Fabrice.
>
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Michael Clark

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Dec 20, 2016, 9:44:34 PM12/20/16
to Madhu Macaque Labs, Andrew Waterman, Fabrice Bellard, RISC-V SW Dev
Yes. For anyone who needs to address > 16 exbibytes. The Library of Congress could mmap their storage into a single address space.

I hope canonical pointers are not enforced for those of us who want lots of ASLR bits or metadata (or bounds).

Kito Cheng

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Dec 20, 2016, 9:53:37 PM12/20/16
to Michael Clark, Madhu Macaque Labs, Andrew Waterman, Fabrice Bellard, RISC-V SW Dev
​​The first problem is we don't have ELF128, and it's related binutils implementation yet,
gcc part is relative simple I guess, since there is already support 128 bit integer/floating point (TImode/TFmode in gcc term) in gcc.

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Madhu

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Samuel Falvo II

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Dec 20, 2016, 9:57:21 PM12/20/16
to Kito Cheng, Michael Clark, Madhu Macaque Labs, Andrew Waterman, Fabrice Bellard, RISC-V SW Dev
And here I was going to say that I can bang out a 128-bit version of
eForth 1.0 in about two or three days. ;)


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Samuel A. Falvo II

Madhu Macaque Labs

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Dec 20, 2016, 10:16:01 PM12/20/16
to Michael Clark, RISC-V SW Dev, Fabrice Bellard, Andrew Waterman
You do not  need to address that big a space. Single address space OSs  with sparse addressing will need greater than 64 bit addressing even for smaller memory sizes. Capability based systems without MMUs are getting there.

But I agree that this should not be the canonical case. But then again some of the address tricks you want to at for greater security may not be needed in a capability based sytem. You will just have a whole host of other headaches !

G S Madhusudan
Founder - Macaque Labs
www.macaque.in

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Samuel Falvo II

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Dec 20, 2016, 10:44:33 PM12/20/16
to Madhu Macaque Labs, Michael Clark, RISC-V SW Dev, Fabrice Bellard, Andrew Waterman
What do you mean by single address space OS with sparse addressing,
and how does that differ from non-sparse addressing?

I'm curious, because it brings to mind thoughts of how
POWER-architecture CPUs use "segment" registers/tables to expand a
process' linear address into a virtual address that is typically 80
bits wide, and page resolution happens from there. So, in effect,
POWER works by mapping multiple address spaces into a single virtual
address space, and page resolution works from that single address
space.

I know what you're describing is different, but I'm just trying to put
what you're describing into a context I'm already familiar with.
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Madhu Macaque Labs

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Dec 20, 2016, 11:04:59 PM12/20/16
to Samuel Falvo II, Michael Clark, RISC-V SW Dev, Fabrice Bellard, Andrew Waterman
Curious you should mention Power. Our RISC-V effort actually started as
a Power8 implementation using teh Power 8 addressing scheme you described
(in fact we still retain it in our codeline and our server grade part
may use this scheme instead of teh RISC-V scheme). Our project, SHAKTI is Sanskrit for
Power - that is how we got our name (the Power folks refused to license the
name).  We just simplified the micro-arch and changed execution to RISC-V.

You are right in that what I am envisaging is different but conceptually not that far off.
The Power and similar scheme give the illusion of multiple address spaces to the OS.
But when you add capabilities to an OS, the MMU no longer needs to perform its
security duties. So you can have a nice VIVT (or is it PIPT !) cache with no TLB.
The OS now controls the physical address space and with it inherits the attendant
headaches of how to assign linear non-virtual memory to processes. This will lead
to inefficient use of address spaces (this cannot be avoided) but a large linear address
space helps. Also makes sharing memory a breeze naturally. Persistent memory
also gets mapped into this unified address space (you will also  need a notion of
slow and fast pointers) . I am glossing over a lot of 
issues here but suffice to say that having a large virtual address space helps avoid
address space conflicts.

We are also toying with the idea of having HMC controllers with simple memory
management, so that the large address space is managed by the controller and the
CPUs just attach to specific parts of the address map. Will probably try out
a proto once we get our HMC enabled FPGA boards. In this scenario, the memory
has to boot first before the CPU can boot !


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Rishiyur Nikhil

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Dec 21, 2016, 11:01:40 AM12/21/16
to RISC-V SW Dev
See also this talk by Steve Wallach at the recent RISC-V workshop on
this topic:

    "3:30pm    128-bit addressing in RISC-V and security    Steve Wallach, Micron"
    https://riscv.org/wp-content/uploads/2016/11/Tue1530-128bit-Addr-RISC-V-Wallach-Micron.pdf

Nikhil



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John Leidel

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Dec 21, 2016, 11:14:38 AM12/21/16
to Madhu Macaque Labs, Samuel Falvo II, Michael Clark, RISC-V SW Dev, Fabrice Bellard, Andrew Waterman
Madhu, we've been toying with some partitioned address space methods using the RV128 model for GoblinCore.  Our memory system is based upon HMC.  Much of our research is geared towards how to efficiently couple HMC's to our RISC-V environment.  We actually have a small micro-controller running on a ZScale that does memory coalescing of disparate requests for HMCs.  




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ron minnich

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Dec 21, 2016, 11:18:17 AM12/21/16
to John Leidel, Madhu Macaque Labs, Samuel Falvo II, Michael Clark, RISC-V SW Dev, Fabrice Bellard, Andrew Waterman
If you can find the docs (I can't) Data General's AOS/VS ca. 1980 implemented a single address space, among other systems. It's a neat model and 128 bits should make it easy to get there. Lots of OS innovation from the 70s was lost in the 80s Unix tsunami ...



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John Leidel

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Dec 21, 2016, 11:28:55 AM12/21/16
to ron minnich, Madhu Macaque Labs, Samuel Falvo II, Michael Clark, RISC-V SW Dev, Fabrice Bellard, Andrew Waterman
Ron, DTIC has a report published on a later version of AOS/VS.  Not sure if Wallach would have those docs laying around anywhere, but it might be worth asking him.  


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Ray Van De Walker

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Dec 21, 2016, 6:00:40 PM12/21/16
to RISC-V SW Dev

It sure sounds like a single-level store with a channel controller.  The file system would easily fit in there as well, a la the IBM i-system and Atlas.

 

FYI, IBM’s i-system has a fully-developed security system that works with its 64-bit-addressed single-level store. It’s also old, already successfully ported from a 48-bit single-level store, and it’s been in long-term serial production.  So it’s not only fully debugged, the patents might be expired. i-systems have been using 64-bit Power cores for the last 15-20 years.

 

From: ron minnich [mailto:rmin...@gmail.com]

 

If you can find the docs (I can't) …

 

On Wed, Dec 21, 2016 at 8:14 AM John Leidel <john....@gmail.com> wrote:

Madhu, we've been toying with some partitioned address space methods using the RV128 model for GoblinCore. ..

.

Madhu Macaque Labs

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Dec 21, 2016, 8:20:25 PM12/21/16
to John Leidel, Samuel Falvo II, Michael Clark, RISC-V SW Dev, Fabrice Bellard, Andrew Waterman
This is really useful. I saw your paper earlier was waiting for some code to be released.
Not able to spend much time on this since I am under pressure to get 
some RISC-V design done for lower end applications. Are you using the open source
HMC controller ?

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John Leidel

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Dec 21, 2016, 9:16:38 PM12/21/16
to Madhu Macaque Labs, Samuel Falvo II, Michael Clark, RISC-V SW Dev, Fabrice Bellard, Andrew Waterman
Madhu, our plan is to build our own HMC controller.  We've worked with a number of commercial controllers (Altera, Pico, Convey, etc), but the openHMC controller is GNU GPL'd.  We're steering clear in order to remain an entirely BSD licensed hardware implementation.  We are considering building it using a similar approach to our DMC engine (ZScale + ucode).  

Madhu Macaque Labs

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Dec 21, 2016, 10:46:02 PM12/21/16
to John Leidel, Samuel Falvo II, Michael Clark, RISC-V SW Dev, Fabrice Bellard, Andrew Waterman
We can collaborate. We started building one and have some prelim code lying around.
It is BSD licensed but is in bluespec but we can share the design. Or if you
do it first we will just put a bluespec wrapper around it and use it !
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John Leidel

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Dec 22, 2016, 6:54:08 PM12/22/16
to Madhu Macaque Labs, Samuel Falvo II, Michael Clark, RISC-V SW Dev, Fabrice Bellard, Andrew Waterman
Madhu, I would be happy to collaborate.  I believe this would benefit the overall RISC-V community a great deal.  

cheers
john 

Madhu Macaque Labs

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Dec 24, 2016, 9:00:10 AM12/24/16
to John Leidel, Samuel Falvo II, Michael Clark, RISC-V SW Dev, Fabrice Bellard, Andrew Waterman
Can we start on a design approach, or do you already have a high level design done ?
Let me dig up our old specs and code. But it was a partly Mater's project, so not sure
how useful it would be, need to check.

The openHMC code may be GPL but can we do a BSD implementation ?
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Madhu

Fabrice Bellard

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Jan 9, 2017, 2:52:27 PM1/9/17
to sw-...@groups.riscv.org
A new version is available with VirtIO console, network, block device
and 9P filesystem. A network filesystem is supported to try a disk image
without downloading it.

Best regards,

Fabrice.

Michael Clark

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Jan 9, 2017, 6:46:13 PM1/9/17
to Fabrice Bellard, sw-...@groups.riscv.org
Hi Fabrice,

This is both awesome and annoying.

Annoying because I am still having trouble getting the emulator I am working on to work fully with upstream riscv-linux. However that’s my problem…

Awesome, well because it’s awesome to have a working example of VirtIO on RISC-V and an 128-bit emulator to boot.

I have discovered your riscv-linux patches directory now so will try to reproduce your config … on my emulator and Spike…

I also discovered that LQ was squeezed into the MISC-MEM. I had missed this very small comment on Page 106 of the ISA spec v2.1

"A LDU (load double unsigned) instruction is added using the existing LOAD major opcode, along
with new LQ and SQ instructions to load and store quadword values. SQ is added to the STORE
major opcode, while LQ is added to the MISC-MEM major opcode.”

I’ve updated my instruction listing, for RV128IMA, but still need to check the width values for the Q extension as I am not sure if they are documented yet:


Michael.

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