Access >4GB address in 32-bit M-mode?

[Bin Meng]

Hi,

I was wondering if it is possible to access >4GB address in 32-bit
M-mode. For S-mode, this can be done via MMU, but is this something
possible in M-mode?

Regards,
Bin

[Samuel Falvo II]

Not without platform specific extensions; for example, you could rely
on external memory banking logic, similar to earlier-generation home
computers like Commodore 128, Atari 8-bit series, or numerous game
consoles of that era.

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Samuel A. Falvo II

[Palmer Dabbelt]

My understanding is that MPRV will handle this. Here's the text from the spec

3.1.9
Memory Privilege in mstatus Register
The MPRV (Modify PRiVilege) bit modifies the privilege level at which loads and stores execute
in all privilege modes. When MPRV=0, translation and protection behave as normal. When
MPRV=1, load and store memory addresses are translated and protected as though the current
privilege mode were set to MPP. Instruction address-translation and protection are unaffected.
MPRV is hardwired to 0 if U-mode is not supported.

So I think all you need to do is set MPP and MPRV to get machine-mode accesses
to behave like supervisor-mode accesses. At that point you can set up the page
tables such that you can access whatever memory you want.

[Samuel Falvo II]

On Mon, Nov 5, 2018 at 11:03 AM Palmer Dabbelt <pal...@sifive.com> wrote:
> So I think all you need to do is set MPP and MPRV to get machine-mode accesses
> to behave like supervisor-mode accesses. At that point you can set up the page
> tables such that you can access whatever memory you want.

That's clever!! I never thought of that before, but you're right. I
stand corrected.

[Bin Meng]

Hi Palmer,

On Tue, Nov 6, 2018 at 3:03 AM Palmer Dabbelt <pal...@sifive.com> wrote:
>
> My understanding is that MPRV will handle this. Here's the text from the spec
>
> 3.1.9
> Memory Privilege in mstatus Register
> The MPRV (Modify PRiVilege) bit modifies the privilege level at which loads and stores execute
> in all privilege modes. When MPRV=0, translation and protection behave as normal. When
> MPRV=1, load and store memory addresses are translated and protected as though the current
> privilege mode were set to MPP. Instruction address-translation and protection are unaffected.
> MPRV is hardwired to 0 if U-mode is not supported.
>
> So I think all you need to do is set MPP and MPRV to get machine-mode accesses
> to behave like supervisor-mode accesses. At that point you can set up the page
> tables such that you can access whatever memory you want.
>

Thanks for the hints! However the spec does not explicitly mention
page table can be altered in such configuration. It only indicates
load/store memory will be translated to S-mode access which will go
through MMU. If as you say we can set up new page tables to access
>4GB memory in M-mode, I believe 'sfence.vma' is needed when modifying
the SATP register. But again the spec does not mention such
explicitly. In the spec 'sfence.vma' chapter indicates the instruction
is for S-mode, but it does not provide any indication on if MPRV is to
be used or not. Should such be clarified?

[Palmer Dabbelt]

On Mon, 05 Nov 2018 22:31:09 PST (-0800), bmen...@gmail.com wrote:
> Hi Palmer,
>
> On Tue, Nov 6, 2018 at 3:03 AM Palmer Dabbelt <pal...@sifive.com> wrote:
>>
>> My understanding is that MPRV will handle this. Here's the text from the spec
>>
>> 3.1.9
>> Memory Privilege in mstatus Register
>> The MPRV (Modify PRiVilege) bit modifies the privilege level at which loads and stores execute
>> in all privilege modes. When MPRV=0, translation and protection behave as normal. When
>> MPRV=1, load and store memory addresses are translated and protected as though the current
>> privilege mode were set to MPP. Instruction address-translation and protection are unaffected.
>> MPRV is hardwired to 0 if U-mode is not supported.
>>
>> So I think all you need to do is set MPP and MPRV to get machine-mode accesses
>> to behave like supervisor-mode accesses. At that point you can set up the page
>> tables such that you can access whatever memory you want.
>>
>
> Thanks for the hints! However the spec does not explicitly mention
> page table can be altered in such configuration. It only indicates
> load/store memory will be translated to S-mode access which will go
> through MMU. If as you say we can set up new page tables to access
>>4GB memory in M-mode, I believe 'sfence.vma' is needed when modifying
> the SATP register. But again the spec does not mention such
> explicitly. In the spec 'sfence.vma' chapter indicates the instruction
> is for S-mode, but it does not provide any indication on if MPRV is to
> be used or not. Should such be clarified?

This is a bit nuanced, but essentially the "supervisor" here doesn't mean
"supervisor instruction" but instead "supervisor translations" -- the
instructions available in machine mode are a superset of those available in
supervisor mode. So "sfence.vma" is valid from machine mode, and has the same
effect that "sfence.vma" does from supervisor mode.

So specifically: yes, you need an "sfence.vma" if modifying the page tables is
necessary to get access to the memory in question.

[Bin Meng]

Hi Palmer,

Thank you for the clarification!

Regards,
Bin