PDP-12/8I Memory Emulation

[Julian Nowaczek]

Hello everyone, it’s been a while! 

As you may remember, last Fall I was an EE undergrad awarded a research grant to design an emulated core memory expansion for UMD’s PDP-12. That project officially ended in December 2019, but through a lucky break I am now a graduate student in the UMD CS department, so I get to keep working on PDP-12 stuff! I was hoping to bounce a few ideas off you knowledgeable folks and get a sanity check before I go ahead and order the memory board. My project files are avaliable at https://github.com/jnowaczek/flipchip-cad if the embedded images don’t show up correctly.

A quick overview of my design:

• Storage (U3) is a Cypress CY14B104M nvSRAM. This part does include a real-time clock, but it’s cheaper on Digikey than the non-RTC version. C1 powers the memory chip during its automatic write to internal flash after losing power.
• U1 and U2 are 3.3V (5V tolerant) SN74LVCH16374A flip flops for data and address input.
• U4 is a SN74AHCT16373 5V TTL-level flip flop for data output.
• U5 is a TLV803 Voltage Supervisor to disable the memory during shutdown.
• N20 through N23 are flat flex cables leading to the other four memory expansion slots on the PDP-12 (the W021J board in the GitHub repo).
• IC1 is a Schmitt trigger buffer connected to the timing signals from the PDP-12 CP and IC2 inverts the signal after it passes through delay lines DL1 and DL2 to return to the CP.

I based my design off of the 32K Omnibus memory expansion that Vince Slyngstad, Stephen Lafferty, and Roland Huisman put together. Stephen’s writeup on his design proved particularly helpful, but there are still a couple things I am not sure about. 

Firstly, as far as I can tell the PDP-12 does not carry power over the memory expansion connectors as the expansion cabinet would have had its own supply. My understanding of the DEC convention is that pin A2 would carry +5 volts. Would it be appropriate to add a backplane wire to power the memory expansion in this manner, or would it be safer to leave the backplane alone and get power from somewhere else?

My second question concerns power filtering. I tested the 5V rail while the PDP-12 was running and there was next to no noise on the it. My current design is a 4 layer board with ground and power planes, do I need more power filtering capacitance similar to the 32K-Omnibus board? Right now I only have the amount of capacitance recommended by the voltage regulator reference design.

I’m hoping to get these and any other issues raised sorted out soon so we can finally run ADVENT! Thank you all for your time and energy, this project has been a fantastic learning opportunity!

Julian Nowaczek

[Jack Rubin]

Hi,

 

I’m not qualified to comment on the qualities of your design, but it seems like a great project. Have you provided a way to select/deselect 8K blocks of memory? That would allow your board to be intermingled with original core modules to aid in troubleshooting.

 

Jack

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[m pepper]

Julian,

I thought you would be hearing answers from others who have experience designing boards for M-series DEC hardware. I don't, so take what follows as non-expert advice.

1. regarding power to the board: I think adding a backplane wire to pin A2 is the cleanest way. One caution is to find a source that does not require touching existing wire wrap. If you have to piggyback onto another +5 pin, find one that has enough exposed pin for adding your wire. Even just sliding the existing wire wrap down the pin to make more room breaks the gas-tight binding and allows oxidation to form. Be sure you have proper wire wrap tools and if you are not experienced using a wire wrap gun, practice first.

2. regarding power noise filtering, follow the IC manufacturer's recommendations for adding Cap. near the chip. My experience with board layouts was with ECL where noise margins were quite small so I'm not up on what precautions are for today's TTL. So, in addition to power noise, our main concern was cross talk between long adjacent lines. Try to space clock pulses as far from other lines as possible.

3. regarding Jack's comments: a) I would think that 4K blocks are a more natural size for a PDP-12, but...   b) I'm not sure how select/deselect would be implemented in a practical way.

4. regarding my previous comment about bypassing the original memory: it might be the easiest and/or best method, but the suggestion was made without considering that you were using an existing interface designed for adding on to the original -- thus, the memory selection and data multiplexing are already provided. In our case with the SuperLINC, that was not the case.

     -maury-

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[Michael Thompson]

I would add some bypass caps next to the ICs. It wouldn't take much space and helps keep the local power planes quiet during signal switching.

Lots of capacitance on the output of the voltage regulator is always a good idea.

If you add a jumper to feed +5V to pin A2, it would be a good idea to have a fuse in the jumper. It could get really messy if one of the ribbons was installed correctly and it shorted +5V to ground.

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Michael Thompson

[Vincent Slyngstad]

I'm interested in these, or something like them, for my PDP-12.

Thanks,

Vince