Notes: 2026-07-15 QEMU/KVM subgroup meeting
Nathalie Chan King Choy
Attendance
Bill M
Edgar I
Ilias A
Joyce Q
Mark B
Nathalie CKC
Randy L
Sai Pavan B
Sumit S
Meeting Overview
To identify and discuss ARM-specific feature gaps in QEMU, focusing on emulation, platforms, and hypervisor enablement.
To review the public development roadmap and coordinate upcoming virtualized feature implementations across industry partners.
To assess the current meeting cadence and determine a more effective schedule for collaborative project tracking.
Key Decisions Made
The CoreCollective simulation subgroup meeting cadence is changed from bi-weekly to monthly, with the next session scheduled for August 15th.
The timing API and plugin design discussions will be elevated to the wider QEMU KVM upstream community call on August 4th.
[Deferred] Deeper coordination and technical planning for QVisor are deferred until representatives from AWS can be successfully integrated into the meetings.
Action Items
Alex B.
Reach out directly to Alex G. (AWS) to invite him to join the CoreCollective meetings for the QVisor collaboration.
Share the presentation slides with the group members.
Review the downstream SMMU platform device patch series once received from Edgar I.
Ping Pierrick, Mark B., and Phil ahead of the August 4th upstream community call to coordinate the timing API discussion.
Edgar I.
Share the downstream SMMU platform device patch series privately with Alex B.
Mark B.
Reach out to Alex G. (AWS) alongside Alex B. to encourage his participation in the QVisor project.
Evaluate personal and team scheduling constraints to determine if attendance is feasible for the KVM Forum or DVCon.
Sai P.
Present the shared slides and feature roadmap during the next internal AMD call to identify further QEMU requirements.
For Future
Discuss the timing API and plugin architecture at the upstream QEMU KVM community call on August 4th.
Convene the next monthly CoreCollective simulation subgroup meeting on August 15th.
Notes
Roadmap and CPU Feature Gaps
The roadmap remains public to prevent development overlap, though specific funding entities are kept confidential at customer request.
PoE overlay extensions are provisionally scheduled on the roadmap, but PoE2 is delayed pending the public release of the official ARM specifications.
Emulating the Neoverse V3 core inside the ARM AGI processor requires several additions to QEMU.
Features like the const pack field algorithm and branch history control will be implemented as no-ops since QEMU does not model microarchitectural performance or branch prediction.
Modeling the memory partitioning and monitoring extension represents the largest emulation gap currently missing in QEMU.
Additional customer-requested feature gaps include the translation hardening extension, the virtual memory tagging extension, and improved fine-grained traps support.
DCC UART Support
AMD internal teams requested DCC UART support from the CoreSight side to enable logging during early boot phases before any standard subsystems are active.
This feature allows early boot images to be validated in QEMU prior to silicon tape-out.
DCC UART differs from the standard PL11 UART because it routes data directly over JTAG.
While semi-hosting is an alternative early bring-up technology that works over JTAG, silicon teams with pre-existing DCC infrastructure are unlikely to switch.
Platform SMMU Support
Edgar I. maintains downstream forked patches to support SMMU for non-PCI platform devices.
In this downstream model, DMA devices write to a shared address space, and the SMMU reads transaction attributes to identify the streaming ID and apply translations.
The upstream QEMU PCI model assigns a separate address space per requester ID, which creates integration issues on the CPU-visible side of the TBU.
Edgar I. has developed two versions of this patch series, including one that implements a per-address-space approach for platform devices.
Timing API and Latency Tools
Plugins can be utilized in QEMU to trace instructions and identify the longest execution paths where interrupts are disabled.
The current timing API is considered broken, and the group discussed designing a cleaner, direct API replacement rather than patching the existing code.
QEMU's iCount mechanism currently supports three modes: round-robin (deterministic), a nominal megahertz clock speed adjustment mode (which is overly complex), and a per-CPU instruction budget mechanism.
Qualcomm is actively evaluating the existing plugin API and timing implementation to propose a functional solution.
Industry Events and Face-to-Face Planning
The KVM Forum is taking place in Vancouver, Canada, which provides a low-cost attendance option for local participants.
Mark B. raised the possibility of a face-to-face team meeting at DVCon in November, though its scheduling immediately following the KVM Forum may present travel conflicts.