BACKPORT: drm/i915: enable intel_lvds->pre_pll_enable for il... [chromiumos/third_party/kernel-next : chromeos-3.8]

[Josh Triplett (Code Review)]

Josh Triplett has uploaded a new change for review.

https://gerrit.chromium.org/gerrit/56429


Change subject: BACKPORT: drm/i915: enable intel_lvds->pre_pll_enable for ilk+, too
......................................................................

BACKPORT: drm/i915: enable intel_lvds->pre_pll_enable for ilk+, too

Only two things needed adjustment:
- pipe select for PCH_CPT
- There's no dithering bit on ilk+ in the lvds ctl reg

Reviewed-by: Paulo Zanoni <paulo.r...@intel.com>
Signed-off-by: Daniel Vetter <daniel...@ffwll.ch>
(cherry picked from commit 62810e5a9df3f47b7261e5d78fc1c33e550f2171)

BUG=chrome-os-partner:19682
TEST=With entire patch series applied, observe PC7 residency via powertop in
crosh.
Change-Id: I0d71228384e98d06dc7f9bffc8eccf6da35bd627
---
M drivers/gpu/drm/i915/intel_display.c
M drivers/gpu/drm/i915/intel_lvds.c
2 files changed, 15 insertions(+), 49 deletions(-)


git pull ssh://gerrit.chromium.org:29418/chromiumos/third_party/kernel-next refs/changes/29/56429/1

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 85b02d9..1ce6110 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5534,7 +5534,6 @@
bool ok, has_reduced_clock = false;
bool is_lvds = false, is_dp = false, is_cpu_edp = false;
struct intel_encoder *encoder;
- u32 temp;
int ret;
bool dither, fdi_config_ok;

@@ -5597,45 +5596,6 @@
}
} else
intel_put_pch_pll(intel_crtc);
-
- /* The LVDS pin pair needs to be on before the DPLLs are enabled.
- * This is an exception to the general rule that mode_set doesn't turn
- * things on.
- */
- if (is_lvds) {
- temp = I915_READ(PCH_LVDS);
- temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
- if (HAS_PCH_CPT(dev)) {
- temp &= ~PORT_TRANS_SEL_MASK;
- temp |= PORT_TRANS_SEL_CPT(pipe);
- } else {
- if (pipe == 1)
- temp |= LVDS_PIPEB_SELECT;
- else
- temp &= ~LVDS_PIPEB_SELECT;
- }
-
- /* set the corresponsding LVDS_BORDER bit */
- temp |= dev_priv->lvds_border_bits;
- /* Set the B0-B3 data pairs corresponding to whether we're going to
- * set the DPLLs for dual-channel mode or not.
- */
- if (clock.p2 == 7)
- temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
- else
- temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
-
- /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
- * appropriately here, but we need to look more thoroughly into how
- * panels behave in the two modes.
- */
- temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
- if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
- temp |= LVDS_HSYNC_POLARITY;
- if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
- temp |= LVDS_VSYNC_POLARITY;
- I915_WRITE(PCH_LVDS, temp);
- }

if (is_dp && !is_cpu_edp) {
intel_dp_set_m_n(crtc, mode, adjusted_mode);
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 0e5fdd3..b182633 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -104,17 +104,20 @@
int pipe = intel_crtc->pipe;
u32 temp;

- /* pch split platforms are not yet converted. */
- if (HAS_PCH_SPLIT(dev))
- return;
-
temp = I915_READ(lvds_encoder->reg);
temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
- if (pipe == 1) {
- temp |= LVDS_PIPEB_SELECT;
+
+ if (HAS_PCH_CPT(dev)) {
+ temp &= ~PORT_TRANS_SEL_MASK;
+ temp |= PORT_TRANS_SEL_CPT(pipe);
} else {
- temp &= ~LVDS_PIPEB_SELECT;
+ if (pipe == 1) {
+ temp |= LVDS_PIPEB_SELECT;
+ } else {
+ temp &= ~LVDS_PIPEB_SELECT;
+ }
}
+
/* set the corresponsding LVDS_BORDER bit */
temp |= dev_priv->lvds_border_bits;
/* Set the B0-B3 data pairs corresponding to whether we're going to
@@ -129,8 +132,11 @@
* appropriately here, but we need to look more thoroughly into how
* panels behave in the two modes.
*/
- /* set the dithering flag on LVDS as needed */
- if (INTEL_INFO(dev)->gen >= 4) {
+
+ /* Set the dithering flag on LVDS as needed, note that there is no
+ * special lvds dither control bit on pch-split platforms, dithering is
+ * only controlled through the PIPECONF reg. */
+ if (INTEL_INFO(dev)->gen == 4) {
if (dev_priv->lvds_dither)
temp |= LVDS_ENABLE_DITHER;
else

--
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I0d71228384e98d06dc7f9bffc8eccf6da35bd627
Gerrit-PatchSet: 1
Gerrit-Project: chromiumos/third_party/kernel-next
Gerrit-Branch: chromeos-3.8
Gerrit-Owner: Josh Triplett <jo...@joshtriplett.org>

[Josh Triplett (Code Review)]

Josh Triplett has posted comments on this change.

Change subject: BACKPORT: drm/i915: enable intel_lvds->pre_pll_enable for ilk+, too
......................................................................

Patch Set 1: Verified

--
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Gerrit-MessageType: comment

Gerrit-Change-Id: I0d71228384e98d06dc7f9bffc8eccf6da35bd627
Gerrit-PatchSet: 1
Gerrit-Project: chromiumos/third_party/kernel-next
Gerrit-Branch: chromeos-3.8
Gerrit-Owner: Josh Triplett <jo...@joshtriplett.org>

Gerrit-Reviewer: ChromeBot <chrom...@google.com>
Gerrit-Reviewer: Josh Triplett <jo...@joshtriplett.org>
Gerrit-Reviewer: Olof Johansson <ol...@chromium.org>
Gerrit-Reviewer: Sonny Rao <sonn...@chromium.org>
Gerrit-Reviewer: Stéphane Marchesin <mar...@chromium.org>
Gerrit-Reviewer: sna...@google.com

[Stéphane Marchesin (Code Review)]

Stéphane Marchesin has posted comments on this change.

Change subject: BACKPORT: drm/i915: enable intel_lvds->pre_pll_enable for ilk+, too
......................................................................

Patch Set 1: Looks good to me, approved

--
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Gerrit-MessageType: comment

Gerrit-Change-Id: I0d71228384e98d06dc7f9bffc8eccf6da35bd627
Gerrit-PatchSet: 1
Gerrit-Project: chromiumos/third_party/kernel-next
Gerrit-Branch: chromeos-3.8
Gerrit-Owner: Josh Triplett <jo...@joshtriplett.org>

[Josh Triplett (Code Review)]

Josh Triplett has posted comments on this change.

Change subject: BACKPORT: drm/i915: enable intel_lvds->pre_pll_enable for ilk+, too
......................................................................

Patch Set 1: Ready

--
To view, visit https://gerrit.chromium.org/gerrit/56429
To unsubscribe, visit https://gerrit.chromium.org/gerrit/settings

Gerrit-MessageType: comment

Gerrit-Change-Id: I0d71228384e98d06dc7f9bffc8eccf6da35bd627
Gerrit-PatchSet: 1
Gerrit-Project: chromiumos/third_party/kernel-next
Gerrit-Branch: chromeos-3.8
Gerrit-Owner: Josh Triplett <jo...@joshtriplett.org>