BACKPORT: drm/i915: rip out pre-DDI stuff from haswell_crtc_... [chromiumos/third_party/kernel-next : chromeos-3.8]
1 view
Skip to first unread message
Josh Triplett (Code Review)
May 23, 2013, 2:24:48 PM5/23/13
to Olof Johansson
Josh Triplett has uploaded a new change for review.
https://gerrit.chromium.org/gerrit/56432
Change subject: BACKPORT: drm/i915: rip out pre-DDI stuff from haswell_crtc_mode_set
......................................................................
BACKPORT: drm/i915: rip out pre-DDI stuff from haswell_crtc_mode_set
Especially getting rid of all things lvds is ... great!
v2: Drop the two additional pre-hsw hunks noticed by Paulo Zanoni.
v3:
- handle DP ports correctly (spoted by Paulo)
- don't leave {} behind for a single-line block (again spotted by
Paulo)
- kill another if (IBX || CPT) block
Reviewed-by: Paulo Zanoni <paulo.r...@intel.com>
Signed-off-by: Daniel Vetter <daniel...@ffwll.ch>
(cherry picked from commit ed7ef43989b3a8235b1cbf1e2b025aa4af3368a6)
BUG=chrome-os-partner:19682
TEST=With entire patch series applied, observe PC7 residency via powertop in
crosh.
Change-Id: Ib93d20d01f01664c0c65fbfbf5d111d3d17b4cf0
---
M drivers/gpu/drm/i915/intel_display.c
1 file changed, 2 insertions(+), 126 deletions(-)
git pull ssh://gerrit.chromium.org:29418/chromiumos/third_party/kernel-next refs/changes/32/56432/1
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 8f51fd6..9d32cf2 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5676,20 +5676,13 @@
int pipe = intel_crtc->pipe;
int plane = intel_crtc->plane;
int num_connectors = 0;
- intel_clock_t clock, reduced_clock;
- u32 dpll = 0, fp = 0, fp2 = 0;
- bool ok, has_reduced_clock = false;
- bool is_lvds = false, is_dp = false, is_cpu_edp = false;
+ bool is_dp = false, is_cpu_edp = false;
struct intel_encoder *encoder;
- u32 temp;
int ret;
bool dither;
for_each_encoder_on_crtc(dev, crtc, encoder) {
switch (encoder->type) {
- case INTEL_OUTPUT_LVDS:
- is_lvds = true;
- break;
case INTEL_OUTPUT_DISPLAYPORT:
is_dp = true;
break;
@@ -5723,142 +5716,25 @@
if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
return -EINVAL;
- if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
- ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
- &has_reduced_clock,
- &reduced_clock);
- if (!ok) {
- DRM_ERROR("Couldn't find PLL settings for mode!\n");
- return -EINVAL;
- }
- }
-
/* Ensure that the cursor is valid for the new mode before changing... */
intel_crtc_update_cursor(crtc, true);
/* determine panel color depth */
dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
adjusted_mode);
- if (is_lvds && dev_priv->lvds_dither)
- dither = true;
DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
drm_mode_debug_printmodeline(mode);
- if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
- fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
- if (has_reduced_clock)
- fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
- reduced_clock.m2;
-
- dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
- fp);
-
- /* CPU eDP is the only output that doesn't need a PCH PLL of its
- * own on pre-Haswell/LPT generation */
- if (!is_cpu_edp) {
- struct intel_pch_pll *pll;
-
- pll = intel_get_pch_pll(intel_crtc, dpll, fp);
- if (pll == NULL) {
- DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
- pipe);
- return -EINVAL;
- }
- } else
- intel_put_pch_pll(intel_crtc);
-
- /* The LVDS pin pair needs to be on before the DPLLs are
- * enabled. This is an exception to the general rule that
- * mode_set doesn't turn things on.
- */
- if (is_lvds) {
- temp = I915_READ(PCH_LVDS);
- temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
- if (HAS_PCH_CPT(dev)) {
- temp &= ~PORT_TRANS_SEL_MASK;
- temp |= PORT_TRANS_SEL_CPT(pipe);
- } else {
- if (pipe == 1)
- temp |= LVDS_PIPEB_SELECT;
- else
- temp &= ~LVDS_PIPEB_SELECT;
- }
-
- /* set the corresponsding LVDS_BORDER bit */
- temp |= dev_priv->lvds_border_bits;
- /* Set the B0-B3 data pairs corresponding to whether
- * we're going to set the DPLLs for dual-channel mode or
- * not.
- */
- if (clock.p2 == 7)
- temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
- else
- temp &= ~(LVDS_B0B3_POWER_UP |
- LVDS_CLKB_POWER_UP);
-
- /* It would be nice to set 24 vs 18-bit mode
- * (LVDS_A3_POWER_UP) appropriately here, but we need to
- * look more thoroughly into how panels behave in the
- * two modes.
- */
- temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
- if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
- temp |= LVDS_HSYNC_POLARITY;
- if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
- temp |= LVDS_VSYNC_POLARITY;
- I915_WRITE(PCH_LVDS, temp);
- }
- }
-
- if (is_dp && !is_cpu_edp) {
+ if (is_dp && !is_cpu_edp)
intel_dp_set_m_n(crtc, mode, adjusted_mode);
- } else {
- if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
- /* For non-DP output, clear any trans DP clock recovery
- * setting.*/
- I915_WRITE(TRANSDATA_M1(pipe), 0);
- I915_WRITE(TRANSDATA_N1(pipe), 0);
- I915_WRITE(TRANSDPLINK_M1(pipe), 0);
- I915_WRITE(TRANSDPLINK_N1(pipe), 0);
- }
- }
intel_crtc->lowfreq_avail = false;
- if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
- if (intel_crtc->pch_pll) {
- I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
-
- /* Wait for the clocks to stabilize. */
- POSTING_READ(intel_crtc->pch_pll->pll_reg);
- udelay(150);
-
- /* The pixel multiplier can only be updated once the
- * DPLL is enabled and the clocks are stable.
- *
- * So write it again.
- */
- I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
- }
-
- if (intel_crtc->pch_pll) {
- if (is_lvds && has_reduced_clock && i915_powersave) {
- I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
- intel_crtc->lowfreq_avail = true;
- } else {
- I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
- }
- }
- }
intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
if (!is_dp || is_cpu_edp)
ironlake_set_m_n(crtc, mode, adjusted_mode);
-
- if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
- if (is_cpu_edp)
- ironlake_set_pll_edp(crtc, adjusted_mode->clock);
haswell_set_pipeconf(crtc, adjusted_mode, dither);
--
To view, visit https://gerrit.chromium.org/gerrit/56432
To unsubscribe, visit https://gerrit.chromium.org/gerrit/settings
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ib93d20d01f01664c0c65fbfbf5d111d3d17b4cf0
Gerrit-PatchSet: 1
Gerrit-Project: chromiumos/third_party/kernel-next
Gerrit-Branch: chromeos-3.8
Gerrit-Owner: Josh Triplett <jo...@joshtriplett.org>
https://gerrit.chromium.org/gerrit/56432
Change subject: BACKPORT: drm/i915: rip out pre-DDI stuff from haswell_crtc_mode_set
......................................................................
BACKPORT: drm/i915: rip out pre-DDI stuff from haswell_crtc_mode_set
Especially getting rid of all things lvds is ... great!
v2: Drop the two additional pre-hsw hunks noticed by Paulo Zanoni.
v3:
- handle DP ports correctly (spoted by Paulo)
- don't leave {} behind for a single-line block (again spotted by
Paulo)
- kill another if (IBX || CPT) block
Reviewed-by: Paulo Zanoni <paulo.r...@intel.com>
Signed-off-by: Daniel Vetter <daniel...@ffwll.ch>
(cherry picked from commit ed7ef43989b3a8235b1cbf1e2b025aa4af3368a6)
BUG=chrome-os-partner:19682
TEST=With entire patch series applied, observe PC7 residency via powertop in
crosh.
Change-Id: Ib93d20d01f01664c0c65fbfbf5d111d3d17b4cf0
---
M drivers/gpu/drm/i915/intel_display.c
1 file changed, 2 insertions(+), 126 deletions(-)
git pull ssh://gerrit.chromium.org:29418/chromiumos/third_party/kernel-next refs/changes/32/56432/1
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 8f51fd6..9d32cf2 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5676,20 +5676,13 @@
int pipe = intel_crtc->pipe;
int plane = intel_crtc->plane;
int num_connectors = 0;
- intel_clock_t clock, reduced_clock;
- u32 dpll = 0, fp = 0, fp2 = 0;
- bool ok, has_reduced_clock = false;
- bool is_lvds = false, is_dp = false, is_cpu_edp = false;
+ bool is_dp = false, is_cpu_edp = false;
struct intel_encoder *encoder;
- u32 temp;
int ret;
bool dither;
for_each_encoder_on_crtc(dev, crtc, encoder) {
switch (encoder->type) {
- case INTEL_OUTPUT_LVDS:
- is_lvds = true;
- break;
case INTEL_OUTPUT_DISPLAYPORT:
is_dp = true;
break;
@@ -5723,142 +5716,25 @@
if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
return -EINVAL;
- if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
- ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
- &has_reduced_clock,
- &reduced_clock);
- if (!ok) {
- DRM_ERROR("Couldn't find PLL settings for mode!\n");
- return -EINVAL;
- }
- }
-
/* Ensure that the cursor is valid for the new mode before changing... */
intel_crtc_update_cursor(crtc, true);
/* determine panel color depth */
dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
adjusted_mode);
- if (is_lvds && dev_priv->lvds_dither)
- dither = true;
DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
drm_mode_debug_printmodeline(mode);
- if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
- fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
- if (has_reduced_clock)
- fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
- reduced_clock.m2;
-
- dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
- fp);
-
- /* CPU eDP is the only output that doesn't need a PCH PLL of its
- * own on pre-Haswell/LPT generation */
- if (!is_cpu_edp) {
- struct intel_pch_pll *pll;
-
- pll = intel_get_pch_pll(intel_crtc, dpll, fp);
- if (pll == NULL) {
- DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
- pipe);
- return -EINVAL;
- }
- } else
- intel_put_pch_pll(intel_crtc);
-
- /* The LVDS pin pair needs to be on before the DPLLs are
- * enabled. This is an exception to the general rule that
- * mode_set doesn't turn things on.
- */
- if (is_lvds) {
- temp = I915_READ(PCH_LVDS);
- temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
- if (HAS_PCH_CPT(dev)) {
- temp &= ~PORT_TRANS_SEL_MASK;
- temp |= PORT_TRANS_SEL_CPT(pipe);
- } else {
- if (pipe == 1)
- temp |= LVDS_PIPEB_SELECT;
- else
- temp &= ~LVDS_PIPEB_SELECT;
- }
-
- /* set the corresponsding LVDS_BORDER bit */
- temp |= dev_priv->lvds_border_bits;
- /* Set the B0-B3 data pairs corresponding to whether
- * we're going to set the DPLLs for dual-channel mode or
- * not.
- */
- if (clock.p2 == 7)
- temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
- else
- temp &= ~(LVDS_B0B3_POWER_UP |
- LVDS_CLKB_POWER_UP);
-
- /* It would be nice to set 24 vs 18-bit mode
- * (LVDS_A3_POWER_UP) appropriately here, but we need to
- * look more thoroughly into how panels behave in the
- * two modes.
- */
- temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
- if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
- temp |= LVDS_HSYNC_POLARITY;
- if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
- temp |= LVDS_VSYNC_POLARITY;
- I915_WRITE(PCH_LVDS, temp);
- }
- }
-
- if (is_dp && !is_cpu_edp) {
+ if (is_dp && !is_cpu_edp)
intel_dp_set_m_n(crtc, mode, adjusted_mode);
- } else {
- if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
- /* For non-DP output, clear any trans DP clock recovery
- * setting.*/
- I915_WRITE(TRANSDATA_M1(pipe), 0);
- I915_WRITE(TRANSDATA_N1(pipe), 0);
- I915_WRITE(TRANSDPLINK_M1(pipe), 0);
- I915_WRITE(TRANSDPLINK_N1(pipe), 0);
- }
- }
intel_crtc->lowfreq_avail = false;
- if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
- if (intel_crtc->pch_pll) {
- I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
-
- /* Wait for the clocks to stabilize. */
- POSTING_READ(intel_crtc->pch_pll->pll_reg);
- udelay(150);
-
- /* The pixel multiplier can only be updated once the
- * DPLL is enabled and the clocks are stable.
- *
- * So write it again.
- */
- I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
- }
-
- if (intel_crtc->pch_pll) {
- if (is_lvds && has_reduced_clock && i915_powersave) {
- I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
- intel_crtc->lowfreq_avail = true;
- } else {
- I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
- }
- }
- }
intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
if (!is_dp || is_cpu_edp)
ironlake_set_m_n(crtc, mode, adjusted_mode);
-
- if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
- if (is_cpu_edp)
- ironlake_set_pll_edp(crtc, adjusted_mode->clock);
haswell_set_pipeconf(crtc, adjusted_mode, dither);
--
To view, visit https://gerrit.chromium.org/gerrit/56432
To unsubscribe, visit https://gerrit.chromium.org/gerrit/settings
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ib93d20d01f01664c0c65fbfbf5d111d3d17b4cf0
Gerrit-PatchSet: 1
Gerrit-Project: chromiumos/third_party/kernel-next
Gerrit-Branch: chromeos-3.8
Gerrit-Owner: Josh Triplett <jo...@joshtriplett.org>
Josh Triplett (Code Review)
May 23, 2013, 2:30:13 PM5/23/13
to ChromeBot, Olof Johansson, Sonny Rao, sna...@google.com, Stéphane Marchesin
Josh Triplett has posted comments on this change.
Change subject: BACKPORT: drm/i915: rip out pre-DDI stuff from haswell_crtc_mode_set
......................................................................
Patch Set 1: Verified
--
To view, visit https://gerrit.chromium.org/gerrit/56432
To unsubscribe, visit https://gerrit.chromium.org/gerrit/settings
Gerrit-MessageType: comment
Gerrit-Reviewer: Josh Triplett <jo...@joshtriplett.org>
Gerrit-Reviewer: Olof Johansson <ol...@chromium.org>
Gerrit-Reviewer: Sonny Rao <sonn...@chromium.org>
Gerrit-Reviewer: Stéphane Marchesin <mar...@chromium.org>
Gerrit-Reviewer: sna...@google.com
Change subject: BACKPORT: drm/i915: rip out pre-DDI stuff from haswell_crtc_mode_set
......................................................................
--
To view, visit https://gerrit.chromium.org/gerrit/56432
To unsubscribe, visit https://gerrit.chromium.org/gerrit/settings
Gerrit-Change-Id: Ib93d20d01f01664c0c65fbfbf5d111d3d17b4cf0
Gerrit-PatchSet: 1
Gerrit-Project: chromiumos/third_party/kernel-next
Gerrit-Branch: chromeos-3.8
Gerrit-Owner: Josh Triplett <jo...@joshtriplett.org>
Gerrit-Reviewer: ChromeBot <chrom...@google.com>
Gerrit-PatchSet: 1
Gerrit-Project: chromiumos/third_party/kernel-next
Gerrit-Branch: chromeos-3.8
Gerrit-Owner: Josh Triplett <jo...@joshtriplett.org>
Gerrit-Reviewer: Josh Triplett <jo...@joshtriplett.org>
Gerrit-Reviewer: Olof Johansson <ol...@chromium.org>
Gerrit-Reviewer: Sonny Rao <sonn...@chromium.org>
Gerrit-Reviewer: Stéphane Marchesin <mar...@chromium.org>
Gerrit-Reviewer: sna...@google.com
Stéphane Marchesin (Code Review)
May 23, 2013, 11:52:26 PM5/23/13
to Josh Triplett, ChromeBot, Olof Johansson, Sonny Rao, sna...@google.com
Stéphane Marchesin has posted comments on this change.
Change subject: BACKPORT: drm/i915: rip out pre-DDI stuff from haswell_crtc_mode_set
......................................................................
Patch Set 1: Looks good to me, approved
--
To view, visit https://gerrit.chromium.org/gerrit/56432
To unsubscribe, visit https://gerrit.chromium.org/gerrit/settings
Gerrit-MessageType: comment
Change subject: BACKPORT: drm/i915: rip out pre-DDI stuff from haswell_crtc_mode_set
......................................................................
--
To view, visit https://gerrit.chromium.org/gerrit/56432
To unsubscribe, visit https://gerrit.chromium.org/gerrit/settings
Gerrit-Change-Id: Ib93d20d01f01664c0c65fbfbf5d111d3d17b4cf0
Gerrit-PatchSet: 1
Gerrit-Project: chromiumos/third_party/kernel-next
Gerrit-Branch: chromeos-3.8
Gerrit-Owner: Josh Triplett <jo...@joshtriplett.org>
Gerrit-PatchSet: 1
Gerrit-Project: chromiumos/third_party/kernel-next
Gerrit-Branch: chromeos-3.8
Gerrit-Owner: Josh Triplett <jo...@joshtriplett.org>
Josh Triplett (Code Review)
May 24, 2013, 3:34:26 AM5/24/13
to ChromeBot, Olof Johansson, Sonny Rao, sna...@google.com, Stéphane Marchesin
Josh Triplett has posted comments on this change.
Change subject: BACKPORT: drm/i915: rip out pre-DDI stuff from haswell_crtc_mode_set
......................................................................
Patch Set 1: Ready
--
To view, visit https://gerrit.chromium.org/gerrit/56432
To unsubscribe, visit https://gerrit.chromium.org/gerrit/settings
Gerrit-MessageType: comment
Change subject: BACKPORT: drm/i915: rip out pre-DDI stuff from haswell_crtc_mode_set
......................................................................
--
To view, visit https://gerrit.chromium.org/gerrit/56432
To unsubscribe, visit https://gerrit.chromium.org/gerrit/settings
Gerrit-Change-Id: Ib93d20d01f01664c0c65fbfbf5d111d3d17b4cf0
Gerrit-PatchSet: 1
Gerrit-Project: chromiumos/third_party/kernel-next
Gerrit-Branch: chromeos-3.8
Gerrit-Owner: Josh Triplett <jo...@joshtriplett.org>
Gerrit-PatchSet: 1
Gerrit-Project: chromiumos/third_party/kernel-next
Gerrit-Branch: chromeos-3.8
Gerrit-Owner: Josh Triplett <jo...@joshtriplett.org>
Reply all
Reply to author
Forward
0 new messages