UPSTREAM: intel/amenia: Program EMMC dll setting [chromiumos/third

Aaron Durbin (Gerrit)

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Jun 9, 2016, 9:50:29 PM6/9/16

to Lijian Zhao

Aaron Durbin has uploaded a new change for review.

https://chromium-review.googlesource.com/351375

Change subject: UPSTREAM: intel/amenia: Program EMMC dll setting
......................................................................

UPSTREAM: intel/amenia: Program EMMC dll setting

EMMC TX DATA Control needs to be programmed to 0x1A1A to make amenia
system can run stable on EMMC with HS400 mode.

BUG=None
BRANCH=None
TEST=None

Change-Id: I42c23ff7e6956e75de5e1b1339a570b35d999301
Original-Signed-off-by: Zhao, Lijian <lijia...@intel.com>
Original-Tested-by: Petrov, Andrey <andrey...@intel.com>
Original-Reviewed-on: https://review.coreboot.org/15092
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adu...@chromium.org>
Signed-off-by: Aaron Durbin <adu...@chromium.org>
---
M src/mainboard/intel/amenia/devicetree.cb
1 file changed, 5 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/intel/amenia/devicetree.cb
b/src/mainboard/intel/amenia/devicetree.cb
index af06848..8128c71 100644
--- a/src/mainboard/intel/amenia/devicetree.cb
+++ b/src/mainboard/intel/amenia/devicetree.cb
@@ -10,6 +10,11 @@
# Integrated Sensor Hub
register "integrated_sensor_hub_enable" = "0"

+ # EMMC TX DATA Delay 1#
+ # 0x1A[14:8] stands for 26*125 = 3250 pSec delay for HS400
+ # 0x1A[6:0] stands for 26*125 = 3250 pSec delay for SDR104/HS200
+ register "emmc_tx_data_cntl1" = "0x1A1A" # HS400 required
+
device domain 0 on
device pci 00.0 on end # - Host Bridge
device pci 00.1 on end # - DPTF

--
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I42c23ff7e6956e75de5e1b1339a570b35d999301
Gerrit-PatchSet: 1
Gerrit-Project: chromiumos/third_party/coreboot
Gerrit-Branch: chromeos-2016.05
Gerrit-Owner: Aaron Durbin <adu...@chromium.org>
Gerrit-Reviewer: Lijian Zhao <lijia...@intel.com>

Duncan Laurie (Gerrit)

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Jun 9, 2016, 10:01:29 PM6/9/16

to Aaron Durbin, Lijian Zhao, Duncan Laurie

Duncan Laurie has posted comments on this change.

Change subject: UPSTREAM: intel/amenia: Program EMMC dll setting
......................................................................

Patch Set 1: Code-Review+2

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Gerrit-MessageType: comment

Gerrit-Change-Id: I42c23ff7e6956e75de5e1b1339a570b35d999301
Gerrit-PatchSet: 1
Gerrit-Project: chromiumos/third_party/coreboot
Gerrit-Branch: chromeos-2016.05
Gerrit-Owner: Aaron Durbin <adu...@chromium.org>

Gerrit-Reviewer: Duncan Laurie <dla...@chromium.org>
Gerrit-Reviewer: Lijian Zhao <lijia...@intel.com>
Gerrit-HasComments: No

Aaron Durbin (Gerrit)

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Jun 9, 2016, 10:13:06 PM6/9/16

to Lijian Zhao, Duncan Laurie

Aaron Durbin has posted comments on this change.

Change subject: UPSTREAM: intel/amenia: Program EMMC dll setting
......................................................................

Patch Set 1: Verified+1 Commit-Queue+1

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Gerrit-MessageType: comment

Gerrit-Change-Id: I42c23ff7e6956e75de5e1b1339a570b35d999301
Gerrit-PatchSet: 1
Gerrit-Project: chromiumos/third_party/coreboot
Gerrit-Branch: chromeos-2016.05
Gerrit-Owner: Aaron Durbin <adu...@chromium.org>

Gerrit-Reviewer: Aaron Durbin <adu...@chromium.org>

ChromeOS Commit Bot (Gerrit)

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Jun 10, 2016, 3:19:55 AM6/10/16

to Aaron Durbin, Lijian Zhao, Duncan Laurie

Hello Aaron Durbin, Duncan Laurie,

I'd like you to reexamine a change. Please visit

https://chromium-review.googlesource.com/351375

to look at the new patch set (#2).

Change subject: UPSTREAM: intel/amenia: Program EMMC dll setting
......................................................................

UPSTREAM: intel/amenia: Program EMMC dll setting

EMMC TX DATA Control needs to be programmed to 0x1A1A to make amenia
system can run stable on EMMC with HS400 mode.

BUG=None
BRANCH=None
TEST=None

Change-Id: I42c23ff7e6956e75de5e1b1339a570b35d999301
Original-Signed-off-by: Zhao, Lijian <lijia...@intel.com>
Original-Tested-by: Petrov, Andrey <andrey...@intel.com>
Original-Reviewed-on: https://review.coreboot.org/15092
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adu...@chromium.org>
Signed-off-by: Aaron Durbin <adu...@chromium.org>

Reviewed-on: https://chromium-review.googlesource.com/351375
Reviewed-by: Duncan Laurie <dla...@chromium.org>

---
M src/mainboard/intel/amenia/devicetree.cb
1 file changed, 5 insertions(+), 0 deletions(-)

--
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Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I42c23ff7e6956e75de5e1b1339a570b35d999301
Gerrit-PatchSet: 2

Gerrit-Project: chromiumos/third_party/coreboot
Gerrit-Branch: chromeos-2016.05
Gerrit-Owner: Aaron Durbin <adu...@chromium.org>

Gerrit-Reviewer: Aaron Durbin <adu...@chromium.org>
Gerrit-Reviewer: ChromeOS Commit Bot <chromeos-...@chromium.org>

ChromeOS Commit Bot (Gerrit)

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Jun 10, 2016, 3:19:57 AM6/10/16

to Aaron Durbin, Lijian Zhao, Duncan Laurie

ChromeOS Commit Bot has submitted this change and it was merged.

Change subject: UPSTREAM: intel/amenia: Program EMMC dll setting
......................................................................

UPSTREAM: intel/amenia: Program EMMC dll setting

EMMC TX DATA Control needs to be programmed to 0x1A1A to make amenia
system can run stable on EMMC with HS400 mode.

BUG=None
BRANCH=None
TEST=None

Change-Id: I42c23ff7e6956e75de5e1b1339a570b35d999301
Original-Signed-off-by: Zhao, Lijian <lijia...@intel.com>
Original-Tested-by: Petrov, Andrey <andrey...@intel.com>
Original-Reviewed-on: https://review.coreboot.org/15092
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adu...@chromium.org>
Signed-off-by: Aaron Durbin <adu...@chromium.org>

Reviewed-on: https://chromium-review.googlesource.com/351375
Reviewed-by: Duncan Laurie <dla...@chromium.org>

---
M src/mainboard/intel/amenia/devicetree.cb
1 file changed, 5 insertions(+), 0 deletions(-)

Approvals:
Duncan Laurie: Looks good to me, approved

diff --git a/src/mainboard/intel/amenia/devicetree.cb
b/src/mainboard/intel/amenia/devicetree.cb
index af06848..8128c71 100644
--- a/src/mainboard/intel/amenia/devicetree.cb
+++ b/src/mainboard/intel/amenia/devicetree.cb
@@ -10,6 +10,11 @@
# Integrated Sensor Hub
register "integrated_sensor_hub_enable" = "0"

+ # EMMC TX DATA Delay 1#
+ # 0x1A[14:8] stands for 26*125 = 3250 pSec delay for HS400
+ # 0x1A[6:0] stands for 26*125 = 3250 pSec delay for SDR104/HS200
+ register "emmc_tx_data_cntl1" = "0x1A1A" # HS400 required
+
device domain 0 on
device pci 00.0 on end # - Host Bridge
device pci 00.1 on end # - DPTF

--
To view, visit https://chromium-review.googlesource.com/351375
To unsubscribe, visit https://chromium-review.googlesource.com/settings

Gerrit-MessageType: merged
Gerrit-Change-Id: I42c23ff7e6956e75de5e1b1339a570b35d999301
Gerrit-PatchSet: 2

Gerrit-Project: chromiumos/third_party/coreboot
Gerrit-Branch: chromeos-2016.05
Gerrit-Owner: Aaron Durbin <adu...@chromium.org>

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UPSTREAM: intel/amenia: Program EMMC dll setting [chromiumos/third_party/coreboot : chromeos-2016.05]

Aaron Durbin (Gerrit)

Duncan Laurie (Gerrit)

Aaron Durbin (Gerrit)

ChromeOS Commit Bot (Gerrit)

ChromeOS Commit Bot (Gerrit)