rockchip/rk3399: Cleanup write leveling code [chromiumos/third_party/coreboot : chromeos-2016.05]

[Derek Basehore (Gerrit)]

Derek Basehore has uploaded a new change for review. (
https://chromium-review.googlesource.com/395671


Change subject: rockchip/rk3399: Cleanup write leveling code
......................................................................

rockchip/rk3399: Cleanup write leveling code

This cleans up the write leveling code to make it simpler.

BRANCH=none
BUG=none
TEST=boot kevin

Change-Id: I5269226c0da4b8a2b8559399b9970b8ea20f80fc
Signed-off-by: Derek Basehore <dbas...@chromium.org>
---
M src/soc/rockchip/rk3399/sdram.c
1 file changed, 37 insertions(+), 65 deletions(-)



diff --git a/src/soc/rockchip/rk3399/sdram.c
b/src/soc/rockchip/rk3399/sdram.c
index 42b2574..fe54121 100644
--- a/src/soc/rockchip/rk3399/sdram.c
+++ b/src/soc/rockchip/rk3399/sdram.c
@@ -564,21 +564,27 @@
pwrup_srefresh_exit);
}

+static void set_cs_training_index(u32 channel, u32 rank)
+{
+ u32 *denali_phy = rk3399_ddr_publ[channel]->denali_phy;
+
+ /*
+ * PHY_8/136/264/392
+ * phy_per_cs_training_index_X 1bit offset_24
+ */
+ clrsetbits_le32(&denali_phy[8], 0x1 << 24, rank << 24);
+ clrsetbits_le32(&denali_phy[136], 0x1 << 24, rank << 24);
+ clrsetbits_le32(&denali_phy[264], 0x1 << 24, rank << 24);
+ clrsetbits_le32(&denali_phy[392], 0x1 << 24, rank << 24);
+}
+
static void select_per_cs_training_index(u32 channel, u32 rank)
{
u32 *denali_phy = rk3399_ddr_publ[channel]->denali_phy;

/* PHY_84 PHY_PER_CS_TRAINING_EN_0 1bit offset_16 */
- if ((read32(&denali_phy[84])>>16) & 1) {
- /*
- * PHY_8/136/264/392
- * phy_per_cs_training_index_X 1bit offset_24
- */
- clrsetbits_le32(&denali_phy[8], 0x1 << 24, rank << 24);
- clrsetbits_le32(&denali_phy[136], 0x1 << 24, rank << 24);
- clrsetbits_le32(&denali_phy[264], 0x1 << 24, rank << 24);
- clrsetbits_le32(&denali_phy[392], 0x1 << 24, rank << 24);
- }
+ if ((read32(&denali_phy[84])>>16) & 1)
+ set_cs_training_index(channel, rank);
}

/*
@@ -589,68 +595,35 @@
* enable PHY_WRLVL_EARLY_FORCE_ZERO for this slice, and trigger write
* leveling again. Else no additional write leveling is required.
*/
-static void check_write_leveling_value(u32 channel,
- const struct rk3399_sdram_params
- *sdram_params)
+static void modify_write_leveling(u32 channel, u32 rank,
+ const struct rk3399_sdram_params
+ *sdram_params)
{
u32 *denali_ctl = rk3399_ddr_pctl[channel]->denali_ctl;
u32 *denali_phy = rk3399_ddr_publ[channel]->denali_phy;
- u32 i, j;
- u32 wl_value[2][4];
- u32 rank = sdram_params->ch[channel].rank;
+ u32 i;
+ u32 wl_value[4];

- for (i = 0; i < rank; i++) {
- /*
- * PHY_8/136/264/392
- * phy_per_cs_training_index_X 1bit offset_24
- */
- clrsetbits_le32(&denali_phy[8], 0x1 << 24, i << 24);
- clrsetbits_le32(&denali_phy[136], 0x1 << 24, i << 24);
- clrsetbits_le32(&denali_phy[264], 0x1 << 24, i << 24);
- clrsetbits_le32(&denali_phy[392], 0x1 << 24, i << 24);
- wl_value[i][0] = (read32(&denali_phy[63]) >> 16) & 0x3ff;
- wl_value[i][1] = (read32(&denali_phy[191]) >> 16) & 0x3ff;
- wl_value[i][2] = (read32(&denali_phy[319]) >> 16) & 0x3ff;
- wl_value[i][3] = (read32(&denali_phy[447]) >> 16) & 0x3ff;
- }
+ set_cs_training_index(channel, rank);
+ wl_value[0] = (read32(&denali_phy[63]) >> 16) & 0x3ff;
+ wl_value[1] = (read32(&denali_phy[191]) >> 16) & 0x3ff;
+ wl_value[2] = (read32(&denali_phy[319]) >> 16) & 0x3ff;
+ wl_value[3] = (read32(&denali_phy[447]) >> 16) & 0x3ff;

- /*
- * PHY_8/136/264/392
- * phy_per_cs_training_multicast_en_X 1bit offset_16
- */
- clrsetbits_le32(&denali_phy[8], 0x1 << 16, 0 << 16);
- clrsetbits_le32(&denali_phy[136], 0x1 << 16, 0 << 16);
- clrsetbits_le32(&denali_phy[264], 0x1 << 16, 0 << 16);
- clrsetbits_le32(&denali_phy[392], 0x1 << 16, 0 << 16);
-
- for (i = 0; i < rank; i++) {
- clrsetbits_le32(&denali_phy[8], 0x1 << 24, i << 24);
- clrsetbits_le32(&denali_phy[136], 0x1 << 24, i << 24);
- clrsetbits_le32(&denali_phy[264], 0x1 << 24, i << 24);
- clrsetbits_le32(&denali_phy[392], 0x1 << 24, i << 24);
- for (j = 0; j < 4; j++) {
- if (wl_value[i][j] < 0x80)
- clrsetbits_le32(&denali_phy[63+j*128],
- 0x3ff << 16,
- (wl_value[i][j]+0x200) << 16);
- else if ((wl_value[i][j] >= 0x80) &&
- (wl_value[i][j] < 0x100))
- clrsetbits_le32(&denali_phy[78+j*128],
- 0x7 << 8, 0x1 << 8);
- }
+ for (i = 0; i < 4; i++) {
+ if (wl_value[i] < 0x80)
+ clrsetbits_le32(&denali_phy[63+i*128], 0x3ff << 16,
+ (wl_value[i] + 0x200) << 16);
+ else if ((wl_value[i] >= 0x80) && (wl_value[i] < 0x100))
+ clrsetbits_le32(&denali_phy[78+i*128], 0x7 << 8,
+ 0x1 << 8);
}

/* CTL_200 ctrlupd_req 1bit offset_8 */
clrsetbits_le32(&denali_ctl[200], 0x1 << 8, 0x1 << 8);

- /*
- * PHY_8/136/264/392
- * phy_per_cs_training_multicast_en_X 1bit offset_16
- */
- clrsetbits_le32(&denali_phy[8], 0x1 << 16, 1 << 16);
- clrsetbits_le32(&denali_phy[136], 0x1 << 16, 1 << 16);
- clrsetbits_le32(&denali_phy[264], 0x1 << 16, 1 << 16);
- clrsetbits_le32(&denali_phy[392], 0x1 << 16, 1 << 16);
+ set_cs_training_index(channel, 0);
+ select_per_cs_training_index(channel, rank);
}

static int data_training(u32 channel,
@@ -755,9 +728,8 @@
(((tmp >> 13) & 0x1) == 0x1) &&
(((tmp >> 4) & 0x1) == 0x0) &&
(obs_err == 0)) {
- if ((rank == 2) && (i == 1))
- check_write_leveling_value
- (channel, sdram_params);
+ modify_write_leveling(channel, i,
+ sdram_params);
break;
} else if ((((tmp >> 4) & 0x1) == 0x1) ||
(obs_err == 1))

--
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I5269226c0da4b8a2b8559399b9970b8ea20f80fc
Gerrit-PatchSet: 1
Gerrit-Project: chromiumos/third_party/coreboot
Gerrit-Branch: chromeos-2016.05
Gerrit-Owner: Derek Basehore <dbas...@chromium.org>

[Derek Basehore (Gerrit)]

Derek Basehore has posted comments on this change. (
https://chromium-review.googlesource.com/395671 )

Change subject: rockchip/rk3399: Cleanup write leveling code
......................................................................

Patch Set 1: Verified+1

--
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To unsubscribe, visit https://chromium-review.googlesource.com/settings

Gerrit-MessageType: comment

Gerrit-Change-Id: I5269226c0da4b8a2b8559399b9970b8ea20f80fc
Gerrit-PatchSet: 1
Gerrit-Project: chromiumos/third_party/coreboot
Gerrit-Branch: chromeos-2016.05
Gerrit-Owner: Derek Basehore <dbas...@chromium.org>

Gerrit-Reviewer: Derek Basehore <dbas...@chromium.org>
Gerrit-Reviewer: Douglas Anderson <dian...@chromium.org>
Gerrit-Reviewer: Julius Werner <jwe...@chromium.org>
Gerrit-Reviewer: Lin Huang <h...@rock-chips.com>
Gerrit-HasComments: No

[Julius Werner (Gerrit)]

Julius Werner has posted comments on this change. (
https://chromium-review.googlesource.com/395671 )

Change subject: rockchip/rk3399: Cleanup write leveling code
......................................................................

Patch Set 1:

*ping*

Just trying to keep track of everything... is this patch still relevant?
Can it be abandoned?

--
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To unsubscribe, visit https://chromium-review.googlesource.com/settings

Gerrit-MessageType: comment

Gerrit-Change-Id: I5269226c0da4b8a2b8559399b9970b8ea20f80fc
Gerrit-PatchSet: 1
Gerrit-Project: chromiumos/third_party/coreboot
Gerrit-Branch: chromeos-2016.05
Gerrit-Owner: Derek Basehore <dbas...@chromium.org>