stm32: fix AXI memory corruption on STM32H743 [chromiumos/platform/ec : master]
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ChromeOS bot (Gerrit)
Feb 21, 2018, 9:46:59 AM2/21/18
to Vincent Palatin, Aseda Aboagye, ChromeOS Commit Bot, Nicolas Boichat, Nicolas Norvez
ChromeOS bot merged this change by Vincent Palatin.
stm32: fix AXI memory corruption on STM32H743
The STM32H743xI Errata document (rev Y) mentions in the paragraph 2.2.15
'Reading from AXI SRAM might lead to data read corruption':
"""
Read data might be corrupted when the following conditions are met:
- Several read transactions are performed to the AXI SRAM,
- and a master delays its data acceptance while a new transfer is
requested.
"""
We can actually hit this under a fair interrupt load and two tasks
running (e.g polling with the AP with host commands while doing
fingerprint image acquisitions).
So apply the proposed workaround and limit concurrent read access on AXI
master to 1 by setting the READ_ISS_OVERRIDE bit in the AXI_TARG7_FN_MOD
register.
Signed-off-by: Vincent Palatin <vpal...@chromium.org>
BRANCH=none
BUG=b:67081508
TEST=on ZerbleBarn or Meowth, run 'ectool fpmode capture vendor',
poll in a tight loop with 'ectool fpmode'. No longer see random panics.
Change-Id: I6270866b74645d53e4d65f07f65431d5dee11576
Reviewed-on: https://chromium-review.googlesource.com/926009
Commit-Ready: Vincent Palatin <vpal...@chromium.org>
Tested-by: Vincent Palatin <vpal...@chromium.org>
Reviewed-by: Aseda Aboagye <aabo...@chromium.org>
---
M chip/stm32/clock-stm32h7.c
M chip/stm32/registers.h
2 files changed, 18 insertions(+), 0 deletions(-)
diff --git a/chip/stm32/clock-stm32h7.c b/chip/stm32/clock-stm32h7.c
index 9dd1f94..f454571 100644
--- a/chip/stm32/clock-stm32h7.c
+++ b/chip/stm32/clock-stm32h7.c
@@ -191,6 +191,14 @@
void clock_init(void)
{
+ /*
+ * STM32H743 Errata 2.2.15:
+ * 'Reading from AXI SRAM might lead to data read corruption'
+ *
+ * limit concurrent read access on AXI master to 1.
+ */
+ STM32_AXI_TARG_FN_MOD(7) |= READ_ISS_OVERRIDE;
+
#if 0 /* Keep default for now: HSI at 64 Mhz */
clock_set_osc(OSC_PLL);
#endif
diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h
index 24fe5276..c6e8321 100644
--- a/chip/stm32/registers.h
+++ b/chip/stm32/registers.h
@@ -368,6 +368,8 @@
#else /* CHIP_FAMILY_STM32H7 */
+#define STM32_GPV_BASE 0x51000000
+
#define STM32_DBGMCU_BASE 0x5C001000
#define STM32_BDMA_BASE 0x58025400
@@ -2947,6 +2949,14 @@
#define STM32_RNG_SR_DRDY (1<<0)
#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8)
+/* --- AXI interconnect --- */
+
+/* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */
+#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + \
+ 0x1000 * (x))
+#define WRITE_ISS_OVERRIDE (1 << 1)
+#define READ_ISS_OVERRIDE (1 << 0)
+
/* --- MISC --- */
#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE)
#define STM32_UNIQUE_ID_LENGTH (3 * 4)
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