UPSTREAM: src/amd: Add common definition of AMD ACPI MMIO ad... [chromiumos/third_party/coreboot : chromeos-2016.05]
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ChromeOS Commit Bot (Gerrit)
Jan 10, 2017, 2:57:09 AM1/10/17
to Aaron Durbin, Patrick Georgi, Furquan Shaikh
ChromeOS Commit Bot merged this change.
Approvals:
Patrick Georgi: Looks good to me, approved
UPSTREAM: src/amd: Add common definition of AMD ACPI MMIO address The bare ACPI MMIO address 0xFED80000 was used in multiple AMD mainboard files as well as the SB800 native code. Reduce duplication by using a centrally defined value for all AMD ACPI MMIO access. Change-Id: I39a30c0d0733096dbd5892c9e18855aa5bb5a4a7 Original-Signed-off-by: Timothy Pearson <tpea...@raptorengineering.com> Original-Reviewed-on: https://review.coreboot.org/18032 Original-Tested-by: build bot (Jenkins) Original-Tested-by: Raptor Engineering Automated Test Stand <nor...@raptorengineeringinc.com> Original-Reviewed-by: Aaron Durbin <adu...@chromium.org> Original-Reviewed-by: Paul Menzel <paule...@users.sourceforge.net> Signed-off-by: Aaron Durbin <adu...@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/425978 Reviewed-by: Patrick Georgi <pge...@chromium.org> --- M src/mainboard/advansus/a785e-i/mainboard.c M src/mainboard/amd/bettong/boardid.c M src/mainboard/amd/bimini_fam10/mainboard.c M src/mainboard/amd/lamar/romstage.c M src/mainboard/asus/f2a85-m/romstage.c M src/mainboard/asus/m5a88-v/mainboard.c M src/mainboard/avalue/eax-785e/mainboard.c M src/mainboard/biostar/am1ml/romstage.c M src/mainboard/msi/ms7721/romstage.c A src/southbridge/amd/common/amd_defs.h M src/southbridge/amd/sb800/early_setup.c 11 files changed, 48 insertions(+), 19 deletions(-)
diff --git a/src/mainboard/advansus/a785e-i/mainboard.c b/src/mainboard/advansus/a785e-i/mainboard.c
index 14f9ec0..a4917e0 100644
--- a/src/mainboard/advansus/a785e-i/mainboard.c
+++ b/src/mainboard/advansus/a785e-i/mainboard.c
@@ -19,6 +19,7 @@
#include <arch/io.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
+#include <southbridge/amd/common/amd_defs.h>
#include <device/pci_def.h>
u8 is_dev3_present(void);
@@ -34,12 +35,12 @@
/* make sure the Acpi MMIO(fed80000) is accessible */
// XXX Redo this RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0);
- gpio_reg = (volatile u8 *)0xFED80000 + 0xD00; /* IoMux Register */
+ gpio_reg = (volatile u8 *)AMD_SB_ACPI_MMIO_ADDR + 0xD00; /* IoMux Register */
*(gpio_reg + 0x6) = 0x1; /* Int_vga_en */
*(gpio_reg + 170) = 0x1; /* gpio_gate */
- gpio_reg = (volatile u8 *)0xFED80000 + 0x100; /* GPIO Registers */
+ gpio_reg = (volatile u8 *)AMD_SB_ACPI_MMIO_ADDR + 0x100; /* GPIO Registers */
*(gpio_reg + 0x6) = 0x8;
*(gpio_reg + 170) = 0x0;
diff --git a/src/mainboard/amd/bettong/boardid.c b/src/mainboard/amd/bettong/boardid.c
index ae33328..4b2dceb 100644
--- a/src/mainboard/amd/bettong/boardid.c
+++ b/src/mainboard/amd/bettong/boardid.c
@@ -15,6 +15,7 @@
#include <stdint.h>
#include <arch/io.h>
+#include <southbridge/amd/common/amd_defs.h>
#include <boardid.h>
/**
@@ -34,7 +35,7 @@
u8 boardrev = 0;
char boardid;
- gpiommioaddr = (void *)0xfed80000ul + 0x1500;
+ gpiommioaddr = (void *)AMD_SB_ACPI_MMIO_ADDR + 0x1500;
value = read8(gpiommioaddr + (7 << 2) + 2); /* agpio7: board_id2 */
boardrev = value & 1;
value = read8(gpiommioaddr + (6 << 2) + 2); /* agpio6: board_id1 */
diff --git a/src/mainboard/amd/bimini_fam10/mainboard.c b/src/mainboard/amd/bimini_fam10/mainboard.c
index c4dd21e..d10f0db 100644
--- a/src/mainboard/amd/bimini_fam10/mainboard.c
+++ b/src/mainboard/amd/bimini_fam10/mainboard.c
@@ -20,6 +20,7 @@
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
+#include <southbridge/amd/common/amd_defs.h>
#include <southbridge/amd/sb800/sb800.h>
@@ -45,12 +46,12 @@
byte |= 1;
pm_iowrite(0x24, byte);
- gpio_reg = (volatile u8 *)0xFED80000 + 0xD00; /* IoMux Register */
+ gpio_reg = (volatile u8 *)AMD_SB_ACPI_MMIO_ADDR + 0xD00; /* IoMux Register */
*(gpio_reg + 0x6) = 0x1; /* Int_vga_en */
*(gpio_reg + 170) = 0x1; /* gpio_gate */
- gpio_reg = (volatile u8 *)0xFED80000 + 0x100; /* GPIO Registers */
+ gpio_reg = (volatile u8 *)AMD_SB_ACPI_MMIO_ADDR + 0x100; /* GPIO Registers */
*(gpio_reg + 0x6) = 0x8;
*(gpio_reg + 170) = 0x0;
diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c
index 58c6e42..bda8c0f 100644
--- a/src/mainboard/amd/lamar/romstage.c
+++ b/src/mainboard/amd/lamar/romstage.c
@@ -30,6 +30,7 @@
#include <northbridge/amd/pi/agesawrapper_call.h>
#include <cpu/x86/bist.h>
#include <cpu/x86/lapic.h>
+#include <southbridge/amd/common/amd_defs.h>
#include <southbridge/amd/pi/hudson/hudson.h>
#include <cpu/amd/pi/s3_resume.h>
#include "cbmem.h"
@@ -59,8 +60,8 @@
outb(0x24, 0xCD6);
outb(0x01, 0xCD7);
- *(volatile u32 *) (0xFED80000 + 0xE00 + 0x28) |= 1 << 18; /* 24Mhz */
- *(volatile u32 *) (0xFED80000 + 0xE00 + 0x40) &= ~(1 << 2); /* 24Mhz */
+ *(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x28) |= 1 << 18; /* 24Mhz */
+ *(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x40) &= ~(1 << 2); /* 24Mhz */
hudson_lpc_port80();
diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c
index b5aff9f..51cadc7 100644
--- a/src/mainboard/asus/f2a85-m/romstage.c
+++ b/src/mainboard/asus/f2a85-m/romstage.c
@@ -29,6 +29,7 @@
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <device/pnp_def.h>
+#include <southbridge/amd/common/amd_defs.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
#include <southbridge/amd/agesa/hudson/smbus.h>
#include <stdint.h>
@@ -38,8 +39,7 @@
#define MMIO_NON_POSTED_START 0xfed00000
#define MMIO_NON_POSTED_END 0xfedfffff
-#define SB_MMIO 0xFED80000
-#define SB_MMIO_MISC32(x) *(volatile u32 *)(SB_MMIO + 0xE00 + (x))
+#define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 + (x))
#define SERIAL_DEV PNP_DEV(0x2e, IT8728F_SP1)
#define GPIO_DEV PNP_DEV(0x2e, IT8728F_GPIO)
diff --git a/src/mainboard/asus/m5a88-v/mainboard.c b/src/mainboard/asus/m5a88-v/mainboard.c
index 3e20044..256d889 100644
--- a/src/mainboard/asus/m5a88-v/mainboard.c
+++ b/src/mainboard/asus/m5a88-v/mainboard.c
@@ -19,6 +19,7 @@
#include <arch/io.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
+#include <southbridge/amd/common/amd_defs.h>
#include <device/pci_def.h>
u8 is_dev3_present(void);
@@ -34,12 +35,12 @@
/* make sure the MMIO(fed80000) is accessible */
// FIXME: RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0);
- gpio_reg = (volatile u8 *)0xFED80000 + 0xD00; /* IoMux Register */
+ gpio_reg = (volatile u8 *)AMD_SB_ACPI_MMIO_ADDR + 0xD00; /* IoMux Register */
*(gpio_reg + 0x6) = 0x1; /* Int_vga_en */
*(gpio_reg + 170) = 0x1; /* gpio_gate */
- gpio_reg = (volatile u8 *)0xFED80000 + 0x100; /* GPIO Registers */
+ gpio_reg = (volatile u8 *)AMD_SB_ACPI_MMIO_ADDR + 0x100; /* GPIO Registers */
*(gpio_reg + 0x6) = 0x8;
*(gpio_reg + 170) = 0x0;
diff --git a/src/mainboard/avalue/eax-785e/mainboard.c b/src/mainboard/avalue/eax-785e/mainboard.c
index dc1a143..b09a3fa 100644
--- a/src/mainboard/avalue/eax-785e/mainboard.c
+++ b/src/mainboard/avalue/eax-785e/mainboard.c
@@ -19,6 +19,7 @@
#include <arch/io.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
+#include <southbridge/amd/common/amd_defs.h>
#include <device/pci_def.h>
u8 is_dev3_present(void);
@@ -34,12 +35,12 @@
/* make sure the Acpi MMIO(fed80000) is accessible */
// FIXME: RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0);
- gpio_reg = (volatile u8 *)0xFED80000 + 0xD00; /* IoMux Register */
+ gpio_reg = (volatile u8 *)AMD_SB_ACPI_MMIO_ADDR + 0xD00; /* IoMux Register */
*(gpio_reg + 0x6) = 0x1; /* Int_vga_en */
*(gpio_reg + 170) = 0x1; /* gpio_gate */
- gpio_reg = (volatile u8 *)0xFED80000 + 0x100; /* GPIO Registers */
+ gpio_reg = (volatile u8 *)AMD_SB_ACPI_MMIO_ADDR + 0x100; /* GPIO Registers */
*(gpio_reg + 0x6) = 0x8;
*(gpio_reg + 170) = 0x0;
diff --git a/src/mainboard/biostar/am1ml/romstage.c b/src/mainboard/biostar/am1ml/romstage.c
index e0afa75..1672349 100644
--- a/src/mainboard/biostar/am1ml/romstage.c
+++ b/src/mainboard/biostar/am1ml/romstage.c
@@ -30,6 +30,7 @@
#include <northbridge/amd/agesa/agesawrapper.h>
#include <cpu/x86/bist.h>
#include <cpu/x86/lapic.h>
+#include <southbridge/amd/common/amd_defs.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
#include <cpu/amd/agesa/s3_resume.h>
#include "cbmem.h"
@@ -44,8 +45,7 @@
#define MMIO_NON_POSTED_START 0xfed00000
#define MMIO_NON_POSTED_END 0xfedfffff
-#define SB_MMIO 0xFED80000
-#define SB_MMIO_MISC32(x) *(volatile u32 *)(SB_MMIO + 0xE00 + (x))
+#define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 + (x))
static void it_sio_write(pnp_devfn_t dev, u8 reg, u8 value)
diff --git a/src/mainboard/msi/ms7721/romstage.c b/src/mainboard/msi/ms7721/romstage.c
index 4aeb1ec..9ce47f2 100644
--- a/src/mainboard/msi/ms7721/romstage.c
+++ b/src/mainboard/msi/ms7721/romstage.c
@@ -30,6 +30,7 @@
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <device/pnp_def.h>
+#include <southbridge/amd/common/amd_defs.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
#include <southbridge/amd/agesa/hudson/smbus.h>
@@ -41,8 +42,7 @@
#define MMIO_NON_POSTED_START 0xfed00000
#define MMIO_NON_POSTED_END 0xfedfffff
-#define SB_MMIO 0xFED80000
-#define SB_MMIO_MISC32(x) *(volatile u32 *)(SB_MMIO + 0xE00 + (x))
+#define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 + (x))
/* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */
#define SUPERIO_ADDRESS 0x4e
diff --git a/src/southbridge/amd/common/amd_defs.h b/src/southbridge/amd/common/amd_defs.h
new file mode 100644
index 0000000..55db30f
--- /dev/null
+++ b/src/southbridge/amd/common/amd_defs.h
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Raptor Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+
+#ifndef _AMD_SB_DEFS_H_
+#define _AMD_SB_DEFS_H_
+
+#define AMD_SB_ACPI_MMIO_ADDR 0xfed80000ul
+
+#endif
diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c
index 54e6ada..7ac6ec8 100644
--- a/src/southbridge/amd/sb800/early_setup.c
+++ b/src/southbridge/amd/sb800/early_setup.c
@@ -19,6 +19,7 @@
#include <reset.h>
#include <arch/acpi.h>
#include <arch/cpu.h>
+#include <southbridge/amd/common/amd_defs.h>
#include <cbmem.h>
#include "sb800.h"
#include "smbus.c"
@@ -107,8 +108,8 @@
reg8 &= ~(1 << 1);
pmio_write(0x24, reg8);
- *(volatile u32 *)(0xFED80000+0xE00+0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */
- *(volatile u32 *)(0xFED80000+0xE00+0x40) |= 1 << 1; /* 48Mhz */
+ *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR+0xE00+0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */
+ *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR+0xE00+0x40) |= 1 << 1; /* 48Mhz */
}
/***************************************
* Legacy devices are mapped to LPC space.
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