upgrade S/W -> timing worse
William LenihanIii
My Virtex-E (xcv600E) design was meeting timing with Alliance (or
Foundation, presumably same P&R engine) version 3.1i, then when I
upgraded to version 4.2i, the design's timing got significantly
worse even though it's operating on the same EDIF netlist & same
UCF file & same "effort" level (max) set in the
Design Manager's " Design --> Options... " menu.
Why? [ I thought it was supposed to get better! ]
PS -- It's not just me .... 4 other designers in my organization are having
same problem.
ham...@cloud.net.au
> My Virtex-E (xcv600E) design was meeting timing with Alliance (or
> Foundation, presumably same P&R engine) version 3.1i, then when I
> upgraded to version 4.2i, the design's timing got significantly
> worse even though it's operating on the same EDIF netlist & same
> UCF file & same "effort" level (max) set in the
> Design Manager's " Design --> Options... " menu.
>
> Why? [ I thought it was supposed to get better! ]
Two possibilities.
1. The route did get worse. Possible.
2. The speed files got more accurate, which for Virtex-E means worse,
especially if you use much block RAM.
Were you using all the latest service packs and speed file updates for
your 3.x tools? If so you shouldn't notice much different in the speed
files going to 4.2, from memory.
Hamish
--
Hamish Moffatt VK3SB <ham...@debian.org> <ham...@cloud.net.au>
Rick Filipkiewicz
ham...@cloud.net.au wrote:
> William LenihanIii <lenih...@earthlink.net> wrote:
> > My Virtex-E (xcv600E) design was meeting timing with Alliance (or
> > Foundation, presumably same P&R engine) version 3.1i, then when I
> > upgraded to version 4.2i, the design's timing got significantly
> > worse even though it's operating on the same EDIF netlist & same
> > UCF file & same "effort" level (max) set in the
> > Design Manager's " Design --> Options... " menu.
> >
> > Why? [ I thought it was supposed to get better! ]
>
> Two possibilities.
>
> 1. The route did get worse. Possible.
>
Esp. in view of Ray Andraka's comments that in the change from 4.1i ->
4.2i the routing has got worse for a given placement. I think this is true
of 3.xi->4.1i as well.
>
> 2. The speed files got more accurate, which for Virtex-E means worse,
> especially if you use much block RAM.
>
> Were you using all the latest service packs and speed file updates for
> your 3.x tools? If so you shouldn't notice much different in the speed
> files going to 4.2, from memory.
>
To check this - speed file degradation - the OP should probably ask Xilinx
for the latest 4.x speed files but in a form compatible with the 3.x P&R
tools. Its been claimed on this NG that this is possible if you badger
your FAE hard enough.
I would say as a side note that Xilinx should really put the speed files
into a format that's independent of the tool set version [simple ASCII
text file ?].
Ray Andraka
several areas with the 4.x. Xilinx is not officially distributing the revised
speed files for 3.3, but like Rick said, if you badger the FAE's enough you
can shake loose the files. Personally, I think it is a sin not putting those
speedfiles for 3.3 up on the web. This of course wouldn't be an issue if 4.2
did as good a routing job as 3.3. Somewhere in the transition the router got
lazy, and even putting the new -xe=2 extra effort switch to its max setting
doesn't bring the PAR back on par with the 3.3 (revised with the latest speed
files). 4.1/2 also broke the floorplanner pretty badly.
BTW, this isn't just the virtex/virtexE with the lazy router either. I got
significantly better results on virtexII by routing a placed design under 3.3
then doing the timing analysis under 4.2 to have the same speed files compared
with doing the same design, same floorplan under 4.2. Unfortunately, that
doesn't work if there are pipelined multipliers in the design.
Rick Filipkiewicz wrote:
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email r...@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
ham...@cloud.net.au
> Esp. in view of Ray Andraka's comments that in the change from 4.1i ->
> 4.2i the routing has got worse for a given placement. I think this is true
> of 3.xi->4.1i as well.
Hmmm... we found that 4.1 was bad for some Virtex-E designs but
4.2 was quite reasonable.
Ray Andraka
does the placement better than 3.3 did. For a highly floorplanned design, the
router in 3.3 does a significantly better job when timing is tight than 4.2
does, although it also takes a little bit longer.
ham...@cloud.net.au wrote:
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