Audio generator using EPROM and DAC
DGLasley
And what _exactly_ is wrong with an op-amp? As suggested earlier, use the uC
as the frequency generator, and use any one of a million analog options to
create a clean, stable, low impedance, _useful_ signal. My first choice would
be a PLL/VCO setup, since it loves to have a digital reference, and most will
go from DC to TV.
-Dan
-Dan
Rickman
I looked at using a PLL in conjunction with a phase accumulator once.
The phase accum could generate a signal with an 'average' frequency
resolution of low Hz. But it always had a clock edge jitter of one clock
cycle. For frequencies near the master clock frequency, this would be a
noticable percentage of a clock period.
I looked at using a PLL to clean up this jitter. The goal was to
generate a clock with a rate that could vary over a wide range like 50
MHz to 0.5 MHz. I thought I could get the PLL to work well over a range
of 50 MHz to 25 MHz and then divide by powers of 2 to get to the lower
rates.
Not having any experience with PLLs, I didn't know how to best use it to
get rid of the jitter. If I worked in the range of 50 to 25 MHz for the
reference, I started with a maximum jitter percentage. If I worked at a
lower rate of say, 1 to 0.5 MHz, the jitter would be a lower percentage,
but now I had to divide the PLL rate and this has an effect on the lock
in of the PLL.
The bottom line was that designing a PLL is not trivial and I didn't
know how to do it. I would like to use this type of design in the
future. Can anyone explain how to best optimize the PLL part?
The big advantage of this approach is that everything except the VCO and
the low pass filter can be done in a part of an FPGA that I often have
on my boards. So I can keep the real estate down.
--
Rick Collins
rick.c...@XYarius.com
remove the XY to email me.
Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design
Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX
Internet URL http://www.arius.com
Allan Herriman
wrote:
[snip]
>I looked at using a PLL in conjunction with a phase accumulator once.
>The phase accum could generate a signal with an 'average' frequency
>resolution of low Hz. But it always had a clock edge jitter of one clock
>cycle. For frequencies near the master clock frequency, this would be a
>noticable percentage of a clock period.
>
>I looked at using a PLL to clean up this jitter. The goal was to
>generate a clock with a rate that could vary over a wide range like 50
>MHz to 0.5 MHz. I thought I could get the PLL to work well over a range
>of 50 MHz to 25 MHz and then divide by powers of 2 to get to the lower
>rates.
>
>Not having any experience with PLLs, I didn't know how to best use it to
>get rid of the jitter. If I worked in the range of 50 to 25 MHz for the
>reference, I started with a maximum jitter percentage. If I worked at a
>lower rate of say, 1 to 0.5 MHz, the jitter would be a lower percentage,
>but now I had to divide the PLL rate and this has an effect on the lock
>in of the PLL.
>
>The bottom line was that designing a PLL is not trivial and I didn't
>know how to do it. I would like to use this type of design in the
>future. Can anyone explain how to best optimize the PLL part?
>
>The big advantage of this approach is that everything except the VCO and
>the low pass filter can be done in a part of an FPGA that I often have
>on my boards. So I can keep the real estate down.
Hi Rick,
Me again.
A superficial theoretical treatment of jitter transfer in PLLs
(including both reference and VCO phase noise suppression) can be
found in the following post:
http://ww2.altavista.com/cgi-bin/news?msg@47566@comp%2earch%2eembedded%26jitter
Deja.com don't seem to have it any more, but if they did the URL would
be:
http://www.deja.com/[ST_rn=ps]/getdoc.xp?AN=472697235&fmt=text
Not that this only covers the case of a second order type 2 loop (i.e.
a PLL with a PI controller). Practical PLLs usually have higher order
loops (at least to account for strays, VCO modulation bandwidth, and
delays in the digital part.).
Also, that analysis doesn't take reference spur suppression into
account, which is another reason for having extra poles in loop
filter.
(If you get really keen and take sampling effects in the divider and
phase comparator into account the jitter transfer functions are no
longer rational polynomials. In that case Bode plots are about the
most useful tool. In the past (on occasions) I have approximated the
sampling effects with a single low pass pole, which allows the use of
rational polynomials (a good thing, IMO).)
Phaselock Techniques, by Floyd M. Gardiner is the most often quoted
reference for PLLs. I found it a little light on some practical
details though.
Something to be careful about: sometimes there will be jitter
components at the output of the phase accumulator that sit close to
0Hz away from the carrier. No amount of filtering with PLLs can
remove them.
The only thing you can do is avoid them altogether by carefully
choosing clock frequencies, etc. I have found spreadsheets useful for
this (email for details).
<old timer recollection mode>
I worked on a frequency synthesiser design once for a frequency
hopping radar. It had a DDS (for fast hopping) clocking at about 1GHz
(for spectral purity). The output of the DDS was at about 50MHz or
so. This went to a PLL to be cleaned up.
To get the PLL to switch quickly enough for the application (a few us,
IIRC), the loop voltage was forced briefly with a DAC to the
approximate voltage and then released.
So yeah, your idea of phase accumulator and PLL is a goer.
</old timer recollection mode>
About your 0.5 to 50MHz problem, did you think of having the VCO run
at a much higher frequency, say 100MHz, and having the PLL multiply by
a fixed number, say 4?
The output divider would need to be a fully programmable divider
instead of just dividing by powers of 2.
This has three effects.
1. The output frequency of the NCO is lower (25MHz max for this
example), which reduces the jitter.
2. The VCO requires a smaller fractional tuning range (which is good
for things like phase noise and may make the design simpler).
For the numbers above, the tuning range would be 66MHz to 100MHz.
(66MHz is determined by the /2 to /3 changeover in the output
divider).
3. The phase accumulator oscillator requires a smaller fractional
tuning range, which may help to avoid some nasty spurii.
For the numbers above, the output of the NCO would be 16.6 to 25MHz.
Cheap canned VCOs are available in the upper UHF (thanks to mobile
phones), so you can take this approach quite far (up to about 3-400MHz
or so with a xilinx FPGA, but there's nothing stopping you from using
an external dual modulus prescaler).
Regards,
Allan.
Rickman
> Hi Rick,
>
> Me again.
>
> A superficial theoretical treatment of jitter transfer in PLLs
> (including both reference and VCO phase noise suppression) can be
> found in the following post:
>
> http://ww2.altavista.com/cgi-bin/news?msg@47566@comp%2earch%2eembedded%26jitter
I took a look. It sounds reasonable. Now all I have to do is to
characterize the noise of the phase accumulator.
...snip...
> Something to be careful about: sometimes there will be jitter
> components at the output of the phase accumulator that sit close to
> 0Hz away from the carrier. No amount of filtering with PLLs can
> remove them.
> The only thing you can do is avoid them altogether by carefully
> choosing clock frequencies, etc. I have found spreadsheets useful for
> this (email for details).
This would be designed to be a general purpose freq gen without knowing
any of the actual freqs that will be required.
> <old timer recollection mode>
>
> I worked on a frequency synthesiser design once for a frequency
> hopping radar. It had a DDS (for fast hopping) clocking at about 1GHz
> (for spectral purity). The output of the DDS was at about 50MHz or
> so. This went to a PLL to be cleaned up.
> To get the PLL to switch quickly enough for the application (a few us,
> IIRC), the loop voltage was forced briefly with a DAC to the
> approximate voltage and then released.
>
> So yeah, your idea of phase accumulator and PLL is a goer.
>
> </old timer recollection mode>
I am surprized that they needed a PLL for this. The reason they didn't
use the phase accumulator and PLL on my last project was because they
went with a full DDS with an DAC, analog low pass filter, and
comparator. For your radar job they could have dropped the comparator
and they should have been able to get a pretty clean signal with the
numbers you indicate.
> About your 0.5 to 50MHz problem, did you think of having the VCO run
> at a much higher frequency, say 100MHz, and having the PLL multiply by
> a fixed number, say 4?
> The output divider would need to be a fully programmable divider
> instead of just dividing by powers of 2.
> This has three effects.
> 1. The output frequency of the NCO is lower (25MHz max for this
> example), which reduces the jitter.
> 2. The VCO requires a smaller fractional tuning range (which is good
> for things like phase noise and may make the design simpler).
> For the numbers above, the tuning range would be 66MHz to 100MHz.
> (66MHz is determined by the /2 to /3 changeover in the output
> divider).
> 3. The phase accumulator oscillator requires a smaller fractional
> tuning range, which may help to avoid some nasty spurii.
> For the numbers above, the output of the NCO would be 16.6 to 25MHz.
>
> Cheap canned VCOs are available in the upper UHF (thanks to mobile
> phones), so you can take this approach quite far (up to about 3-400MHz
> or so with a xilinx FPGA, but there's nothing stopping you from using
> an external dual modulus prescaler).
I am not clear about the architechture you are suggesting. If you have a
fully programmable divider why do you need the PLL? One of the reasons I
chose the phase accumulator is because the programming is straight
forward. You pick a real divisor of the maximum clock rate. The integer
part controls the power of 2 divider and the fractional part is used to
control the phase accumulator. Very straight forward programming. No
uncertainty as to the freq you have selected.
The other reason I want to use this topology is because I want to
minimize the external (to the FPGA) components. I am already putting 10
pounds of circuitry on a 5 pound board. ;)
Allan Herriman
On Mon, 26 Jul 1999 08:59:03 -0400, Rickman <spamgo...@yahoo.com>
wrote:
>Allan Herriman wrote:
>> A superficial theoretical treatment of jitter transfer in PLLs
>> (including both reference and VCO phase noise suppression) can be
>> found in the following post:
>>
>> http://ww2.altavista.com/cgi-bin/news?msg@47566@comp%2earch%2eembedded%26jitter
>
>I took a look. It sounds reasonable. Now all I have to do is to
>characterize the noise of the phase accumulator.
This is the fun part. I tried to do this once using a straighforward
approach by estimating the waveform as a function of time and then
taking an FFT. Try it, you'll find out how difficult it is.
A better way is to notice that the phase accumulator msb output is
just a square wave sampled (& ZOH applied) by the phase accumulator
clock.
One can perform the Fourier decomposition of the square wave (into
harmonically related sinusoids) then apply sampling and sin(x)/x
correction (for the ZOH) to each harmonic in turn.
I have an Excel spreadsheet that will plot the spectrum for the first
3000 harmonics. Just enter the clock frequency and the output
frequency, and it does the rest. It also estimates the jitter at the
output of an analog PLL on the output of the NCO. You get to specify
the PLL bandwidth and order.
I have just emailed it to you (and will email it to all other
interested parties, but they have to send me email first so I know
where to send it).
Playing with the spreadsheet quickly reveals that there are certain
division ratios that are *really bad* for jitter (the ones close to
integers (or ratios of small integers) are the worst), and others that
are ok. The trick is to get the frequencies you want without having
to tune across any of the bad ones.
>...snip...
>> Something to be careful about: sometimes there will be jitter
>> components at the output of the phase accumulator that sit close to
>> 0Hz away from the carrier. No amount of filtering with PLLs can
>> remove them.
>> The only thing you can do is avoid them altogether by carefully
>> choosing clock frequencies, etc. I have found spreadsheets useful for
>> this (email for details).
>
>This would be designed to be a general purpose freq gen without knowing
>any of the actual freqs that will be required.
It should still be possible to reduce the tuning range enough to avoid
the nasty frequencies. By using a multiplier after the NCO, you can
reduce the fractional tuning range of the NCO while still keeping the
linear tuning range at the output high enough.
Did that make sense?
Say you want your output to vary by 10MHz, and the NCO clock is 50MHz.
You could have the NCO tune over (say) 5MHz to 15MHz, but this is a
20% range, and it will definitely have jitter problems at some
frequencies.
You could have the NCO tune over 0.5MHz to 1.5MHz, and multiply the
output frequency by 10. So the output still varies by 10MHz, but the
NCO only tunes over a 2% range, which might enable you to have much
lower sampling induced jitter.
>> <old timer recollection mode>
>>
>> I worked on a frequency synthesiser design once for a frequency
>> hopping radar. It had a DDS (for fast hopping) clocking at about 1GHz
>> (for spectral purity). The output of the DDS was at about 50MHz or
>> so. This went to a PLL to be cleaned up.
>> To get the PLL to switch quickly enough for the application (a few us,
>> IIRC), the loop voltage was forced briefly with a DAC to the
>> approximate voltage and then released.
>>
>> So yeah, your idea of phase accumulator and PLL is a goer.
>>
>> </old timer recollection mode>
>
>I am surprized that they needed a PLL for this. The reason they didn't
>use the phase accumulator and PLL on my last project was because they
>went with a full DDS with an DAC, analog low pass filter, and
>comparator. For your radar job they could have dropped the comparator
>and they should have been able to get a pretty clean signal with the
>numbers you indicate.
"Pretty clean" varies with the customer's needs (*). In this case we
needed a PLL. But it was also used as a frequency multiplier (the
output was at several GHz), which is much easier than trying to
upconvert the output of a DDS (which is very difficult to do cleanly
due to all the spurious signals at the output of the DDS).
(*) Military users tend to be paranoid about spurious outputs on
frequency synthesisers (ECM, ECCM and all that).
>> About your 0.5 to 50MHz problem, did you think of having the VCO run
>> at a much higher frequency, say 100MHz, and having the PLL multiply by
>> a fixed number, say 4?
>> The output divider would need to be a fully programmable divider
>> instead of just dividing by powers of 2.
>> This has three effects.
>> 1. The output frequency of the NCO is lower (25MHz max for this
>> example), which reduces the jitter.
>> 2. The VCO requires a smaller fractional tuning range (which is good
>> for things like phase noise and may make the design simpler).
>> For the numbers above, the tuning range would be 66MHz to 100MHz.
>> (66MHz is determined by the /2 to /3 changeover in the output
>> divider).
>> 3. The phase accumulator oscillator requires a smaller fractional
>> tuning range, which may help to avoid some nasty spurii.
>> For the numbers above, the output of the NCO would be 16.6 to 25MHz.
>>
>> Cheap canned VCOs are available in the upper UHF (thanks to mobile
>> phones), so you can take this approach quite far (up to about 3-400MHz
>> or so with a xilinx FPGA, but there's nothing stopping you from using
>> an external dual modulus prescaler).
>
>I am not clear about the architechture you are suggesting. If you have a
>fully programmable divider why do you need the PLL? One of the reasons I
>chose the phase accumulator is because the programming is straight
>forward. You pick a real divisor of the maximum clock rate. The integer
>part controls the power of 2 divider and the fractional part is used to
>control the phase accumulator. Very straight forward programming. No
>uncertainty as to the freq you have selected.
<ascii art>
Your original approach:
+-----+ +-----+ +-----+ +-----+ +-----+
| | | | |Loop | | | Fv | | Fout
---->| NCO |---->| PD |---->|Filt |---->| VCO |--+->| /M |---->
Fref | | Fn | | | | | | | | |
+-----+ +-----+ +-----+ +-----+ | +-----+
^ |
| |
+-----------------------------+
(M is power of 2)
My Suggestion:
+-----+ +-----+ +-----+ +-----+ +-----+
| | | | |Loop | | | Fv | | Fout
---->| NCO |---->| PD |---->|Filt |---->| VCO |--+->| /M |---->
Fref | | Fn | | | | | | | | |
+-----+ +-----+ +-----+ +-----+ | +-----+
^ |
| +-----+ |
+--------| |<-------------+
Fv/N | /N |
| |
+-----+
(M is +ve integer, N is fixed +ve integer)
</ascii art>
At the upper end of Fout M will be small, so you still need the NCO
and PLL to get fine control over frequency.
The main advantages of "my suggestion" are that
(1) Fn has a smaller fractional tuning range, which can improve output
jitter (by avoiding the "bad" division ratios),
(2) Fn can be at a lower frequency, which can improve output jitter,
(3) Fv has a smaller fractional tuning range, which can improve output
jitter (smaller Hz/V, etc.),
(4) Fv has a smaller fractional tuning range, which may make it
cheaper.
(5) Fn has a smaller fractional tuning range, which avoids the problem
of PLL performance changing with Fn.
(6) Fn can be at a lower frequency, which means that Fref doesn't need
to be as high (power savings, easier FPGA design, etc.).
As you point out, programming is more complicated, but is this a
problem if you have a micro in the system? (I assume you do. This is
c.a.e after all...)
One disadvantage is that it is harder to do frequency sweeps. There
will be frequency jumps when M is changed. This also happened in your
original architecture, so I assume it's not an issue for you.
>The other reason I want to use this topology is because I want to
>minimize the external (to the FPGA) components. I am already putting 10
>pounds of circuitry on a 5 pound board. ;)
In the above block diagram, both the /M and /N dividers could be put
in the FPGA, so there is no increase in board space (but there is an
increase in FPGA power dissipation and utilisation (bummer if it takes
you up to the next size part)).
Regards,
Allan.
(I'm having fun here!)