Pentium info
Eric James Ewanco
Thanks for posting that press release on Pentium. Has Intel set up an ftp
server where people can download that performance brief? How about an email
server? Here at Digital, we put all the Alpha performance briefs on
Gatekeeper for download ;-)
I'd still be interested in architectural information on Pentium, e.g., does
it do register renaming and how many registers are available to be mapped to
the architected registers? How does the branch prediction work? Does the P5
use speculative execution? Which instructions can be dual-issued, and what
happens when a "complex" instruction (one which cannot be "superscalarly
issued") is executing and a "simple" instruction is ready for issue? (i.e.
complex/complex is obviously not possible, and simple/simple is possible, but
can a complex/simple instruction pair be dual-issued, or a simple/complex
pair?) Are prefetched instructions partially decoded or fully decoded? What
new instructions and modes does Pentium implement?
Also, what additional processor speeds or Pentium varieties has Intel
publically hinted at?
Next question: I heard that the P6 was going to break with Intel
compatibility. Has this been verified? Will it be similar to the internal RISC
architecture and instruction set the Pentium is running on top of?
Eric
--
/===========================================================================\
| Eric Ewanco - Software Engineer For the rash and outrageous opinions ex-|
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\==========================- 2 Th 2:15 -====================================/
Dennis O'Connor
e...@irenaeus.mlo.dec.com (Eric James Ewanco) writes:
] Next question: I heard that the P6 was going to break with Intel
] compatibility. Has this been verified?
I severely doubt it ever will be. Who makes up these rumours ?
--
Dennis O'Connor doco...@sedona.intel.com
Thomas D. Barrett
>How does the branch prediction work?
Just obvious speculation that there is sufficient look-ahead to start
the evaluation before it happens. The Prefetch could also be alterred
based on various parameters which could on average potentially provide
a performance gain.
> Does the P5 use speculative execution?
More speculation... if the microcode detects that two instructions
cannot be executed in parallel, the other pipe is basically free to do
something else. The obvious thing would be to provide a look-ahead to
see if anything else that is quick could be executed ahead of the
stalled instruction. Of course this is generally the job of the
compiler, but there is no reason besides microcode complexity that it
cannot be done onchip and thus run without much optimization.
>Which instructions can be dual-issued
Again, the obvious thing is if the instructions are mutually
exclusive. This is extremely easy to detect by looking at the next
instruction, but more complex microcode could be designed to do a
real-time optimization. I doubt that they went to the trouble since
they are process limited, but this is something that will show up in
everyone's next generation processor.
>Are prefetched instructions partially decoded or fully decoded?
Another person has asked about whether or not partially or fully
decoded values are stored in the cache. This will certainly be
answered when the chip is closely examined for cache area. Storing
partially decoded or fully decoded instructions in a cache is nothing
new... it is something quite obvious to be for the instruction cache.
> What new instructions and modes does Pentium implement?
Who knows what is lurking behind the Appendix H. I suspect however
that besides the CPUID which has been hinted at (and/or confirmed...
I haven't been paying attention to the rumored new instructions much),
there is nothing really earth shattering... CPUID has been begged for
by BIOS, OS, and apps programmers for a very long time.
>Also, what additional processor speeds or Pentium varieties has Intel
>publically hinted at?
This is very process dependent... 66MHz is really the upper
manufactureable limit in todays process technology. IBM has a 100MHz
process which they claim to be profitable (and I believe them). The
industry is bringing 100MHz processes online very soon. And, Sematech
(the US consortium which AMD is involved in) has released a 0.35
micron processes which we will be eventually using in our new Fab-25
(in celebration of our, then, 25 years in the biz).
>Next question: I heard that the P6 was going to break with Intel
>compatibility.
This would be a VERY stupid move in the short term. A lots of
OS software still relies on the v86 and v286 mode of operation. While
this is great for Windows NT and the other NT-like operating systems,
it would be bad news for many UNIX and OS/2 users. Maybe in 5 years
or so when the performance level of emulating virtual modes match that
of the native performance of the 486DX/33... but not in the next
generation. Maybe you have been hearing rumors about the port of NT
to their next generation RISC? This move is to combat MIPS and Alpha
on their own ground, so to speak. There is nothing technical in
preventing this and it is a smart marketing move to try and make intel
leaders in the NT marketplace.
Tom
--
|Tom Barrett (TDBear), Sr. Engineer|tom.b...@amd.com|v:512-462-6856 |
|AMD PCD MS-520 | 5900 E. Ben White|Austin, TX 78741 |f:512-462-5155 |
|"No is yes, And we're all free" ---Tracy Chapman, "Why?" |
|My views are my own and may not be the same as the company of origin |
Guy Harris
>compatibility. Has this been verified? Will it be similar to the internal RISC
>architecture and instruction set the Pentium is running on top of?
Err, what "instruction set" is that? Is it an "instruction set" in any
"conventional" sense of the word, or is it just Stuff That Gets Stuck In
The Pipeline?
Eric James Ewanco
My understanding is that Pentium is basically a RISC processor executing
CISC instructions; i.e., something like microcode, but on a more complex level.
The RISC implementation is hidden and inaccessible to the programmer. What I
meant was, is the P6 merely going to make this RISC implementation visible to
the programmer?
Guy Harris
>CISC instructions; i.e., something like microcode, but on a more complex level.
>The RISC implementation is hidden and inaccessible to the programmer. What I
>meant was, is the P6 merely going to make this RISC implementation visible to
>the programmer?
According to the latest issue of *Microprocessor Report*, there are
"microwords" that control stuff inside the chip. "Simple" instructions
generate a single, internal microword that "triggers a simple hardware
state machine in the EX stage" of the pipeline; the article seems to
indicate that they do state control for memory/register operations.
More complicated instructions decode into a microword and, presumably,
the address in the internal microcode ROM of subsequent microwords.
Those microwords control both integer pipelines (as opposed to those
used by "simple" instructions which, at least in some cases, run only
one pipeline, presumably so that two simple instructions can, in some
cases, run through the pipeline in parallel).
The microwords in the ROM are 92 bits long; dunno how long the internal
microwords are. 92 bits seems like a somewhat, umm, *unusual* length
for a RISC instruction set and, given that it runs two pipelines, it may
be a bit VLIW-ish.
I suspect that if that stuff gets exposed, it'll not look much like a
conventional RISC architecture. I also suspect that it *won't* get
exposed, and that P6's equivalent of those microwords, if any, won't
necessarily look like those in P5.
It's an interesting article. In addition to a lot of the details of the
chip's microarchitecture, they also mention what stuff is described in
the infamous Appendix H - or, at least, the document to which Appendix H
of the over-1000-page "Pentium Processor User's Manual: Volume 3"
refers. The article indicates that the appendix "contains only a
three-sentence explanation that the information is considered Intel
confidential and proprietary and is provided in the *Supplement to the
Pentium Processor User's Manual* only under appropriate non-disclosure."
(Sounds like the infamous Figure 1 to me. "See Figure 1." :-))
The article mentions the undocumented stuff, but doesn't describe it;
*Microprocessor Report* didn't get a copy - they say it's "supplied only
to selected operating-system vendors."
The issue is the March 29, 1993 issue, Volume 7, Number 4.
*Microprocessor Report* is published by MicroDesign Resources. Their
customer-service e-mail address is "c...@mdr.ziff.com" (they were bought
by Ziff-Davis a while ago); you can probably speak to them about
ordering that issue, ordering back issues, or ordering subscriptions.
(It's not cheap, though.)
Guy Harris
>it do register renaming
The article in *Microprocessor Report*, Volume 7, Number 4, doesn't seem
to indicate that it does.
>How does the branch prediction work?
See the aforementioned article; it has a several-paragraph section on
that.
>Does the P5 use speculative execution?
The article doesn't seem to indicate that it does.
>Which instructions can be dual-issued,
There's a sidebar in the article that gives the rules for multiple
issue.
>and what
>happens when a "complex" instruction (one which cannot be "superscalarly
>issued") is executing and a "simple" instruction is ready for issue?
The instructions that require microcode can't be issued in parallel with
any other instructions, because the microwords run both of the
pipelines.
>Are prefetched instructions partially decoded or fully decoded?
Apparently, Intel isn't telling....
>What new instructions and modes does Pentium implement?
User-mode:
CMPSXCHG8B, which is an 8-byte "compare-and-exchange"
instruction, similar to the 486's 4-byte version;
CPUID, which reads the vendor, family, model, and stepping of
the chip:
load 0 into EAX and do a CPUID, and P5 stuffs
"Genu"
into EBX,
"ineI"
into EDX, and
"ntel"
into ECX. Gag me with a spoon....
load 1 into EAX and do a CPUID, and EAX and EDX get the
stepping, model, family, and "feature flags"; the latter
indicate whether there's an on-chip FPU, whether the
machine check exception is implemented, whether
CMPXCHG8B is implemented, and stuff for which you have
to See Appendix H.
RDTSC - "See Appendix H"
Supervisor-mode:
MOV instructions to read and write control register 4; for a
description of most of the bits in that register, See Appendix
H.
RDMSR and WRMSR to read and write model-specific registers; P5
seems to have some diagnostic registers, and to see what they
do, See Appendix H.
RSM, which returns from system management mode; P5 has the SMM
stuff in it.
Eric James Ewanco
In article <17...@auspex-gw.auspex.com>, g...@Auspex.COM (Guy Harris) writes:
>>What new instructions and modes does Pentium implement?
> User-mode:
> CMPSXCHG8B, which is an 8-byte "compare-and-exchange"
> instruction, similar to the 486's 4-byte version;
Especially for Norton's Desktop For Windows With Support For Windows for
Workgroups (NDFWWSFWFW)!
--
/===========================================================================\
| Eric Ewanco - Software Engineer For the rash and outrageous opinions ex-|
| Digital Equipment, Maynard MA pressed herein I alone am responsible; |
| ewa...@mlo.dec.com they do not belong to DIGITAL(TM). |
Mika Iisakkila
> load 0 into EAX and do a CPUID, and P5 stuffs
> "Genu"
> into EBX,
> "ineI"
> into EDX, and
> "ntel"
> into ECX. Gag me with a spoon....
So for other values of EAX, do you get the names of the people who
designed the chip :-) :-)
This kind of "copy protection" schemes remind me of those old PC clone
graphics cards that had the string "this is not an IBM EGA display
adapter" in the onboard BIOS...
--
Segmented Memory Helps Structure Software
johnson scott andrew
One wonders. Would Intel be within their rights to write software which would
crash if this particular sequence was not present, or to encourage software
developers to do the same (to discourage Pentium-clones)????
Also, would a clone developer (like Cyrix or AMD) be able to legally duplicate
this function on any Pentium clones?
As I am not an expert on anti-trust law or trademark law, I was wondering if
the net had any ideas on this.
/sj/
John F Carr
joh...@prism.CS.ORST.EDU (johnson scott andrew) writes:
[about CPUID writing "GenuineIntel" into %eax:%ebx:%ecx]
>Also, would a clone developer (like Cyrix or AMD) be able to legally duplicate
>this function on any Pentium clones?
Someone here came up with a good solution to this: implement a SETCPUID
function in the clones. If someone runs a program to set the CPU ID to
"GenuineIntel", you can't blame Cyrix or AMD.
Anything which doesn't run in privileged mode can be supported by not
implementing CPUID and trapping the illegal opcode fault. If a software
vendor happens to implement the fault by writing "GenuineIntel" and
returning, you can't blame Cyrix or AMD.
--
John Carr (j...@athena.mit.edu)
Thomas D. Barrett
>Someone here came up with a good solution to this: implement a SETCPUID
>function in the clones. If someone runs a program to set the CPU ID to
>"GenuineIntel", you can't blame Cyrix or AMD.
[The following is humor... just wanted to make that clear :-)]
I much prefer "GenuineIntel""[tm]--NOT!!!"
--
|Tom Barrett (TDBear), Sr. Engineer|tom.b...@amd.com|v:512-462-6856 |
|AMD PCD MS-520 | 5900 E. Ben White|Austin, TX 78741 |f:512-462-5155 |
|love yourself, you will dissolve all the stones that are cast -Amy Ray|
Cory C. Albrecht
> g...@Auspex.COM (Guy Harris) writes:
> > load 0 into EAX and do a CPUID, and P5 stuffs
> > "Genu"
> > into EBX,
> > "ineI"
> > into EDX, and
> > "ntel"
> > into ECX. Gag me with a spoon....
>
> So for other values of EAX, do you get the names of the people who
> designed the chip :-) :-)
Forgive me if I haven't been paying attention, but is CPUID a new opcode
on the Pentium, or is it a procedure?
BTW, how do I tell a Pentium apart from a 386 or 486, in software? (I can
do this for 8086s to i486s.) Have enough specs been released yet to the
general public to determine this? :)
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call...@vax.oxford.ac.uk
>
> User-mode:
>
> CMPSXCHG8B, which is an 8-byte "compare-and-exchange"
> instruction, similar to the 486's 4-byte version;
>
> CPUID, which reads the vendor, family, model, and stepping of
> the chip:
>
> load 0 into EAX and do a CPUID, and P5 stuffs
>
> "Genu"
>
> into EBX,
>
> "ineI"
>
> into EDX, and
>
> "ntel"
>
> into ECX. Gag me with a spoon....
>
> load 1 into EAX and do a CPUID, and EAX and EDX get the
> stepping, model, family, and "feature flags"; the latter
> indicate whether there's an on-chip FPU, whether the
> machine check exception is implemented, whether
> CMPXCHG8B is implemented, and stuff for which you have
> to See Appendix H.
>
> RDTSC - "See Appendix H"
>
> Supervisor-mode:
>
> MOV instructions to read and write control register 4; for a
> description of most of the bits in that register, See Appendix
> H.
Hmmm... My impression from the Intel people on the net
was that "Appendix H" just gave performance details (like details
of the pipeline) but that the ISA was public. Was this wrong?
Have Intel really decided to make the privileged ISA secret?
One obvious question becomes, can one write an operating system
for the Pentium using just the public information on the 386/486
privileged ISA and the public information on the Pentium?
>
> RDMSR and WRMSR to read and write model-specific registers; P5
> seems to have some diagnostic registers, and to see what they
> do, See Appendix H.
Fair enough. Not really clear to me what this accomplishes but it
doesn't matter much.
>
> RSM, which returns from system management mode; P5 has the SMM
> stuff in it.
Michael
---
Michael Callahan
call...@vax.ox.ac.uk
call...@math.harvard.edu
Kirk Hays
|> > MOV instructions to read and write control register 4; for a
|> > description of most of the bits in that register, See Appendix
|> > H.
|>
|> Hmmm... My impression from the Intel people on the net
|> was that "Appendix H" just gave performance details (like details
|> of the pipeline) but that the ISA was public. Was this wrong?
|> Have Intel really decided to make the privileged ISA secret?
Most of the bits in CR4 are only described in the document Appendix H
points you to, not in the standard Pentium documentation. The names,
however, are given in the standard documentation.
|> One obvious question becomes, can one write an operating system
|> for the Pentium using just the public information on the 386/486
|> privileged ISA and the public information on the Pentium?
Well, since MSDOS and UNIX (various flavors) exist, and run on the
Pentium, without using the "secret bits", I believe we have a proof
by existance.
I haven't seen the Appendix H material, but since some of the new
flags are named things like "Virtual Interrupt Pending" and "Virtual
Interrupt Flag" in the _User's Guide_, my educated guess would be
that some of Appendix H covers virtualizing the Pentium.
Any bets on who develops the first non-Intel virtual-machine
control OS?
[I don't speak for Intel, etc., etc...]
--
Kirk Hays - NRA Life, seventh generation.
"The only thing necessary for the triumph of evil is for good men to
do nothing." -- Edmund Burke (1729-1797)