comp.lsi.cad Frequently Asked Questions With Answers (Part 1/4) [LONG]
Michael Altarriba
Archive-name: lsi-cad-faq/part1
Posting-Freqency: every 14 days
Url: http://www.ece.ucdavis.edu/sscrl/clcfaq/faq/faq-toc.html
Welcome to comp.lsi.cad / comp.lsi: this is the biweekly posting of fre-
quently asked questions with answers. Before you post a question such as
"Where can I ftp spice from?", please make sure that the answer is not
already here. If you spot an error, or if there is any information that
you think should be included, please send us a note at
clc...@ece.ucdavis.edu.
This FAQ has recently been put on the Web in a much more readable format.
Though it is still under minor construction, all of the pieces are there.
Try it out at <URL:http://www.ece.ucdavis.edu/sscrl/clcfaq/faq/faq-
toc.html> and let us know of any problems or suggestions by mailing to
clc...@ece.ucdavis.edu.
The products and packages described here are intended for research and edu-
cational use. As such, we try to limit our entries to applications which
are available for free or at low cost (< $500). We also wish to limit the
descriptions to at most a page (60 lines) in length.
Bret Rothenberg <roth...@ece.ucdavis.edu>
Wes Hardaker <hard...@ece.ucdavis.edu>
Mike Altarriba <alta...@ece.ucdavis.edu>
Solid State Circuits Research Laboratory
Electrical Engineering and Computer Science
University of California, Davis
Davis, California 95616
----------------------------------------------------------------------
$Id: comp.lsi.cad.FAQ.ms,v 1.150 1997/01/10 00:52:03 altarrib Exp $
Frequently Asked Questions with Answers
! 1: Mosis Users' Group (MUG)
2: Improved spice listing from magic.
3: Tips and tricks for magic (Version 6.3)
4: What can I use to do good plots from magic/CIF?
5: What tools are used to layout verification?
6: EDIF data exchange format.
7: What layout examples are available?
8: How can I get my lsi design fabbed and how much will it cost?
9: Mosis fabrication services.
10: Archive sites for comp.lsi.cad and comp.lsi
11: Other newsgroups and information sources that relate to comp.lsi*
12: Simulation programs tips/tricks/bugs
13: Getting the latest version of the FAQ
14: Converting from/to GDSII/CIF/Magic
15: CFI (CAD Framework Initiative Inc.)
16: What synthesis systems are there?
17: What free tools are there available, and what can they do?
18: What Berkeley Tools are available for anonymous ftp?
19: What Berkeley Tools are available through ILP?
! 20: Berkeley Spice (Current version 3f4)
21: Octtools (Current version 5.1)
22: Ptolemy (Current version 0.5)
23: Lager (Current version 4.0)
24: BLIS (Current version 2.0)
25: COSMOS and BDD
26: ITEM
27: PADS logic/PADS PCB
28: Another PCB Layout Package
29: Magic (Current version 6.5)
30: PSpice
31: Esim
32: iSPLICE3, a mixed-mode simulator for MOS/Bipolar circuits
33: Watand
34: Caltech VLSI CAD Tools
35: Switcap2 (Current version 1.1)
36: Test Software based on Abramovici text
37: Atlanta and Soprano automatic test generators
38: Olympus Synthesis System
39: OASIS logic synthesis
40: T-SpiceTM (was CAzM), a Spice-like table-based analog circuit simulator
41: Galaxy CAD, integrated environment for digital design for Macintosh
42: WireC graphical/procedural system for schematic information
43: LateX circuit symbols for schematic generation
44: Tanner Research Tools (Ledit and LVS) (Commercial Product)
45: SIMIC, a full-featured logic verification simulator
46: LASI CAD System, IC and device layout for IBM compatibles
47: EEDRAW, an electrical/electronic diagramming tool for IBM compatibles
48: MagiCAD, GaAs Gate Array Design through MOSIS
49: XSPICE, extended version of Spice
50: MISIM, a model-independent circuit simulation tool
51: Nelsis Cad Framework
52: APLAC, a general purpose circuit simulation and design tool
53: SLS, a switch-level simulator
54: OCEAN, a sea-of-gates design system
55: ALLIANCE, a CAD package and simulator for teaching digital VLSI design
! 56: ceBox EDIF Viewer and Schematic Generator
57: Analog CMOS VLSI Design Educational Resource Kit
58: TDX Fault Simulation and Test Generation Software
59: Nascent Technologies CDROM - magic and spice releases for Linux
60: Time Crafter 1.0, a timing diagram documentation tool
61: ACS, a general purpose mixed analog and digital circuit simulator
62: LOG/iC, a logic synthesis package for PLDs
63: SIMLAB, a circuit simulation environment
64: Pcb, an X-based PC board design tool
65: SPICE-PAC, A Modular Spice Simulator with Enhancements
66: U.C. Berkeley Low-Power Cell Library
67: The Substrate Resistance Extractor SUBSPACE
68: XRLCAD, A C++ library for manipulating Calma (GDS) and CIF libraries
69: SAVANT, an Analyzer of VHDL Applications for Next-Generation Technology
70: Protel Demos for Windows
71: BPECS PCB Software
72: RF, an RF Circuit Simulation Tool
+ : new item
! : changed
? : additional information for this subject would be appreciated.
1: Mosis Users' Group (MUG)
(From the Microelectronics Systems Newsletter)
Microelectronic Systems News, formerly known as the MOSIS Users' Group
(MUG) Newsletter, includes not only items of interest to those design-
ing integrated circuits for prototyping via MOSIS but also for those
designing, prototyping and producing microelec- tronic systems. Notices
of new items are broadcast to about 1800 subscribers throughout the
world. There is no charge for this service.
To make a contribution or to be added to the email notification list,
please send email to Prof. Don Bouldin at the University of Tennessee,
Knoxville: dbou...@utk.edu
Microelectronic Systems News can now be accessed at:
<URL:http://microsys6.engr.utk.edu/ece/msn>
A variety of design files and CAD tools contributed by the members of the
MOSIS Users' Group (MUG) are now available via anonymous ftp from
"ftp://ftp.mosis.edu/pub/mug" (128.9.0.32). The files "readme" and
"index" should be retrieved first. These files are provided "as is", but
may prove very helpful to those using the MOSIS integrated circuit proto-
typing service.
2: Improved spice listing from magic.
Hierarchical extractions with net names: ext2spice done by Andy Burstein
<burs...@eecs.berkeley.edu>:
This program will do hierarchial extraction using node names. It sup-
ports PS, PD, AS, and AD extraction as well. It is available for ftp
from ftp://ic.eecs.berkeley.edu/pub/spice3/ext2spice.tar .
Poly and well resistance extraction: There are persistent rumors that
people have this working, however, all I have seen is extracted poly
resistor with each end shorted together, ie each end has the same node
name/number.
(This is the most annoying problem that I typically encounter daily. If
ANYONE knows a fix for this, please tell us! I wrote a real quick and
dirty set of scripts/programs to edit the magic file. It will break the
poly contacts and relabel them. This is a real hack, but all other solu-
tions require modification of the magic code itself. This procedure only
works with an extractor that handles labeled nodes, i.e. ext2spice from
above. --WH)
Spice listing from magic with MESFETs.
(from Jen-I Pi <p...@isi.edu>)
We have a revised version (of sim2spice) that goes with version6. It is
available from our anonymous FTP host
"ftp://ftp.mosis.edu/pub/mosis/magic/gaas_extract.tar.Z" (128.9.0.32).
Assuming file inv.ext exist, the procedure for using 'sim2spice' is
ext2sim inv
sim2spice inv.sim
Here's the resulting SPICE decks for SPICE3e...
SPICE 3 Deck created from inv.sim, tech=edgaas
*
z2 3 4 2 efet1.2 2.8
C3 3 0 0.485F
C4 4 0 1.062F
z1 1 4 3 dfet1.2 2.8
*
Commercial Plotting Service
Artwork Conversion offers an IC plotting service. We will take your
CIF/GDSII files and plot them in large format color using an HP 650C
color plotter in 24 hrs at a very reasonable cost.
Designers can FTP files to artwork.com and we will plot them the same day
and return by FedEx.
Fill patterns and line types are completely customizable although most
users select from the 100 preset patterns already defined.
Complete information, specifications and pricing is available from our
Web site: <URL:http://www.artwork.com/plot1.html>.
We are offering universities our best price that we give to high volume
customers: $4.00 per square foot of plotted area.
The plots can be any size (the plotter is 36 inches wide).
We can of course be reached by tel (408) 426-6163 fax 426-2824.
Foundries such as MOSIS, Chip Express and Orbit use this service as well
as many small design shops that cannot justify a large format plotter.
contact: Hagai Pettel ha...@artwork.com or Steve DiBartolomeo
ste...@artwork.com
3: Tips and tricks for magic (Version 6.3)
Searching for nets:
Yes, magic does actually let you search for node names. Use :specialopen
netlist. Then click on the box underneath label, you will be prompted
for the name of the label you want to search for. Enter the name, and
then press enter twice. Click on show, and then find, magic will then
highlight the net.
Bulk node extraction:
Problems with getting the bulk node to extract correctly? Try labeling
the well with the node name that it is connected to.
Painting Wells:
Supposedly :cif in magic will automatically paint in the wells correctly.
However this is not always the case. If you are using mosis 2u technol-
ogy, and your wells are getting strange notches in them, you might try
changing the grow 300 shrink 300 lines in your lambda=1.0(pwell) and
lambda=1.0(nwell) cif sections of your tech file to grow 450 shrink 450.
(Remember you can use :cif see CWN to see nwell, if :cifostyle is nwell,
or :cif see CWP to see pwell if its pwell technology to preview what will
be done with the well. You may use :feedback clear to erase what it
shows you.)
Magic notes available from ftp://gatekeeper.dec.com/pub/DEC/magic/notes
(16.1.0.2):
Magic note.1 - 9/14/90 - ANNOUNCEMENT: Magic V6 is ready
Magic note.2 - 9/19/90 - DOC: Doc changes (fixed in releases after 9/20/90)
Magic note.3 - 9/19/90 - GRAPHICS: Mode problem (fixed 9/20/90)
Magic note.4 - 9/19/90 - HPUX: rindex macro for HPUX 7.0 and later
Magic note.5 - 9/19/90 - GCC: "gcc" with magic, one user's experience
Magic note.6 - 9/19/90 - FTP: Public FTP area for Magic notes
Magic note.7 - 9/20/90 - RSIM: Compiling rsim, one user's suggestions & hints
Magic note.8 - 9/26/90 - GENERAL: Magic tries to open bogus directories
Magic note.9 - 9/26/90 - GRAPHICS: Mods to X11Helper
Magic note.10 - 10/5/90 - DOS: Magic V4 for DOS and OS/2
Magic note.11 - 10/11/90 - GENERAL: reducing memory usage by 600k
Magic note.12 - 12/19/90 - EXT2xxx: fixes bogus resistances
Magic note.13 - 12/19/90 - EXTRESIS: fixed bug in resis that caused coredump.
Magic note.14 - 12/19/90 - EXTRESIS: new version of scmos.tech for extresis
Magic note.15 - 12/19/90 - TECH: documentation for contact line in tech file
Magic note.16 - 12/19/90 - EXTRACT: bug fix to transistor attributes
Magic note.17 - 5/13/91 - CALMA: Incorrect arrays in calma output
Magic note.18 - 5/14/91 - CALMA: Extension to calma input
Magic note.19 - 6/28/91 - IRSIM: Some .prm files for IRSIM
Magic note.20 - 7/18/91 - EXTRESIS: fixes for Magic's extresis command
Magic note.21 - 2/7/92 - FAQ: Frequently asked questions
Magic note.22 - 11/6/91 - CALMA: how to write a calma tape
Magic note.23 - 11/4/91 - EXT2xxx: fix for incorrect resistor extraction
Magic note.24 - 11/8/91 - EXTRESIS: fix 0-ohm resistors
Magic note.25 - 11/15/91 - NEXT: porting magic to the NeXT machine
Magic note.26 - 11/21/91 - IRSIM: fix for hanging :decay command
Magic note.27 - 12/17/91 - RESIS: fix for "Attempt to remove node ..." error
Magic note.28 - 1/28/92 - MAGIC: anonymous FTP now available
Magic note.29 - 3/27/92 - PLOT: support for Versatec 2700
Magic note.30 - 4/8/92 - PATHS: Have the ":source" command follow a path
Magic note.31 - 4/10/92 - MPACK: Mpack now works with Magic 6.3
Magic note.32 - 3/13/92 - AED: Using AED displays with Magic 6.3
Magic note.33 - 3/13/92 - OPENWINDOWS: Compilation for OpenWindows/X11
Magic note.34 - 2/14/92 - OPENWINDOWS: fix mouse problem
Magic note.35 - 8/27/92 - RS6000: diffs to get magic to run on RS6000
4: What can I use to do good plots from magic/CIF?
(Thanks to Douglas Yarrington <ar...@ee.eng.ohio-state.edu> and Harry
Langenbacher <ha...@neuronz.Jpl.Nasa.Gov>, for feedback here.)
CIF:
CIF stands for CalTech Intermediate Form. It's a graphics language which
can be used to describe integrated circuit layouts.
(from Jeffrey C. Gealow <jge...@mtl.mit.edu>)
The definitive description of the Caltech Intermediate Form (CIF Version
2.0) is included in Mead and Conway's book:
@book{mead80,
author = "Carver A. Mead and Lynn A. Conway",
title = "Introduction to {VLSI} Systems",
publisher = "Addison-Wesley",
address = "Reading, Massachusetts",
year = 1980,
call = "TK7874.M37",
A brief description is included in Rubin's book:
@book{rubin87,
author = "Steven M. Rubin",
title = "Computer Aids for {VLSI} Design",
publisher = "Addison-Wesley",
address = "Reading, Massachusetts",
year = 1987,
call = "TK7874.R83",
isbn = "0-201-05824-3"}
Rubin's description should not be considered authoritative. Parts of the
description are not accurate.
cif2ps version 2 (Gordon W. Ross, MITRE):
A much better version of cif2ps, extending the code of cif2ps (Marc
Lesure, Arizona State University) and cifp (Arthur Simoneau, Aerospace
Corp). It features command line options for depth and formatting. Can
extend one plot over several pages (up to 5 by 5, or 25 pages). By
default, uses a mixture of postscript gray fill and cross-hatching.
Options include rotating the image, selecting the hierarchy depth to
plot, and plotting style customization. Plots are in B/W only.
It was posted to comp.sources.misc, and is available by ftp from
ftp://ftp.uu.net/usenet/comp.sources.misc/volume8/cif2ps.Z (192.48.96.9).
cifplot:
Cifplot plots CIF format files on a screen, printer or plotter. Cifplot
reads the .cif file, generates a b/w or color raster dump, and sends it
to the printer. Plots can be scaled, clipped, or rotated. Hierarchy
depth is selectable, as well as the choice of colormap or fill pattern.
An option exists which will compress raster data to reduce the required
disk space. For those plotting to a Versatec plotter, there is also a
printer filter/driver available called vdmp.
oct2ps (available as part of the octtools distribution):
It is possible to convert your .mag file to octtools, and then you may
use oct2ps to print it.
Both cif2ps and oct2ps work well for conversion to postscript. They do
look slightly different, so pick your favorite. Note that cif2ps can be
converted to adobe encapsulated postscript easily by adding a bounding
box comment. oct2ps does convert to color postscript, which can be a
plus for those of you with color postscript printers.
Flea:
Flea ([F]un [L]oveable [E]ngineering [A]rtist) is a program used to plot
magic and cif design files to various output devices. Parameters are
passed to flea through the flags and flag data or through .flearc files
and tech files. Supports: HP7580 plotter, HP7550 hpgl file output,
HP7550 plotter lpr output, Postscript file output, Laser Writer lpr out-
put, Versatec versaplot random output. Options include: Does line draw-
ings with crosshatching for postscript, versatec, and hp plotters. Many
options (depth, label depth, scale, path, format...)
Available by ftp from ftp://zeus.ee.msstate.edu/pub/flea.1.4.1.tar.Z .
pplot:
Can output color PostScript from CIF files. The source is available from:
ftp://anise.ee.cornell.edu/pub/cad/pplot.tar.Z . It only generates PS
files (including color PS), and there's no support for EPS files. It is
limited in its support of cif commands. (Wire, roundflash, and delete
are not supported.) It only supports manhattan geometry (Polygons and
rotations may only be in 90 degree multiples.)
vic:
Part of the U. of Washington's Northwest Lab, for Integrated Systems Cad
Tool Release (previously UW/NW VLSI Consortium). Does postscript and HP
pen plotters. Only available as part of the package.
CIF/Magic -> EPS -> groff/latex
Currently no prgram here directly generates EPS files. It is possible to
add an EPS bounding box (%% BoundingBox: l t b r) to the output from
these programs to get an EPS file. Alternatively, ps2eps or ps2epsf may
be used.
CIF display on PCs
LaSy
(from Frank Bauernoeppel <baue...@informatik.hu-berlin.de>)
The primary goal of LaSy was to implement a simple CIF layout viewer
under MS-Windows.
Requirements:
MS-Windows 3.1 in extended mode or Windows-NT. Hi-resolution colour
display, mouse, and a colour-printer are recommended. Note that there is
a special Windows-NT version of LaSy included: lasy32.exe featuring 32-
bit integer coordinates.
Input:
A CIF file plus appropriate layer description (.lay file). Sample layer
descriptions are included. You probably have to adapt them to your tech-
nology. CIF description see "Introduction to VLSI systems" by Mead and
Conway. Several restrictions apply (cf. online help).
Output:
A layout window for visual inspection/measurements of the layout.
Printer output using Windows printing mechanism, works fine. Clipboard
copy in bitmap and metafile format. The metafile is a flat, object
oriented layout representation understood by many applications. Can be
postprocessed with MSDraw among others. The bitmap gives a pixel
oriented view of the layout (at screen resolution) and can be postpro-
cessed by most "Painting programs".
I have repacked the archive for distribution (some designs removed).
The new url is: <URL:ftp://ftp.informatik.hu-
berlin.de/pub/local/hulda/lasy25.zip>
Two references that describe the CIF file formats are:
Introduction to VLSI Systems, Mead & Conway, 1980, p115
and
Basic VLSI Design, Pucknell & Eshraghian, 1988, p 275
5: What tools are used to layout verification?
Gemini:
Gemini is a graph isomorphism tool for comparing circuit wirelists. The
latest version of Gemini is 2.7 and is now available by FTP from
shrimp.cs.washington.edu (128.95.1.99). Note: Gemini is not available by
anonymous FTP. Send email to Larry McMurchie (la...@cs.washington.edu)
if you need the FTP login and password for Gemini.
Version 2.7 includes a new SIM file format to support four-terminal MOS
transistors. This format is called 'LBL' and was inspired by Mario
Aranha at Lawrence Berkeley Labs. Also some minor bugs have been fixed
concerning portability. The user guide 'gemuser.ps' has been updated to
reflect the changes to the code.
Gemini compiles and runs on a wide variety of architectures, including
Sparc, Mips, DEC AXP, HP, KSR, Intel i860, MC 68020 and VAX, under both
Classic C and ANSI C compliant compilers. As the number of architectures
continues to expand, new portability problems are revealed. Please keep
us informed if you encounter any portability problems or bugs.
Contact:
Larry McMurchie
Computer Science Department, FR-35
University of Washington
Seattle, WA 98195
la...@cs.washington.edu
Tanner LVS:
This is a relatively inexpensive commercial product, see the section on
Tanner tools.
Wellchecker:
(from MUG) ftp ftp.mosis.edu (128.9.0.32)
netcmp:
Part of the caltech tools (see the "Caltech VLSI CAD Tools" section)
6: EDIF data exchange format.
(from Mark Lambert <lam...@cs.man.ac.uk>)
The Electronic Design Interchange Format (EDIF) is the most widely used
EDA standard and is used to interchange design data between CAD systems.
The language is a standard under the auspices of the Electronic Indus-
tries Association (the `EIA'), a US based industry association, responsi-
ble for a number of electronics related standards. EDIF Version 3 0 0,
used for the transfer of connectivity and schematic information, has also
become an IEC standard; IEC 1690.
The latest version of EDIF, Version 4 0 0, promises to add to EDIF Ver-
sion 3 0 0 in the areas of; PCB and MCM Capabilities, Technology Rules
and Manufacturing Drawings
EDIF Version 4 0 0 is currently out for ballot, until 28th May 1996, as
EDIF Version 3 9 9.
EDIF Version 3 9 9 documentation is supplied in CD-ROM form or on paper
directly from the EIA or Framemaker4 hypertext format directly from the
EDIF Technical Centre, on behalf of the EIA. To review the material, the
FrameViewer software is required. To obtain a copy of EDIF Version 3 9 9
(4 0 0), contact either Patti Rusher of the EIA or the EDIF Technical
Centre for detailed instructions.
The EDIF Version 2 0 0 Reference Manual and User Guides and copies of the
manuals or CD-ROM for EDIF Version 3 0 0 can be obtained from the Elec-
tronic Industries Association, Attn. Patti Rusher.
For more EDIF related information visit the EDIF Web site:
and the anonymous ftp server:
ftp://edif.cs.man.ac.uk/pub/edif
An ftpmail server is provided for those without ftp access. Send an empty
email message to: ftp...@cs.man.ac.uk ; a message describing the com-
mands which can be used in further email messages to retreive files will
be sent to you.
An electonic mailing list is available to people interested in EDIF and
for EDIF developers/programmers. Send email to edif-users-
req...@cs.man.ac.uk to be added.
Patti Rusher at the EIA can be contacted at:
Patti Rusher
2500 Wilson Boulevard, Suite 203
Arlington, VA 22201, U.S.A.
Telephone: +1 703 907 7545
Fax: +1 703 907 7501
E-mail: pat...@eia.org
The EDIF Technical Centre can be contacted at:
EDIF Technical Centre, Department of Computer Science,
University of Manchester, Manchester M13 9PL, UK
Tel: +44 161 275 6289
FAX: +44 161 275 6280
E-mail: edif-s...@cs.man.ac.uk
URL: http://www.cs.man.ac.uk/cad/EDIFTechnicalCentre/
7: What layout examples are available?
From MUG:
Analog neural network library of cells, 66-bit Manchester carry-skip
adder, static ram fabricated at 2-micron, an analog op amp, from
ftp://ftp.mosis.edu/pub/mug .
8: How can I get my lsi design fabbed and how much will it cost?
See section on mosis fabrication services as well.
(From MUG 20 George Lewicki of Orbit Semiconductor)
Orbit Semiconductor operates an integrated circuit prototyping service
that accepts designs each week for all of its processes. The service is
available to both U.S. and non-U.S. designers. In- quiries about the
FORESIGHT prototyping service should be ad- dressed to George Lewicki.
Designs can now be submitted directly via email.
Orbit Semiconductor, Inc.
1215 Bordeaux Drive
Sunnyvale, CA 94089
TEL: (408)-744-1800
FAX: (408)-747-1263
Email: fore...@orbsemi.com
(Contributed by Don Bouldin of the University of Tennessee)
Recently, I contacted several foundries to determine which com- panies
are interested in fabricating small to moderate lots of wafers for cus-
tom CMOS designs. I believe many of the readers of this column are
designers who wish to have fabricated only 1,000 to 20,000 parts per
year. There are currently several prototyp- ing services (e.g. MOSIS
and Orbit) that can produce fewer than 100 parts for about $100 each and
there are also several foun- dries which are willing to produce
100,000 custom parts for $5- $20 each (depending on the die size and
yield). My purpose was to identify those companies filling the large
gap between these two services.
The prices in the table below are a result of averaging the data sup-
plied by four foundries. The raw data varied by more than +/- 40% so the
information should be used only in the early stages of budgetary plan-
ning. Once the design specifications are fairly well known, the
designer should contact one or more foundries to obtain specific
budgetary quotes. As the design nears comple- tion, binding quotes can
then be obtained.
The following assumptions were made by the foundries:
All designs will require custom CMOS wafer fabrication using a
double-metal, single-poly process with a feature size between 2.0 and 1.2
microns. The designs may contain some analog circuitry and some RAM
so the yield has been calculated pessimistically. The dies will be pack-
aged and tested at 1 MHz using a Sentry- type digital tester for 5-10
seconds per part. The customer will furnish the test vectors.
Piece Price includes Wafer Fabrication+Die Packaging+Part Testing
Size Package Quantity
|1,000 | 5,000 | 10,000 | 20,000 |100,000
-----------------------------------------------------------------
2 mm x 2 mm; 84 PLCC: | $ 27 | $ 6 | $ 5 | $ 4 | $ 3 |
5 mm x 5 mm; 84 PLCC: | $ 31 | $ 12 | $ 8 | $ 7 | $ 6 |
5 mm x 5 mm; 132 PGA: | $ 49 | $ 30 | $ 25 | $ 22 | $ 18 |
7 mm x 7 mm; 132 PGA: | $ 65 | $ 44 | $ 36 | $ 31 | $ 27 |
Lithography charges: $ 20,000 - $ 40,000
Preferred Formats: GDS-II or CIF Tapes
Additional charges for Second-Poly: $ 5,000
(This is from MUG 19, there is also a list of foundries that these prices
were derived from. In the interested of saving space, I have ommitted
the list. The list is available from MUG's ftp site included in MUG
newsletter #19.)
9: Mosis fabrication services.
(From Mosis) Information is available from mosis for pricing and fab
schedules through an automatic email system:
Mail to mo...@mosis.edu with the message body as follows:
REQUEST: INFORMATION
TOPIC: TOPICS
REQUEST: END
for general information and a list of available topics.
If you need to contact a person at mosis, you may mail to mo...@mosis.edu
with REQUEST: ATTENTION.
Also anonymous ftp is available. ftp to ftp.mosis.edu. This is a dupli-
cation of all files that are available from the mail server.
(From MUG 20 Contributed by Don Bouldin of the University of Tennessee)
Multi-project fabrication of BICMOS designs are already available to
European universities via CMP and to Canadian universities via the Cana-
dian Microelectronic Corporation. However, in the United States, the
demand for BiCMOS fabrication via MOSIS has not been considered signifi-
cant. MOSIS is currently planning to start offering 0.5-micron BiCMOS
during the first quarter of 1994. This will have a core voltage operation
of 3.3v and a clock frequency in the range of 220-250Mhz. MOSIS is
interested in seeing if a larger demand exists in the community than
expressed so far.
If you would like to have BiCMOS available before 1994, please send a
short note to mo...@mosis.edu (with a copy to bou...@sun1.engr.utk.edu)
using the following format.
REQUEST: ATTENTION
.
.
your message goes here
.
.
REQUEST: END
(From MUG 20 and Chris Donham of the University of Pennsylvania)
Support for mosis technologies under Cadence Analog Artist 2.4 is avail-
able as is from University of Pennsylvania. This includes DRC, LVS, EXT,
and a beginner's guide. Currently they are working on support for Opus
4.2. The files supporting Artist 2.4 are currently available via
anonymous FTP. Penn is not affiliated with MOSIS, except as a satisfied
customer, and as a result, NO WARRANTY IS EXPRESSED OR IMPLIED WITH
REGARDS TO THE FILES, OR THEIR FITNESS FOR ANY USE. Use the files at
your own risk. To obtain the files, FTP to axon.ee.upenn.edu
(130.91.6.208), using the name "anonymous" and your mailing address as
the password. The files are in the "pub" directory.
Penn is in the process of switching from Artist 2.4 to Opus 4.2. The
manual is being rewritten, and the support files are being updated.
Technology files supporting DRC, Extract, and Compare are currently in
beta-test. If problems or bugs are detected, please send email to
"cad...@axon.ee.upenn.edu".
10: Archive sites for comp.lsi.cad and comp.lsi
(None of these are comprehensive archives, rather, they have about 3
postings each)
comp.lsi.cad:
ftp://cnam.cnam.fr/pub/Archives/comp.archives/auto/comp.lsi.cad
ftp://cs.dal.ca/pub/comp.archives/comp.lsi.cad
ftp://srawgw.sra.co.jp/.a/sranha-bp/arch/arch/comp.archives/auto/comp.lsi.cad
11: Other newsgroups and information sources that relate to comp.lsi*
alt.cad
comp.cad.cadence
comp.lang.verilog
comp.lang.vhdl
comp.sys.mentor
sci.electronics
The following gopher link points to a collection of information from
pulled from newsgroups like comp.lsi.cad, comp.lsi, and other cad related
sources.
gopher://kona.ee.pit.edu/
12: Simulation programs tips/tricks/bugs
Berkeley spice:
Pspice:
Hspice:
If your simulation won't converge for a given DC input, you can ramp the
input and print the DC operating point and then set the nodes that way
for future simulations.
A number of documents are available for information on BSIM model parame-
ters: (from Mark Johnson, as posted to comp.lsi <mjoh...@netcom.com>)
1. The very best written description I have seen is in a software manual.
The good news is that this manual is free; the bad news is that you
have to buy the multi-thousand-dollar program in order to get the free
manual. The program is HSPICE from Meta-Software Inc (Campbell,
Calif., USA). The HSPICE User's Manual, chapter 7, gives all the
details you'd ever want to know regarding BSIM parameters.
2. The second best description I have seen of BSIM is in, strangely
enough, a manual for BSIM2 (!). It is available from the University
of California at Berkeley. Telephone (510)-643-6687 and they will
give you instructions on how to buy the manual. (They'll probably
suggest that you might want to buy some software too).
J.S. Duster, M.C. Jeng, P.K. Ko, and C. Hu, "Users
Guide for the BSIM2 Parameter Extraction Program and
the SPICE3 with BSIM Implementation"
3. You can learn some things about BSIM parameters by reading about pro-
grams which extract the parameters from measured data. UC Berkeley
offers several programs and manuals for this. The one that I person-
ally prefer is
M.C. Jeng, B.J. Sheu, and P.K. Ko: "BSIM Parameter
Extraction - Algorithms and User's Guide," Memo
No. UCB/ERL M85/79, 7 October 1985.
4. Next, look at Sheu's Ph.D. thesis. He is the guy who combined the
Bell Labs CSIM model with a bunch of other published equations, and
formulated BSIM. It's available from the same phone number.
B.J. Sheu, "MOS Transistor Modelling and Characterization
for Circuit Simulation", Memo No. UCB/ERL M85/85,
26 October 1985
5. The worst description (in +my+ opinion of course) is unfortunately in
the most-accessible publication. To save space in the journal they
left out some parameter discussions and (again in my opinion) produced
a disjointed, not-fully- informative paper. Others may have different
views, naturally.
B.J. Sheu, D.L. Scharfetter, P-K Ko, M-C Jeng, "BSIM:
Berkeley Short-Channel IGFET Model for MOS Transistors,"
IEEE Journal of Solid-State Circuits, Vol SC-22, No. 4,
August 1987, pp. 558-565.
13: Getting the latest version of the FAQ:
Mail to lsi-faq...@ece.ucdavis.edu with the subject "send faq".
If you wish to be added to the FAQ mailing list, send a note to lsi-faq-
req...@ece.ucdavis.edu with subject heading 'subscribe'. You will then
have the FAQ regularly emailed to the return address of the note. Like-
wise, use the subject heading 'unsubscribe' to be removed from the list.
This FAQ is now cross-posted to news.answers and comp.answers. This news-
group is archived periodically on
ftp://rtfm.mit.edu/pub/usenet/news.answers/lsi-cad-faq [18.181.0.24].
Postings are archived as "part1" through "part4".
Our FAQ is also available through the WWW pages. You can access it at
<URL:http://www.ece.ucdavis.edu/sscrl/clcfaq/faq/faq-toc.html> . I sug-
gest this site above the one listed below, since ours is hyper-text for-
matted and the site below is essentially just a text to html conversion
with no table of contents.
(from Thomas A. Fine <fi...@cis.ohio-state.edu>)
WWW I maintain an "archive" of news.answers available via WWW. As a
matter of fact, I used WWW to read through your posting just last week.
I found it very informative; thanks much. Advertise the following refer-
ence to get to the archive in general:
<URL:http://www.cis.ohio-state.edu:80/hypertext/faq/usenet/FAQ-
List.html>
or to get to your particular FAQ, give out this reference:
<URL:http://www.cis.ohio-state.edu:80/hypertext/faq/usenet/lsi-cad-
faq/top.html>
Gopher The news.answers introduction (which I pulled up in WWW ;-) lists
the following gopher sites for the FAQs:
cc1.kuleuven.ac.be port 70
jupiter.sun.csd.unb.ca port 70
gopher.univ-lyon1.fr, port 70
ftp.win.tue.nl, port 70
gopher.win.tue.nl, port 70
kona.ee.pitt.edu 70
To reference gopher from Mosaic, us the following reference:
gopher://kona.ee.pitt.edu WAIS
I pulled this straight out of the news.answers Introduction:
Note that the periodic posting archives on rtfm.mit.edu are also accessi-
ble via WAIS (the database name is "usenet" on port 210). If you don't
know what WAIS is, don't worry about it, although you can look in
comp.infosystems.wais if you're curious. And don't write to us and ask,
please; we unfortuately already have too many things to deal with without
having to answer questions about other people's software.
14: Converting from/to GDSII/CIF/Magic
Magic version 6.3 is capable of reading and writting to all three for-
mats. (From the magic man page):
calma [option] [args]
This command is used to read and write files in Calma GDS II Stream for-
mat (version 3.0, corresponding to GDS II Release 5.1). This format is
like CIF, in that it describes physical mask layers instead of Magic
layers. In fact, the technology file specifies a correspondence between
CIF and Calma layers. The current CIF output style (see cif ostyle) con-
trols how Calma stream layers are generated from Magic layers.
(from Jeffrey C. Gealow <jge...@mtl.mit.edu>)
Calma Company sold their electronics CAD/CAM software (GDS II) to Valid
Logic Systems which later merged with Cadence.
Cadence has added a few extensions. A Cadence document is almost identi-
cal to the old Calma Company document:
Cadence Design Systems, Inc.
Construct Stream Format
Reference
Version 4.0
August 1991
900-001094
An overview of the Stream format is included in Rubin's book:
@book{rubin87,
author = "Steven M. Rubin",
title = "Computer Aids for {VLSI} Design",
publisher = "Addison-Wesley",
address = "Reading, Massachusetts",
year = 1987,
call = "TK7874.R83",
isbn = "0-201-05824-3"}
cif [option] [args]
Read or write files in Caltech Intermediate Form (CIF).
15: CFI (CAD Framework Initiative Inc.)
(From Randy Kirchhof <r...@cfi.org>)
CFI quick FAQ guide for release 1.0, v1.1
For those of you who may be unfamiliar with our work, The CAD Framework
Initiative Inc. was formed in May 1988. We're located in Austin, TX,
although we're a distributed company. We're a not-for-profit consortium
formed under the laws of the state of Delaware. Our mission is to pro-
vide industry-accepted standards and technology that enable interopera-
bility of electronic design automation (EDA) applications and data for
end-users and suppliers world-wide. This includes interoperability
between EDA applications as well as the integration of EDA applications
into CAD frameworks.
A CAD framework is a software infrastructure which provides a common
operating environment for CAD tools. Through a framework, a user should
be able to launch and manage tools, create, organize, and manage data,
graphically view the entire design process and perform design management
tasks such as configuration management, version management, etc. CFI
Release 1.0 started shipping in January 1993.
Q When can users buy CFI compliant tools?
A Eleven vendor companies have announced EDA products and frameworks
which will be available and compliant with CFI 1.0 standards. CFI
has initiated a formal certification program for these (and future
products) as of 12/93. CFI expects to begin awarding the first
certification brand marks in the first quarter of 1994. We expect
to see a rapid expansion of compliant products beginning in the
third quarter of 1994.
Q How can the Standards be obtained? Are there any restrictions?
A The 1.0 Standards, copyrighted by CFI, are available to members
and non-members priced as a set or individually through CFI Member
Services (512) 338-3739. They will also being distributed under
license by Cadence, Mentor Graphics, and Viewlogic as part of
their product documentation. Versions of the 1.0 Standards are
available on diskette in an electronic format as well as bound
manuals.
Q How do the CFI Standards relate to vendor framework programs like
Mentor's Open Door, Viewlogic Power Team and Cadence Connection
Partners - with so many point tool vendors participating, don't
they have this problem solved?
A The major EDA vendors have been and continue to be challenged by
their customers over multi-vendor integration. These programs
were a practical response by opening up their existing interfaces
and providing services to assist integration. CFI 1.0, and future
releases, will create a functional alternative to a growing subset
of those interfaces so that the requirement that point tool ven-
dors create partnership specific versions of their tool will
decrease. Actually, the service provided through these programs
will likely compliment the CFI certification effort as these
supplier's frameworks become fully certified.
Contact: c...@cfi.org (CFI Member Services, Jean Gallagher) CFI Main number:
(512) 338-3739 Fax: (512) 338-3853
16: What synthesis systems are there?
Thanks to Simon Leung <sle...@sun1.atitech.ca>, Michel Berkelaar
<mic...@ele.tue.nl>, Noritake Yonezawa <yone...@cs.uiuc.edu>, Donald A
Lobo <lo...@guardian.cs.psu.edu>, Greg Ward <gr...@bnr.ca>, Peter Duzy,
Robert Walker <wal...@turing.cs.rpi.edu>, Heinrich Kraemer
<kra...@fzi.de>, Luciano Lavagno <luc...@ic.eecs.berkeley.edu>
ADPS
- Case Western Reserve University, USA
- scheduling and data path allocation
- Papachristou, C.A. et al.: "A Linear Program Driven Scheduling and
Allocation Method Followed by an Interconnect Optimization Algorithm",
Proc. of the 27th DAC, pp. 77-83, June 1990.
ALPS/LYRA/ARYL
- Tsing Hua University
- scheduling and data path allocation
- Lee, J-H: et al.: "A New Integer Linear Programming Formulation of
the Scheduling Problem in Data Path Synthesis", Proc. of ICCAD89, pp.
20-23, November 1989.
BDSYN
- University of California, Berkeley, USA
- FSM synthesis from DECSIM language for multilevel combination-logic
realization
- Brayton, R.: "Multiple-level Logic Optimization System", Proc. of IEEE
ICCAD, Santa Clara, Nov. 1986
BECOME
- AT & T Bell Labs, USA
- FSM synthesis from C-like language for PLA, PLD and standard cell realization
- Wei, R-S.: "BECOME: Behavior Level Circuit Synthesis Based on Structure
Mapping", Proc. of 25th ACM/IEEE Design Automation Conference, pp. 409-414,
IEEE, 1988
BOLD
- logic optimization
- Bartlett, K. "Synthesis and Optimization of Multilevel Logic Under Timing
Constraints", IEEE Transactions on Computer-Aided Design, Vol 5, No 10,
October 1986
BRIDGE
- AT & T Bell Labs, USA
- High-level synthesis FDL2-language descriptions
- Tseng: "Bridge: A Versatile Behavioral Synthesis System", Proc. of 25th
ACM/IEEE Design Automation Conference, pp. 415-420, IEEE, 1988
Michael Altarriba
Archive-name: lsi-cad-faq/part2
CADDY
- Karlsruhe University, Germany
- behavioral synthesis using VHDL as the input/output language, based on
data-flow analysis; automated component selection (allocation), scheduling,
and assignment. Different architechture styles are supported, such as
multiplexers vs busses and two-phase vs single phase clocks.
- Camposano, R.: "Synthesing Circuits From Behavioral Descriptions", IEEE
Transactions on Computer-Aided Design, Vol. 8, No. 2, February 1989
Rosenstiel, W., Kraemer, H.: "Scheduling and Assignment in High-Level
Synthesis", in 'High-Level VLSI-Synthesis' R. Camposano, W. Wolf Ed.
Kluwer, 1991
Gutberlet P., Mueller J., Kraemer H., Rosenstiel W.: "Automatic Module
Allocation in High-level Synthesis", Proc. of 1st EURO-DAC, 1992
CALLAS
- Siemens, Germany
- highlevel, algortihmic and logic synthesis (contains CADDY, see
above)
- Koster, M. et al.: "ASIC Design Using the High-Level Synthesis
System CALLAS: A Case Study", Proc. IEEE International Conference on
Computer Design (ICCD '90), pp. 141-146, Cambridge, Massachusetts,
Sept. 17-19, 1990
CAMAD
- Linkoping University, Sweden
- scheduling, data path allocation and iteration from a Pascal subset
- Peng, Z.: "CAMAD: A Unified Data Path/ Control Synthesis
Environment", Proc. of the IFIP Working Conference on Design
Methodologies for VLSI and Computer Architecture, pp. 53-67, Sept.
1988.
CARLOS
- Karlsruhe University, Germany
- multilevel logic optimization for CMOS realizations
- Mathony, H-J.: "CARLOS: An Automated Multilevel Logic Design System for
CMOS Semi-Custom Integrated Circuits", IEEE Transactions on Computer-Aided
Design, Vol 7, No 3, pp. 346-355, March 1988
CATHEDRAL
- Univ. of Leuve, Phillips and Siemens, Belgium
- synthesis of DSP-circuits from algorithm descriptions
- De Man, H.: "Architecture-Driven Synthesis Techiques for VLSI Implementation
of DSP Algorithms", Proceedings of the IEEE, Vol. 78, NO. 2, pp. 319,
February 1990
CATREE
- Univ. of Waterloo, Canada
- scheduling and data path allocation
- Gebotys, C.H.: "VLSI Design Synthesis with Testability", Proc. of
the 25th DAC, pp. 16-21, June 1988
CHARM
- AT & T Bell Labs., USA
- data-path synthesis
- Woo, N-S.: "A Global, Dynamic Register Allocation and Binding for a
Data Path Synthesis System", Proc. of the 27th DAC, pp. 505-510, June 1990.
CMU-DA (2)
- Carnagie-Mellon University, USA
- behavioral synthesis from ISPS
- Thomas, D.: "Linking the Behavioral and Structural Domains of Representation
for Digital System Design", IEEE Transactions on Computer-Aided Design, pp.
103-110, Vol. 6, No. 1, January 1987
CONES
- AT & T Bell Labs, USA
- FSM synthesis, produces 2-level logic realizations (truth-table)
- Stroud, C.E.: "CONES: A System for Automated Synthesis of VLSI and
programmable logic from behavioral models", Proc. of IEEE ICCAD, Santa Clara,
Nov. 1986.
DAGAR
- University of Texas, Austin, USA.
- scheduling and data-path allocation
- Raj. V.K.: "DAGAR: An Automatic Pipelined Microarchitecture
Synthesis System", Proc. of ICCD '89, pp. 428-431, October 1989.
DELHI
- IIT
- design iteration, scheduling and data path allocation
- Balakrishnan, M. et al.: "Integrated Scheduling and Binding: A
Synthesis Approach for Design Space Exploration", Proc. of the 26th
DAC, pp. 68-74, June 1989
DESIGN AUTOMATION ASSISTANT (DAA)
- AT & T Bell Labs, USA
- expert system for data path synthesis
- Kowalski, T.J. "The VLSI Desig Automation Assistant: An Architecture
Compiler", Silicon Compilation, pp. 122-152, Addison-Wesley, 1988
ELF
- Carleton University, Canada
- scheduling and data path allocation
- Girczyc, E.F. et al.: "Applicability of a Subset of Ada as an
Algorithmic Hardware Description Language for Graph-Based Hardware
Compilation", IEEE Trans. on CAD, pp. 134-142, April 1985.
EUCLID
- Eindhoven University of Technology, Netherlands
- logic synthesis
- Berkelaar, Michel R.C.M. and Theeuwen, J.F.M., "Real Area-Powe-Delay
Trade-off in the EUCLID Logic Synthesis System" , proceedings of the Custom
Integrated Circuits Conference 1990, Boston MA USA, pp 14.3.1 ff
EXLOG
- NEC Corporation, Japan
- expert system, synthesizes gate level circuits from FDL descriptions
- M. Watanabe, et al.,: "EXLOG: An Expert System for Logic Synthesis in
Full-Custom VLSI Design", Proc. of 2nd Int. Conf. Application of Artificial
Intelligence, August 1987.
FACE/PISYN
- General Electric, USA
- FACE: high-level synthesis tools and a tool framework, PISYN:
synthesis of pipelined architecture DSP systems (mostly)
- Smith, W.D. et al.: "FACE Core Environment: The Model and it's
Application in CAE/CAD Tool Development", Proc. of the 26th DAC, pp.
466-471, June 1989.
FLAMEL
- Stanford University, USA
- data path and control-logic synthesis from Pascal description
- Trickey, H. "Flamel: A High-Level Hardware Compiler", IEEE Transactions
on Computer-Aided Design, Vol 6, No 2, March 1987.
HAL
- Carleton University, Canada
- data path synthesis
- Paulin, P.: "Force-Directed Scheduling for the Behavioral Synthesis of
ASIC's", IEEE Transaction on Computer-Aided Design, pp. 661,
Vol. 8, No. 6, June 1989.
HARP
- NTT, Japan
- scheduling and data path-allocation from FORTRAN
- Tanaka, T. et al.: "HARP: Fortran to Silicon", IEEE Trans. on CAD,
pp. 649-660, June 1989.
HYPER
- UCB, USA
- synthesis for realtime applications (scheduling, allocation, module
binding, controller design)
- Chu, C-M. et al.: "HYPER: An Interactive Synthesis Environment for
Real Time Applications", Proc. of ICCD '89, pp. 432-435, October 1989
IMBSL/RLEXT
- Univ. of Illinois, USA
- data-path allocation, RTL-level design
- Knapp D.W.: "Manual Rescheduling and Incremental Repair of Register
Level Data Paths", Proc. of ICCAD '89, pp.58-61, November 1989.
LSS (Logic Synthesis System)
- IBM, USA
- logic synthesis and optimization from many RTL-languages
- Darringer, J. et al. "LSS: A System for Production Logic Synthesis",
IBM Journal of Research and Developement, vol. 28, No. 5, pp. 272-280,
Sept 1984.
MAHA
- University of Southern California, USA
- data path synthesis
- Parker, A.C. "MAHA: A Program for Data Path Synthesis", Proc. 23rd ACM/IEEE
Design Automation Conference, pp. 252-258, IEEE 1986.
MIMOLA
- University of Dortmund, Germany
- scheduling, data-path allocation and controller design
- Marwedel, P. "Matching System And Component Behavior in MIMOLA
Synthesis Tools", Proc. of EDAC '90, pp. 146-156, March 1990.
OLYMPUS/HERCULES
- Stanford University, USA
- behavioral synthesis from C-language (HERCULES), logic and physical
synthesis
- De Micheli, G.: "HERCULES - A System for High-Level Synthesis", Proceedings
of the 25th ACM/IEEE Design Automation Conference, pp. 483-488, IEEE 1988
SEHWA
- University of Southern California, USA
- pipeline-realizations from behavioral descriptions
- Park, N. "SEWHA: A Program for Synthesis of Pipelines", Proc. 23rd ACM/IEEE
Design Automation Conference, pp. 454-460, IEEE 1986.
SIEMENS' SYNTHESIS SYSTEM
- Siemens, Germany
- partitioning, data path allocation and scheduling
- Scheichenzuber, J. et al.: "Global Hardware Synthesis from
Behavioral Dataflow Descriptions", Proc. of the 27th DAC, pp. 456-461,
June 1990.
SIS (formerly MIS (II/MV))
- University of California, Berkeley, USA
- synthesis and verification system for sequential logic
- E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai,
A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton,
A. Sangiovanni-Vincentelli: "SIS: A System for Sequential Circuit
Synthesis", Tech report UCB/ERL M92/41, University of California,
Berkeley, CA, May 1992
SOCRATES
- General Electric, University of Colorado, USA
- expert system
- logic optimization and mapping for different technologies
- de Geus, A.J., "The Socrates Logic Synthesis and Optimization System",
Design Systems for VLSI Circuits, pp. 473-498, Martinus Nijhoff Publishers,
1987.
SPAID
- Universty of Waterloo, Canada
- DSP-synthesis for silicon compiler realizations
- Haroun, B.: "Architectural Synthesis for DSP Silicon Compilers", IEEE
Transactions on Computer-Aided Design, pp. 431-447, Vol. 8, No 4, April 1989.
SYNFUL
- Bell-Northern Research, Canada
- RTL and FSM synthesis for a production environment
- G. Ward, "Logic Synthesis at BNR: A SYNFUL Story", Proceedings
Canadian Conference on Very Large Scale Integration, October 1990.
SYSTEM ARCHITECT'S WORKBENCH
- Carnagie-Mellon University, USA
- behavioral synthesis
- Thomas, D. "The System Architect's Workbench", Proceedings of the 25th
ACM/IEEE Design Automation Conference, pp. 337-343, IEEE 1988
UCB'S SYNTHESIS SYSTEM
- UCB, USA
- transformations, scheduling and data path allocation
- Devadas, S.: "Algorithms for Hardware Allocation in Data Path
Synthesis", IEEE Trans. on CAD, pp. 768-781, July 89
V COMPILER
- IBM, USA
- scheduling and data path allocation from V-language
- Berstis, V: "The V Compiler: Automatic Hardware Design", IEEE Design
and Test, pp. 8-17, April 1989.
VSS
- Univ. of California at Irvine, USA
- transformations, scheduling and data path allocation from VHDL to
MILO
- Lis, J. et al.: "Synthesis from VHDL", Proc. ICCD'88, pp. 378-381,
October 1988.
YORKTOWN SILICON COMPILER
- IBM T.J.Watson Research Centre, USA
- data path synthesis, logic synthesis etc.
- Brayton, R.K., et al. "The Yorktown Silicon Compiler", Silicon Compilation,
pp. 204-311, Addison-Wesley, 1988
17: What free tools are there available, and what can they do?
(This section can be viewed as a cross reference to the detailed descrip-
tion of software that follows.)
Analog VLSI and Neural Systems: Caltech VLSI CAD Tools
Automated place and route: octtools, Lager
Digital design environment: Galaxy CAD
Lsi (polygon) schematic capture: magic, octtools(vem)
Layout Verification: caltech tools (netcmp), gemini (Washington
Univerity), wellchk (MUG)
PCB auto/manual place and route: PADS pcb, PCB (Just for testing lsi
designs, of course :)
Simulation: irsim(comes with magic), esim, pspice, isplice3, watand,
switcap2.Synthesis: octtools, blis, Lager, item, (see section on synthesis)
Standard schematic capture: PADS logic, PSPICE for windows
18: What Berkeley Tools are available for anonymous ftp?
available from ftp://ic.eecs.berkeley.edu/pub
adore: switched capacitor layout generator. (Requires Octtools 5.1 to
compile.)
bdd:
road: analog layout router
sis: simplifies both sum-of-products and generic multi-level boolean
expressions; it includes many tools including espresso, bdd
ext2spice: enhanced ext2spice for use with magic
available from ftp://gatekeeper.dec.com/pub/misc
espresso: simplifies sum-of-products boolean expressions
19: What Berkeley Tools are available through ILP?
(From MUG 20 Contributed by Carol Block of U. C. Berkeley)
A new version of the popular circuit simulator, Spice3F2, is now avail-
able from the Industrial Liaison Program (ILP) Office at the University
of California, Berkeley. A new release of Octtools will be forthcoming
in 1993. Enclosed is a list of software distributed by this office.
Adore, BBL.2, Berkeley Building-Block Layout System, Berkeley Computer
Integrated Manufacturing System, Parameter Extraction Program for BSIM,
Parameter Extraction for BSIM2, Bear-FP, Bert, BLIS, Spice 2G with BSIM
Implementation, Cider, Ditroff/Gremlin, Ecstasy, EDIF 2 0 0, Elogic,
ES1:Electrostatis 1-Dimensional Periodic Plasma, Franz Lisp, Glitter,
IBC: Traveling-Wave-Tube Simulation, IEEE-754 Test Vector, Jsim, Jspice,
Lanso, Magic-X11R3-Patch, Magic 1990 Decwrl/Livermore Release, Mahjong,
Mighty, Octtools, Parmex Pix-Parmex, Plasma Device Simulation Codes, PLA
Tools, Proteus, Ptolemy, Relax, Ritual, Sample, Sample-3D, Additional
SAMPLE Documentation, Simpl-IPX and Simpl System 5, SIS, SPAM, Sparse,
Spectre, Spice 2G6, Spice 3F2, Additional SPICE Documentation, Splat,
Splice 3.0, Supercrystal, SWEC, Tempest, TimberWolf 3.2, Tsize, 1986 VLSI
Tools, Wombat.
Within a few weeks, a new catalog will be available via anonymous FTP.
Users will also be able to obtain forms, ordering instruc- tions and some
software via this means. Generally, recipients will have to com-
plete an Agreement Form and pay a documentation and handling fee of about
$250 per program.
ILP can now distribute most of its programs in a variety of media,
including: QIC-120, QIC-150, QIC-320, 8mm (2.2 gig), TK 50 (DEC tape for-
mat), 9-track 1600 bpi and 9-track 6250 bpi. Visa and Mastercard ord-
ers will be accepted on-line by 1993. Most of the software may be freely
redistributed either within an organi- zation or to other organiza-
tions, both within the United States and abroad, subject to the certain
restrictions, including all U.S. Government restrictions, particu-
larly those concerning ex- port.
(from blurb+ftp, in the ILP distribution)
If you have access to ftp, then the tape is free (you just get to suck it
over by yourself) and you have to remember to print out the docs yourself
too. The usual anonymous ftp rules:
Name: ftp://ic.eecs.berkeley.edu/edif
Address: 128.32.132.1
|-EDIFWorld89.ps
|-Release_7.6-notes-reversed.ps
|-Release_7.6-notes.ps
|-Release_7.6.tar.Z
edif-|-agreement-reversed.ps
|-agreement.ps
|-agreement.tex
|-assurance-reversed.ps
|-assurance.ps
|-assurance.tex
|-blurb
|-blurb+ftp
Other Ports
-------------------------------------------------------------------- I
I have a port of the system for SysV, Apollo and HP machines as well
which is available on request. Most of these operating systems are
mature enough now to work directly with Release 7.6. The system has been
ported to other non-Unix machines such as VMS, the mac, and various main-
frame architectures; these latter being a nontrivial effort on the part
of the individuals involved, but it was accomplished. I do not have
these ports; I just know that they are possible because they have been
performed by others.
For additional information, contact:
Industrial Liaison Program
205 Cory Hall
Software Distribution Office
University of California at Berkeley
Berkeley, CA 94720
TEL: (510) 643-6687
FAX: (510) 643-6694
ilpso...@eecs.berkeley.edu
20: Berkeley Spice (Current version 3f4)
(From spice_info on ic.eecs.berkeley.edu)
Upgrading from Spice 3f2 to 3f4
The current version is 3f4. This is derived from version 3f2 by applying
a patch. The patch is available via ftp from ic.eecs.berkeley.edu.
Acquiring Spice 3f2
For more information on how to acquire Spice3f2, please send your physi-
cal mailing address to "ilpso...@eecs.berkeley.edu" and request a
software catalog. This will give you all of the necessary information
for ordering Spice3f2 and other Berkeley CAD software, including an order
form and use agreements. At last check, the cost for spice3f2 was
$250.00 (this price may change without notice).
Systems supported and Formats Supplied
Spice3f2 has been compiled on the following systems:
Ultrix 4, RISC or VAX
SunOS 4, Sun3 or Sun4
AIX V3, RS/6000
HP-UX 8.0, 9000/700
MS-DOS on the IBM PC, using MicroSoft C 5.1 or later
The following systems have been successfully tested either in the past or
by someone outside of UC Berkeley.
Dynix 3.0, Sequent Symmetry or Balance (does _not_ take advantage of
parallelism)
HP-UX 7.0, 9000/300
Irix 3.2, SGI Personal Iris
NeXT 2.0
Apple MacIntosh, Using Think C
Spice3f2 is distributed in source form only. The C compiler "gcc" has
been used successfully to compile spice3f2, as well as the standard com-
pilers for the systems listed above.
Spice3 displays graphs under X11, PostScript, or a graphics-terminal
independent library, or as a crude, spice2-like line-printer plot. On
the IBM PC, CGA, EGA, and VGA displays are supported through the Micro-
Soft graphics library. Note in particular that there is no Suntools
interface.
Note the the X11 interface to Spice3 expects release 4 or later, and
requires the "Athena Widgets Toolkit" ("Xaw") which may be available only
in the "unsupported" portion of your vendor software. A version of
"OpenWindows" has problems due to undefined routines during linking --
linking with a null copy of these routines has reportedly worked, but
"OpenWindows" has not been tested in any way for this release.
Note that for practical performance a math co-processor is required for
an IBM PC based on the 286 processor. A math co-processor is also recom-
mended for the more advanced IBM PC systems.
(from posting to comp.lsi.cad) The Windows NT port of spice3e2, Spice32,
is available via ftp from site
ftp://ftp.cica.indiana.edu/pub/pc/win3/nt/spice100.zip . A similar port
of nutmeg is included.
(from Robert Zeff <rob...@koko.csustan.edu>)
I have revised my on line help for Spice32 / Nutmeg32 for Windows NT and
Win3.1 to Berkeley's version 3F4. It is available by ftp from
ftp://csustan.csustan.edu/pub/spice/nutmeg.hlp . I have removed the exe-
cutables for DOD complience. For access, see the readme file in that
directory.
I've updated my Spice circuit simulator to 3F5 and have included the
BSIM3v3 level 8 mosfet model. You can get it at
Sometime it will also be available (ftp) at
csustan.csustan.edu/pub/spice/i386 or www.zapco.com Yes, it does work on
Win95.
The Unix distribution comes on 1/2" 9-track tape in "tar" format, TK50
tape (DEC tape), or QIC-150 1/4" cartridge tape (Sun cartridge tape).
The MS-DOS distribution comes on several 3.5" floppy diskettes (both high
and low density) in the standard MS-DOS format. The contents of both
distributions are identical, including file names.
New features in 3f2
The following is a list of new features and fixes from the previous major
release of Spice3 (3e.2) (see the user's manual for details):
AC and DC Sensitivity.
MOS3 discontinuity fix ("kappa").
Added a new JFET fitting parameter.
Minor initial conditions fix.
Rewritten or fixed "show" and "trace" commands.
New interactive commands "showmod" and "alter".
Minor bug-fixes to the Pole-Zero analysis.
Miscellaneous bug fixes in the front end.
Additional features since release 3d.2 are:
Lossy transmission line model (not available under MS-DOS).
Proper calculation of sheet resistance in MOS models.
A new command ("where") to aid in debugging troublesome
circuits.
Smith-chart plots improved.
Arbitrary sources in subcircuits handled correctly.
Arbitrary source reciprocal calculations and DC biasing
now done correctly.
Minor bug-fixes to the Pole-Zero analysis.
Miscellaneous bug fixes in the front end.
A Note on Version Numbering
Spice versions are numbered "NXM", where "N" is a number representing the
major release (as in re-write), "X" is a letter representing a feature
change reflected by a change in the documentation, and "M" is a number
indicating a minor revision or bug-patch number.
FTP Access and Upgrades
There is no anonymous ftp access for the Spice3 source(see below). The
manual for spice3f2 (in it's postscript format) is available via
anonymous ftp from ftp://ic.eecs.berkeley.edu/pub/spice3/um.3f.ps . If
you are interested in the troff/me source, contact the email address
below (the "make" files and whatnot are somewhat cumbersome for the
manual).
Patches or upgrades for Spice3 are _not_ normally supplied, however we
have made exceptions to this rule, particularly in the case of minor ver-
sion changes (such as 3f2 to 3f3).
Email Address for Problems
Please direct technical inquiries to "sp...@berkeley.edu" or "spice-
bu...@berkeley.edu" (for now these addresses are the same), and ordering
or redistribution queries to "ilpso...@eecs.berkeley.edu". If you
find that your email to "spice" or "spice-bugs" doesn't get a response in
a few days, resend your message.
(from Jim Nance <jln...@isscad.com>)
Hello all circuits people. I have uploaded source and binaries for Spice
2g6 to ftp://sunsite.unc.edu/pub/Linux/Incoming/spice2g6.tar.z . As you
are probably aware, spice is a circuit simulator, written at Berkeley.
Version 2g6 was released in 1983. The current Berkeley version is
approximatly Spice 3f2, however, Berkeley does not want this distributed.
Source code for Spice 3e2 did escape from Berkeley and was ported to
Linux (and a lot of other platforms). This code has been removed from
anonymous FTP servers, and is therefore no longer available. Berkeley
does publish the source code for Spice 2g6.
I obtained the source code for Spice from a 386BSD ftp site. The code
compiled cleanly, with only minor changes to the Makefile being required.
I also included an ASCII spice manual which I have found helpful.
(from Martin Maschmann <martin.m...@t-online.de>)
I can also be reached at <martin.m...@vlsi.com>
I have created a SCHEMATIC CAPTURE program running under X11Rsomething
(something >=5) for both linux, sunos and SOLARIS. SPICECAD now has a
home page which has the URL:
<URL:http://home.t-online.de/home/martin.maschmann>
There you will find some links to an ftp site from where you can download
the compiled binaries. Before loading, you can look at some pictures
which show how the graphics interface looks like. If you don't like it,
don't load it.
An english manual is included. Please read the manual! Example schemat-
ics are included, too.
Soure code is not included, because the making of SPICECAD means making
of SPICE3F4 , which is hard-linked to SPICECAD, making a stripped version
of GNUPLOT and making the schematic entry part.
All in all, it is really a mess, especially if you look at the schematics
part which is VERY hard to understand.
Customizing SPICECAD for your own needs means: send me a mail which
explains the problem, and then I can tell you whether I will do it by
myself (because there could be a wide need for this new feature), or
whether you can do it by yourself.
For example, if you want to create an interface for a new simulator (a
PSPICE interface is still missing, an HSPICE interface will be available
in the future), I can send you several example files (the interface for
HSPICE), and you write the interface. Finally , everything can be linked.
Those who want to add some features I cannot write (because my program-
ming skills and time is limited) can obtain the source code on a small
QIC cartridge. What I am thinking of is an EDIF interface. This would be
a very nice feature.
21: Octtools (Current version 5.1)
(From the ANNOUNCE-5.1 that comes with it)
Octtools is a collection of programs and libraries that form an
integrated system for IC design. The system includes tools for PLA and
multiple-level logic synthesis, state assignment, standard-cell, gate-
matrix and macro-cell placement and routing, custom-cell design, circuit,
switch and logic-level simulation, and a variety of utility programs for
manipulating schematic, symbolic, and geometric design data. Most tools
are integrated with the Oct data manager and the VEM user interface.
The software requires UNIX, the window system X11R4 including the Athena
Widget Set. The design manager VOV and a few other tools require the C++
compiler g++.
Octtools-5.1 have been built and tested on the following combinations of
machines and operating systems: DECstation 3100, 5000 running Ultrix 4.1
and 4.2; DEC VAX running Ultrix 4.1 and 4.2; Sun 3 and 4 running OS 4.0
and Sun SparcStation running OS 4.0. The program has been tried on the
following machines, but is not supported: Sequent Symmetry, IBM RS/6000
running AIX 3.1.
To obtain a copy of Octtools 5.1 (8mm, tk50, or 1/4inch cartridge QIC150)
and a printed copy of the documentation) for a $250 distribution charge,
see section on Berkeley ILP.
Questions may be directed to octt...@ic.eecs.berkeley.edu.
22: Ptolemy (Current version 0.5):
(From comp.lsi.cad)
What is Ptolemy:
---------------
Ptolemy provides a highly flexible foundation for the specification,
simulation, and rapid prototyping of systems. It is an object oriented
framework within which diverse models of computation can co-exist and
interact. For example, using Ptolemy a data-flow system can be easily
connected to a hardware simulator which in turn may be connected to a
discrete-event system, etc. Because of this, Ptolemy can be used to
model entire systems.
Ptolemy also has code generation capabilities. From a flow graph
description, Ptolemy can generate C code and DSP assembly code for rapid
prototyping. Ptolemy can also generate Silage and VHDL descriptions for
hardware synthesis.
Ptolemy has been used for a broad range of applications including signal
processing, telecomunications, parallel processing, wireless communica-
tions, network design, radio astronomy, real time systems, and
hardware/software co-design. Ptolemy has also been used as a lab for
signal processing and communications courses. Currently Ptolemy has hun-
dreds of users in over 100 sites, both in industry and academia.
Ptolemy is available for the Sun 4 (sparc), DecStation (MIPS), and HP
(HP-PA) architectures. Installing the system requires 90 Mbytes for
Ptolemy (more if you optionally remake). Ptolemy also requires at least
8 Mbytes of physical memory.
Getting the New Release:
-----------------------
Ptolemy is available via anonymous ftp at:
ftp://ptolemy.eecs.berkeley.edu/pub/README This site contains the entire
Ptolemy distribution, a postscript version of the Ptolemy manual, and
several Ptolemy papers.
For those unfamiliar with anonymous ftp, here's what you need to do:
1. FTP to Internet host "ptolemy.eecs.berkeley.edu" (128.32.240.78)
2. Login as "anonymous"; use your full email address as the password
3. cd pub
4. get the README file and follow its instructions.
Organizations without Internet FTP capability can obtain Ptolemy
without support from ILP:
EECS/ERL Industrial Liaison Program Office
Software Distribution
205 Cory Hall
University of California, Berkeley
Berkeley, CA 94720
(510) 643-6687
email: ilpso...@eecs.berkeley.edu
This includes printed documentation, including installation instructions,
a user's guide, and manual pages. A handling fee (on the order of $250)
will be charged.
23: Lager (Current version 4.0):
(From MUG 18)
The LAGER system is a set of CAD tools for performing parameterized VLSI
design with a slant towards DSP applications (but not limited to DSP
applications). A standard cell library, datapath library, several module
generators and several pad libraries comprise the cell library. These
tools and libraries have originated from UC Berkeley, UCLA, USC, Missis-
sippi State, and ITD. The tool development has been funded by DARPA
under the Rapid Prototyping Contract headed by Bob Brodersen (UC Berke-
ley). LAGER 3.0 was described in MUG 15.
Send email to re...@erc.msstate.edu if you are interested in obtaining
the toolset via FTP. If you cannot get the distribution via ftp then send
one 1/4" 600 ft. tape OR an 8 mm tape (Exabyte compatible) to Bob Reese
by phone at (601)-325-3670 or at one of the following addresses:
(US Mail Address)
P.O. Box 6176
Mississippi State, MS 39762
(FEDEX)
2 Research Boulevard
Starkville, MS 39759
Be sure to include a return FEDEX waybill we can use to ship your tape
back to you. Instead of sending a tape and FEDX waybill, you can also
just send us a check for $75 and we will send you back a tape. Make the
check payable to Mississippi State Univ. The tape will be written on a
high density tape drive (150 Mb). Older low density SUN tape drives (60
Mb) cannot read this format so you need to have access to one of SUN's
newer tape drives.
24: BLIS (Current version 2.0):
(From their announcement posted here)
BLIS (Behavior-to-Logic Interactive Synthesis) is an environment for the
synthesis of digital circuits from high-level descriptions. Version 2.0
supports functional-level synthesis starting from the ELLA hardware
description language. Other languages can easily be supported by inter-
facing a parser to the internal data-flow representation of BLIS.
BLIS is distributed through the Industrial Liason's Program (ILP) Office
of the UCB EECS department. The cost of $250 covers media and distribu-
tion charges. Binaries are provided for SUN4 and DEC MIPS architectures
but BLIS should compile on most other machines supported by the GNU C and
C++ compilers (e.g. HP, vax, etc). ELLA language documentation and simu-
lator are not supplied with the BLIS distribution, but can be obtained
from Computer General.
25: COSMOS and BDD
(From their announcement posted here)
Obtaining and installing COSMOS and BDD.
The COSMOS package generates switch-level simulators for MOS circuits.
The BDD package is a subset of COSMOS providing a set of library routines
for symbolic Boolean manipulation.
To obtain a copy of either COSMOS or BDD via FTP:
1. Create an appropriate subdirectory. For COSMOS, you may want to
create a symbolic link /usr/cosmos to this directory, although this is
not essential.
2. Connect to the subdirectory
3. FTP to ftp://n3.sp.cs.cmu.edu/usr/cosmos/ftp (login anonymous, pass-
word your...@your.host.name)
4. Type:
cd /usr/cosmos/ftp
ls
5. Select which version of the code you want. The files are named
bdd.XXX.YYY.tar.Z and cosmos.XXX.YYY.tar.Z, where XXX.YYY is the ver-
sion number. Generally you should select the highest numbered ver-
sion.
6. 6. Type:
get <FILE> (where <FILE> is the file name of the selected ver-
sion).
get README
quit
7. Follow the instructions in README
8. Send the following information to cos...@cs.cmu.edu
Your name
Your postal address
Your net address
The file retrieved
The date of your retrieval
COSMOS and BDD are made available with the understanding that no part of
it will be redistributed further without permission.
Last updated 18 July 1991 by Derek Beatty.
26: ITEM
(Taken from the item.news file contained in the package:)
The first public release of ITEM, UCSC's logic minimizer using if-then-
else DAGs, was made 2 January 1991. The system is available by anonymous
ftp from ftp://ftp.cse.ucsc.edu/pub/item/item.tar.Z . Also available are
tech reports about the algorithms and data structures (88-28, 88-29, and
90-43).
ITEM can also be found at ftp://ftp.cse.ucsc.edu/pub/item directory.
27: PADS logic/PADS PCB:
While this is a commercial product, they have just recently made avail-
able a shareware version. This version is fully functional and indenti-
cal to their schematic capture and PCB autoplace and route software
except that it is limited to about 50 components. It is available for
IBM PC/PC compatibles directly from PADS, or from anynonmous ftp at
several sites including
<URL:ftp://wuarchive.wustl.edu:/systems/ibmpc/simtel/cad/pads*.zip>.
There is a $50 registration fee if you would like to get future updates
from them.
28: Another PCB Layout Package:
(from Randy Nevin <ran...@microsoft.com>:)
I am distributing a freely-copyable printed circuit board (pcb) autorout-
ing software package called PCBCAD. It runs on PC-compatible computers,
and requires EGA resolution. All source code is included. It contains: a
"ratnest" viewer, autorouters for 1- and 2-layer boards, a board viewer,
hard copy output programs for hp laserjet and postscript printers, and a
DXF converter (autocad). For more background on autorouting, see the
related article published in the September 1989 Dr. Dobb's Journal. In a
nutshell, what you do is create an ascii file which describes your cir-
cuit, feed it to the autorouter, and the circuit will be routed for you.
To receive the programs, send a stamped, self-addressed floppy mailer and
a floppy to:
Randy Nevin,
24135 SE 16th PL
Issaquah, WA 98029, USA
internet: ran...@eskimo.com.
The programs are also available via ftp from
<URL:ftp://oak.oak.and.edu/SimTel/msdos/cad/pcbca110.zip>
<URL:ftp://oak.oak.and.edu/SimTel/msdos/cad/pcbcattl.zip>
29: Magic (Current version 6.5):
This is a polygon based lsi layout editor. It is capable of reading and
writing magic, calma (version 3.0, corresponding to GDS II Release 5.1),
and cif. It is available for anonymous ftp from
ftp://gatekeeper.dec.com/pub/DEC/magic .
Linux versions of magic are available from the standard linux mirror
archives, such as ftp://dorm.rutgers.edu/pub/linux/sources/usr.bin.X11/
[128.6.18.15]:
ftp://dorm.rutgers.edu/pub/linux/sources/usr.bin.X11/magicp3-src.tar.gz
ftp://dorm.rutgers.edu/pub/linux/sources/usr.bin.X11/magic63p3-run.tar.gz
A short summary of the problems people have experienced in using Magic
6.3 under Linux is available:
ftp://magnet.fsu.edu/users/murali/magic6.3-summary
(from Bob Mayo <ma...@pa.dec.com>)
Magic 6.4 is a minor update of magic. It includes the patches from the
6.3 notes series, as well as ports to Digital's Alpha AXP OSF/1 worksta-
tions (courtesy of Stefanos Sidiropoulos) and to Linux on a PC (courtesy
of Harold Levy).
This release includes an updated copy (version 9.2) of Stanford's Irsim
program, as well as scmos tech files (version 8.0.0) from MOSIS.
The easiest way to get magic is via the World Wide Web:
<URL:http://www.research.digital.com/wrl/magic/magic.html>
If you don't have web access, use anonymous FTP from gatekeeper.dec.com
in the directory pub/DEC/magic/6.4. This directory also include the file
irsim-9.2.tar.Z.
(from Tom Burd <bu...@eecs.berkeley.edu>)
If you have layout you can extract, try using irsim-cap, a modified ver-
sion of irsim. switched level simulation gives results close to spice
(within 20% for certain (rail-to-rail) circuits... CMOS, nora, domino,
etc. stuff like CPL, some differential logic styles, etc. gives irsim
problems in its estimation). And it is _much_ faster than SPICE. We
simulate upwards of 100k xsistor chips, but it takes a good CPU and lots
of memory. You can download
such:<URL:ftp://infopad.eecs.berkeley.edu/pub/irsim-cap.tar.Z>
(from comp.lsi.cad)
Newer versions of magic (6.5) and irsim (9.4) are now available through
the magic web page:
<URL:http://www.research.digital.com/wrl/projects/magic/magic.html>
Magic 6.5 is yet another upgrade of magic. It includes all patches posted
since the introduction of 6.4.4 and integrates ports to Solaris and
Free-BSD. Additionally it includes:
New versions of ext2sim and ext2spice.
Cif/Calma enhancements
DRC enhancements
Some new commands.
The latest version of the mosis technology file.
Magic-6.5 is distributed with irsim-9.4. This new version deals with the
sim file format produced by magic-6.5 and it also includes support for
power estimation and writing user modules in C.
The system has been compiled and tested in a number of systems (solaris,
irix, ultrix, linux, sunos, hpux to name a few). However the usuall dis-
claimers about the no-maintenance mode apply: I can't promise that I will
fix any bugs (which I am sure that exist) but I will do my best.
Comments and bug reports/patches should be posted to the magic hypermail
archive: magic-h...@pa.dec.com
30: PSpice:
This is a commercial product, however, they do have a student version
that is available (limited to around 16 transistors).
PC dos version 5.0a:
ftp://oak.oakland.edu/pub/msdos/electric/pspice5a.zip
ftp://oak.oakland.edu/pub/msdos/electric/pspice5b.zip
PC windows3 version 5.1:
ftp://ftp.cica.indiana.edu/pub/pc/win3/util/pspice1.zip
ftp://ftp.cica.indiana.edu/pub/pc/win3/util/pspice2.zip
Mac version 5.1:
ftp://sumex-aim.stanford.edu/info-mac/app/pspice-51.hqx
The PC version is also available at a number of U.S. and non-U.S. sites.
PSPICE 6.0
(from Jonathan Layes <la...@qucis.queensu.ca>)
An evaluation version of PSpice 6.0 for DOS and Windows 3.1 is now avail-
able.
PC dos version 6.0:
<URL:ftp://bode.ee.ualberta.ca/pub/electrical/win3/spice6d1.zip>
<URL:ftp://bode.ee.ualberta.ca/pub/electrical/win3/spice6d2.zip>
PC windows3.1 version 6.0:
<URL:ftp://bode.ee.ualberta.ca/pub/electrical/win3/spice6w1.zip>
<URL:ftp://bode.ee.ualberta.ca/pub/electrical/win3/spice6w2.zip>
<URL:ftp://bode.ee.ualberta.ca/pub/electrical/win3/spice6w3.zip>
PC explode disk:
<URL:ftp://bode.ee.ualberta.ca/pub/electrical/win3/spice6ed.zip>
The incoming directory is not directly readable, but files can still be
read via FTP. These will be moved ot a more appropriate directory, prob-
ably pub/cookbook/softw/msdos.
PSPICE 6.2
(from Richard Nekus<ao...@freenet.carleton.ca>)
Evaluation versions of the circuit simulator and schematic editor are
available with the following limitations:
These device limitations apply:
- 64 analog nodes
- or, 10 transistors (any combinationn of B, M, Q, or J devices)
- or, 2 opamps
- or, 10 transmission lines (up to 4 coupled)
- or, 65 digital primitive devices
- or, logic output transitions limited to 10000
- or, logic expression primitives limited to 36 I/O pins
- or, any combination of the above (which will result in a
lower allowable number of each)
Additional limitations include:
- device characterization for diodes only
- stimulus generation for sine waves only
- libraries with approximately 22 analog and 140 digital parts
- synthesis of up to 3rd order filters
Schematic Editor limitations include: