Announce:GPLed 6502 IP core

[Naohiko Shimizu]

Hi, I made 6502 IP core to use in my class,
and I would like to release this core with GPL license.

See and enjoy with it.

http://shimizu-lab.dt.u-tokai.ac.jp/pgm/m65/index.html

Naohiko Shimizu

------------------------------------------------------
m65 - 6502 instruction compatible micro processor

Copyright (C) 2002-
Naohiko Shimizu <nshi...@keyaki.cc.u-tokai.ac.jp>

m65 is provided as a synthesizable soft IP core under GPL.
The description language is SFL and can be synthesized for
any FPGA such as ALTERA or Xilinx. When synthesized for
ALTERA FLEX10K series, it will fit within 600 logic cells.
I successfully complied for a FLEX EPF10K10LC84-3.
When compiled for a gate array, it will use under 4000 gates.

If you want to try the core, you sould download PARTHENON tools
from NTT WEB page. (It is free for non-commercial use)

http://www.kecl.ntt.co.jp/parthenon/

Because this IP core is covered with GPL2, if you make
any products with this IP core, you should provide your
source code and/or schematics for the users, freely.
See the COPYING file for more details.

Anyone who wants other license, or VHDL version,
please contact me:

Associate Prof. Naohiko Shimizu
Dept. Communications Engineering,
School of Information Technology and Electronics,
Tokai University
1117 Kitakaname, Hiratsuka-city, 259-1292 Japan
Emal: nshi...@keyaki.cc.u-tokai.ac.jp
URL: http://shimizu-lab.dt.u-tokai.ac.jp/
TEL: +81-463-58-1211(ext.4084)
FAX: +81-463-58-8320

The documents:

README.TXT: This file
COPYING : License document (GPL2)

The logic is consisted with:

inc16.sfl : 16bit PC incrementer
alu65.sfl : ALU logic
data65.sfl: Datapath logic of MPU
m65.sfl : Control logic of MPU
m6502.sfl : 6502 compatible soft IP core
m6505.sfl : 6505 compatible soft IP core
m6502chip.sfl : Bidirectional databus version

Simulation environment is provided with Lee Davison's EhBASIC
After you installed PARTHENON, you can run the simulator "seconds"
and input "basic.run" as a command. After 45000 cycles simulation,
the script will dump the Lee's BASIC output strings in hex format.

basic.sfl : Simulation main logic
basic.run : Simulation main script
instring.dat: BASIC command inputs script
o64tohex : o64 to hex conversion script
od2hex.awk : od dump to hex file conversion

*)monitor.rom : BIOS, interrupt vectors based on Lee's monitor
*)basic.rom : Lee Davison's EhBASIC ROM image

*) These two files are not covered with GPL,
see the license on the Lee's page:

http://members.lycos.co.uk/leeedavison/index.html

And for his EhBASIC,

http://members.lycos.co.uk/leeedavison/6502/ehbasic/index.html

Synthesized demo code:
The demo m6505's address space is restricted for 10bit,
though it has 12bit address lines. (The SFL source code
have 16/12 bit addressing capability.)

m6505/m6505.tdf : Converted TDF from the synthesized EDIF file
m6505/m6505.sym : Symbol file for m6505
m6505/m6505chip.gdf : Demonstration for make a real chip.

This code is free software IP; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.

[Micah Dowty]

This is the first time I've heard of the SFL language. It looks
interesting, but I managed to find only sparse documentation on it. Is
there any good documentation? More important, what license is it released
under and where can I get the source?