Celeron vs. PPro vs. PII
Pearce
cetra?
Thanks,
Pearce
cqu...@iafrica.com
<smit...@ccmail.orst.edu> wrote:
>What is the difference between these different chips?
Difference is in form factor, and the way the L2 cache is implimented
(or not). AFAIK the cores are otherwise close to identical as far as
the microcode goes, except for the addition of MMX instructions.
Pentium Pro
.35 fabrication
Supports up to 4-way SMP
Requires Socket 8 motherboards
- usual single-CPU chipset is 440FX:
- no SDRAM support
- no UIDE support
First P6 generation core
Microcode purely optimised for 32-bit code
- slow++ on 16-bit code
L2 cache is 256k, on second wafer
- CPU and L2 wafers bound within same ceramic "chip" package
- L2 runs at full core speed, 4096M addressability range
- expensive to make++ due to yeild losses of the wafer binding
Was produced as 150, 180, 200MHz based on 66MHz RAM speed
Klamuth (the original Pentium II)
.35 fabrication
Supports up to 2-way SMP
Requires Slot One motherboards
- usual single-CPU chipsets are 440FX, 'LX, 'EX
- 440LX, 'EX have SDRAM support
- 440LX, 'EX have UIDE support
- 440LX, 'EX have AGP support
Second P6 generation core
Microcode purely optimised for 32-bit code, but...
- ... may be less slow++ on 16-bit code (?)
- adds additional MMX instructions
L2 cache is 512k, on second wafer
- CPU and L2 built on a board, sealed in "cartridge" package
- cartridge bulk -> ATX case form factor re-invention
- L2 runs at half core speed, 512M addressability range
- cheaper to make in this cartridge format
Was produced as 233, 266, 300MHz based on 66MHz RAM speed
Deschutes (the current Pentium II)
.25 fabrication
Supports up to 2-way SMP
Requires Slot One motherboards
- usual single-CPU chipsets are 440BX, 'LX, 'EX
- 440BX adds support for 100MHz RAM speed
Second P6 generation core, shrunk to .25 micron
Same microcode, but L2 cache management slightly different
- cheaper to make, but marginally slower
- 4096M addressability range
L2 cache is 512k, on second wafer, same as Klamuth
Runs lower voltage, cooler, takes less current than Klamuth
Initially produced as 333MHz based on 66MHz RAM speed
Now produced as 350, 400 and 450MHz based on 100MHz
Covington (the original Celeron)
.25 fabrication
No SMP support
Requires Slot One motherboards
- usual chipsets is 440EX, but can 'BX or 'LX
- 440EX is watered-down 440LX
- 440EX fewer SDRAM, PCI, ISA slots
- 440EX AGP is mode 1x only, no 2x (may have changed)
- 440EX is 66MHz only
- 440EX RAM addressability limited to 256M
Covington is a "floor sweepings" cost-cutter; same wafer as Deschutes
- nice, because this is usually 100MHz-capable
- hence overclocker's delight
- not nice, because this wafer has no L2 cache built into it
L2 cache is absent from the processor board
Produced as 266, 300MHz based on 66MHz RAM speed
Overclocked by running on 'BX at 100MHz to 400, 450MHz
Mendocino (the current Celeron)
.25 fabrication
No SMP support
Initially for Slot One motherboards
- usual chipsets is 440EX, but can 'BX or 'LX
Will be force-marched to Socket 370
- enforces Intel's Celeron/PII market segmentation
- breaks Celeron-to-PII upgrade path
- intention is to chain it to reduced-feature chipsets, but.
- usual chipset is 440ZX, "440ZX66"
- said to be derived from 'BX as 'EX was from 'LX
- 440ZX is 66MHz-only, though "ZX66" suggests may change
- 440ZX fewer RAM and PCI slots, etc. etc.
- 440ZX RAM addressability limited to 256M
Mendocino uses .25 shrink to build 128k L2 cache into wafer
- L2 runs at full core speed, 4096M addressability range
- cheaper to make than dual-wafer PPro approach
- Socket 370 cheaper to make than Slot One cartridge rigmarole
Produced as 300, 333MHz based on 66MHz RAM speed
- 300MHz called "300A" to distinguish it from Covington
- 366MHz imminent
Overclocked by running on 'BX at 100MHz to 400, 450MHz
Future 100MHz-based expected, but ? will be Socket 370 only
>Performance wise et cetra?
Generally, at the same clock speed, PPro outperforms PII in 32-bit
code environments, may be slower on 16-bit code. Intel "solved" that
by knocking the PII-200 on the head before it was released. The real
value of PII/Celeron over PPro lie in the benefits of post-440FX
motherboard chipsets, which are locked out of Socket 8.
Deschutes runs about same speed per clock as Klamuth; the cheaper L2
organisation drops speed slightly, so that PII-333 (Deschutes) runs
close to PII-300 (Klamuth). However, most Deschutes run off 100MHz
and this gives them the edge, aside from raw clock speed boosts that
the cooler running allows. If the 440BX hadn't been delayed, I doubt
if we would have seen a PII-333 Deschutes.
Celeron based on Covington suck, performance wise, and the fact that
this product line has gone from release to death in under a year
speaks for itself. However, 3D games are often less sensitive to the
lack of L2 cache, and as these Deschutes wafers tend to be quite
stable at 100MHz base speed, it's popular as a cheap gaming CPU.
Mendocino is harder to evaluate; if the data fits in the smaller L2
cache, it will be faster than PII, if it is too far away but still
fits in 512k L2 cache, PII will be faster. The expectation, and usual
reported experience, is that PII will be faster than Mendocino for a
given clock speed. But L2 within the wafer (made possible by the
shrink to .25) is clearly the way to go, and I'd expect to see those
huge cartridges retreat to the high-cost high-end.
Buyer's Advice
At the moment, there's a golden opportunity to defer the purchase of
processor performance, while minimizing the disruption of adding this
later. You can build a system around the PII-450 (440BX chipset
motherboard, PC100 spec SDRAM) yet leave out this currently overpriced
chip, using a Celeron (preferably Mendocino core) in the meantime.
The cost of this placeholder CPU will be recovered by the drop in
PII-450 cost (prolly within a year) and you might try it at 100MHz in
the meantine if your data isn't important (i.e. second or games PC).
But Intel has established a monopoly position by preventing other CPU
makers from competing on Slot One or Socket 370. And you can expect
them to press this advantage as IBM did in their days of domination,
by rigidly enforcing market segmantation and functional pricing. The
Slot One Celeron to PII upgrade path will not last forever.
If they succeed in heading off other motherboard chipset makers, lock
down ATX, and bind different chipsets to different ATX, then they can
even prevent other motherboard manufacturers from building (say) dual
Socket 370 / Slot One mobos based on the 440BX, or de-lamered Socket
370 motherboards based on the 440BX rather than 440ZX chipsets.
Intel's risk is that the public will come to associate the Intel brand
name monopoly manipulation rather than quality, and that the PC
platform will lose much of the "open" advantage it currently enjoys
over the Mac. But if the DoJ and the courts have trouble following
tech issues such as "what is a browser", they are even less likely to
be effective in curbing Intel should this be required in near future.
David T. Wang
: But Intel has established a monopoly position by preventing other CPU
: makers from competing on Slot One or Socket 370. And you can expect
: them to press this advantage as IBM did in their days of domination,
: by rigidly enforcing market segmantation and functional pricing. The
: Slot One Celeron to PII upgrade path will not last forever.
: If they succeed in heading off other motherboard chipset makers, lock
: down ATX, and bind different chipsets to different ATX, then they can
: even prevent other motherboard manufacturers from building (say) dual
: Socket 370 / Slot One mobos based on the 440BX, or de-lamered Socket
: 370 motherboards based on the 440BX rather than 440ZX chipsets.
: Intel's risk is that the public will come to associate the Intel brand
: name monopoly manipulation rather than quality, and that the PC
: platform will lose much of the "open" advantage it currently enjoys
: over the Mac. But if the DoJ and the courts have trouble following
: tech issues such as "what is a browser", they are even less likely to
: be effective in curbing Intel should this be required in near future.
Two corrections.
1. Minor point. 150 MHz PPro was fabricated on 0.6um BiCMOS process.
166 MHz and above are 0.35um BiCMOS. Klamath is 0.28/0.35 CMOS.
2. Intel has already licensed Slot 1 to Via Technologies. Supposedly
there are negotiations with other chipsetmakers, though I'm not 100%
sure. I was in Taiwan about 2 months ago, and I saw no less than 3
non-Intel slot 1 chipsets.
--
dave...@kagututi.kecl.ntt.co.jp.I.like.green.eggs.and.ham,not.spam
All statements are personal opinions
Not speaking for NTT or University of Maryland
Kyoto, Japan.
cqu...@iafrica.com
dave...@cslab.kecl.ntt.co.jp.DELETE.delete.DELETE@Glue.umd.edu
>cqu...@iafrica.com wrote:
>Two corrections.
>1. Minor point. 150 MHz PPro was fabricated on 0.6um BiCMOS process.
Wow - that's heavy metal! Must have dated from the P60/66 days... was
it also 5 volts?
>166 MHz and above are 0.35um BiCMOS. Klamath is 0.28/0.35 CMOS.
How do you mean ".28/.35"; are parts fabbed at diff sizes, or is that
referring to the latter-day/born-again Klamuth-speed PIIs? AFAIK the
latter were Deschutes cores; I've seen a couple, and they were 2.0v,
and also reported to have 4G RAM cache range.
>2. Intel has already licensed Slot 1 to Via Technologies. Supposedly
>there are negotiations with other chipsetmakers, though I'm not 100%
>sure. I was in Taiwan about 2 months ago, and I saw no less than 3
>non-Intel slot 1 chipsets.
We do see them here, but until recently they were under a cloud in the
US. Slot One isn't Socket 370, though, and there still ways to
proprietise things if they wanted to, in the grand old IBM tradition.
David T. Wang
: On 14 Dec 1998 03:44:58 GMT,
: dave...@cslab.kecl.ntt.co.jp.DELETE.delete.DELETE@Glue.umd.edu
: >cqu...@iafrica.com wrote:
: >Two corrections.
: >1. Minor point. 150 MHz PPro was fabricated on 0.6um BiCMOS process.
: Wow - that's heavy metal! Must have dated from the P60/66 days... was
: it also 5 volts?
150 MHz PPro was released at the introduction of the Pentium Pro itself.
November 1995. It uses 3.1V. The Pentium 60 was manufactured on 0.8um
and was released about 2 1/2 years prior around March of 1993.
http://developer.intel.com/design/pro/
: >166 MHz and above are 0.35um BiCMOS. Klamath is 0.28/0.35 CMOS.
: How do you mean ".28/.35"; are parts fabbed at diff sizes, or is that
: referring to the latter-day/born-again Klamuth-speed PIIs? AFAIK the
: latter were Deschutes cores; I've seen a couple, and they were 2.0v,
: and also reported to have 4G RAM cache range.
0.28/0.35 because the process is slightly different than the 0.35um
BiCMOS process. The Bipolar drivers were taken out, and replaced with
large CMOS only drivers. Intel still refers to it as "0.35um", although
MDR refers to it as "0.28um"
http://www.chipanalyst.com/q/@12120565kpmzmw/mpr/articles/v11/110201.pdf
page 3. Under "Circuit designers make impact" Title.
In any case, it's a different process, and I was trying to be diplomatic
by referring to this process as a "0.28/0.35" process, different from
PPro's 0.35 BiCMOS process.
Finally, Why do you insist on spelling Klamath as Klamuth?
: >2. Intel has already licensed Slot 1 to Via Technologies. Supposedly
: >there are negotiations with other chipsetmakers, though I'm not 100%
: >sure. I was in Taiwan about 2 months ago, and I saw no less than 3
: >non-Intel slot 1 chipsets.
: We do see them here, but until recently they were under a cloud in the
: US. Slot One isn't Socket 370, though, and there still ways to
: proprietise things if they wanted to, in the grand old IBM tradition.
I'm not sure where you come up with all this stuff. Intel's spokesperson's
comments appears to contradict what you claim here. In any case, P6 bus
is essentially the same bus as the Slot 1 bus, and the Socket 370 is the
same as well. If you want to argue that the change in termination
impendence between PPro and P II would it is a "different" bus. Then
go ahead.
http://www.news.com/News/Item/0,4,29349,00.html
....
Intel's Mulloy agreed that Intel and Via are "competitors in the chipset
space. But at the same time, both sides felt they found a solution here
that we can both live with."
....
The new twist on the socket design is called simply "370-pin socket,"
Mulloy said; Hays referred to it as Socket 370. Whatever it's called,
though, a chipset for Slot 1 will also work for the 370-pin socket
design, Mulloy said.
cqu...@iafrica.com
dave...@cslab.kecl.ntt.co.jp.DELETE.delete.DELETE@Glue.umd.edu (David
>cqu...@iafrica.com wrote:
>150 MHz PPro was released at the introduction of the Pentium Pro itself.
>November 1995. It uses 3.1V. The Pentium 60 was manufactured on 0.8um
>and was released about 2 1/2 years prior around March of 1993.
Yes, one forgets how long ago the old Pentium60/66 came out.
They were largely ignored here, esp after the DX4 came out; in fact I
only started building Pentium-75's some time after the 90/75/100 had
all been out.
>Finally, Why do you insist on spelling Klamath as Klamuth?
Oops. One of my most common incoming pricelists has it that way, and
I kinda got into the habit :->
>: >2. Intel has already licensed Slot 1 to Via Technologies.
>: >I was in Taiwan about 2 months ago, and I saw no less than 3
>: >non-Intel slot 1 chipsets.
>: We do see them here, but until recently they were under a cloud in the
>: US. Slot One isn't Socket 370, though, and there still ways to
>: proprietise things if they wanted to, in the grand old IBM tradition.
>I'm not sure where you come up with all this stuff. Intel's spokesperson's
>comments appears to contradict what you claim here.
For "until recently", read "before the Intel/VIA agreement".
>In any case, P6 bus is essentially the same bus as the Slot 1 bus,
>and the Socket 370 is the same as well. If you want to argue that
>the change in termination impendence between PPro and P II
>would it is a "different" bus. Then go ahead.
No, I was thinking about aspects other than the bus; the socket
itself, or other features that can be introduced, possibly between an
revised ATX power supply and motherboard. Speculation, really.
>Intel's Mulloy agreed that Intel and Via are "competitors in the chipset
>space. But at the same time, both sides felt they found a solution here
>that we can both live with."
>The new twist on the socket design is called simply "370-pin socket,"
>Mulloy said; Hays referred to it as Socket 370. Whatever it's called,
>though, a chipset for Slot 1 will also work for the 370-pin socket
>design, Mulloy said.
Certainly sounds good so far!
David T. Wang
: dave...@cslab.kecl.ntt.co.jp.DELETE.delete.DELETE@Glue.umd.edu (David
: >In any case, P6 bus is essentially the same bus as the Slot 1 bus,
: >and the Socket 370 is the same as well. If you want to argue that
: >the change in termination impendence between PPro and P II
: >would it is a "different" bus. Then go ahead.
: No, I was thinking about aspects other than the bus; the socket
: itself, or other features that can be introduced, possibly between an
: revised ATX power supply and motherboard. Speculation, really.
Such are mechanical specifications that doesn't change the fundamentals
of a bus protocol. To come up with a new bus that VIA can't clone
under this existing licensing, Intel would probably have to design
another processor from the ground up that uses yet another completely
new bus protocal. Merced perhaps? I have no idea what bus protocol
that beast uses. Things such as changing sockets doesn't even require
designing a new chipset, much less invalidation a license. The 440FX
chipset was used for both socket 8 and slot 1.
cqu...@iafrica.com
dave...@cslab.kecl.ntt.co.jp.DELETE.delete.DELETE@Glue.umd.edu (David
>cqu...@iafrica.com wrote:
>: dave...@cslab.kecl.ntt.co.jp.DELETE.delete.DELETE@Glue.umd.edu (David
>: >In any case, P6 bus is essentially the same bus as the Slot 1 bus,
>: >and the Socket 370 is the same as well.
>:I was thinking about aspects other than the bus; the socket
>: itself, or other features that can be introduced, possibly between an
>: revised ATX power supply and motherboard.
>Such are mechanical specifications that doesn't change the fundamentals
>of a bus protocol.
Yes, as long as voltage regulation is independent of the chipset,
there's no hard link to ATX etc.
>To come up with a new bus that VIA can't clone
>under this existing licensing, Intel would probably have to design
>another processor from the ground up that uses yet another completely
>new bus protocal. Merced perhaps?
It's been interesting to see the periodic waxing and waning of PR-push
on Merced - at one "quiet" time it looked as if projected x86
successors were closing the performance level to the point that Merced
would be passed over for it's successor.
With this in mind, I expect there will be other new tech to be debuted
with Merced. After all, why not? It's a chance to start from fresh,
plus initial high prices increase expectations, but can cover costs of
new tech. K7 on Digital's platform will keep the heat on.