New Risc5x cpu core on Opencores

[Mike Johnson]

Just released on opencores :

RISC5X

A small RISC CPU (written in VHDL) that is compatible with the 12 bit opcode
PIC family. Single cycle operation normally, two cycles when the program
counter is modified. Clock speeds of over 40Mhz are possible when using the
Xilinx Virtex optimisations.

The core has a single pipeline stage and is run from a single clock, so
(ignoring program counter changes) a 40Mhz clock will give 40 MIPS
processing speed. Any instruction which modifies the program counter, for
example a branch or skip, will result in a pipeline stall and this will only
cost one additional clock cycle.

The CPU architecture chosen is not particularly FPGA friendly, for example
multiplexers are generally quite expensive. The maximum combinatorial path
delay is also long, so to ease the place and route tool's job the core is
written at a low level. It instantiates a number of library macros, for
example a 4:1 mux. Two versions of these are given, one is generic VHDL and
the second is optimised for Xilinx Virtex series (including sparten2's etc).
A constraints file locates the datapath macros within the device and ensures
an easy fit and high clock speed.

http://www.opencores.org/projects/risc5x/

mikej<NO SPAM>@opencores.org

[S. Ramirez]

"Mike Johnson opencores.org>" <mikej<NOSPAM> wrote in message
news:10120762...@eurus.uk.clara.net...

> Just released on opencores :
>
> RISC5X
>
> A small RISC CPU (written in VHDL) that is compatible with the 12 bit
opcode
> PIC family. Single cycle operation normally, two cycles when the program
> counter is modified. Clock speeds of over 40Mhz are possible when using
the
> Xilinx Virtex optimisations.

Wow, thank you very much, Mike!
Simon Ramirez, Consultant
Synchronous Design, Inc.
Oviedo, FL USA