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Why no high end PPC?

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Martin H. Kristiansen

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Jul 19, 1999, 3:00:00 AM7/19/99
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I've been wondering why IBM/Moto hasn't made a PPC750 Hotrod. Current
implementations are only 40mm^2 and burns <6W. It seems that emphasis is
on low power, but why??? When dissipating power up to 40W is trivial
these days.

I mean, how much higher could the clockrate go with 4x the power budget?
They supposedly used copper now for interconnect and thus current
density should be less of a worry, right?

I saw that IBM has 2MB cache chips in their G6 processors. These have a
die size of 16.5mm (squared? =260mm^2?). Bolt on of these on a PPC750
core, skip the backside bus and use the IO pins to build a 128bit
systeminterface. Oh yeah, and throw in a fully pipelined double
precision FPU (like the one in the 604e).

Is this possible? I can't see why not, but then again I do software !8)

I would expect >600MHz operation frequency, >30 SpecInt and 40-50
SpecFP.

Cheers
Martin

Mark Johnson

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Jul 19, 1999, 3:00:00 AM7/19/99
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Whip out your trusty Internet search engine and look
for "Exponential Technology" --- a company that built
an extremely high-end Power PC. They agreed with
you, dissipating lots of power is one way to boost
the performance.

Dave Schuman

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Jul 19, 1999, 3:00:00 AM7/19/99
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Mark Johnson wrote:

> Whip out your trusty Internet search engine and look
> for "Exponential Technology" --- a company that built
> an extremely high-end Power PC. They agreed with
> you, dissipating lots of power is one way to boost
> the performance.
>
> "Martin H. Kristiansen" wrote:
> >

I found the web page at http://www.exp.com/ , but it doesn't look like much
has been going on for a while. the last press release was Feb. 1997. Are they
still at 533Mhz or much faster now?


John McCalpin

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Jul 19, 1999, 3:00:00 AM7/19/99
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In article <3793116A...@webhouse.dk>,

Martin H. Kristiansen <m...@webhouse.dk> wrote:
>I've been wondering why IBM/Moto hasn't made a PPC750 Hotrod. Current
>implementations are only 40mm^2 and burns <6W. It seems that emphasis is
>on low power, but why??? When dissipating power up to 40W is trivial
>these days.

This is just speculation on my part, but I can think of three issues....

(1) It is not automatically true that you can trade more power for
higher clock rates. The devil is in the details.

(2) Running at 5W is very nice when your major customer (Apple) wants
to put the same processor family in laptops and desktops.

(3) Low power is a key to success in the embedded systems market,
which is *much* larger than the PC market.

The current PPC750's are adequate for their intended use. To provide
significant improvement in realized performance would require fundamental
changes to the memory and cache architectures. So far, Motorola's
disclosures of its future plans do not provide much information to
fuel speculation in these areas....

--
--
John D. McCalpin, Ph.D. Principal Scientist
System Architecture Group http://reality.sgi.com/mccalpin/
SGI mcca...@sgi.com 650-933-7407

David Lau

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Jul 19, 1999, 3:00:00 AM7/19/99
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In article <379334CE...@lucent.com>,

Dave Schuman <dssc...@lucent.com> wrote:
>
> I found the web page at http://www.exp.com/ , but it doesn't look
like much
> has been going on for a while. the last press release was Feb. 1997.
Are they
> still at 533Mhz or much faster now?
>
>

They have been out of business for over a year. From what I remember,
they closed their Silicon Vally offices first, keeping an Austin,TX
site open to build an x86 part. The Austin office closed a few months
later.

Exponential was last among many failed attempts to bring a non-CMOS
microprocessor to market.

If you're looking for fast PPC implementations, you can also check
out a company named MicroMagic. Does anybody know how far along they
got with their implementation?

dl

--
Usenet: Where the truely clueless can learn from
the profoundly ignorant.
Hey Buddy, it's only my opinion!


Sent via Deja.com http://www.deja.com/
Share what you know. Learn what you don't.

Paul DeMone

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Jul 19, 1999, 3:00:00 AM7/19/99
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Dave Schuman wrote:
>
> Mark Johnson wrote:
>
> > Whip out your trusty Internet search engine and look
> > for "Exponential Technology" --- a company that built
> > an extremely high-end Power PC. They agreed with
> > you, dissipating lots of power is one way to boost
> > the performance.
> >

> > "Martin H. Kristiansen" wrote:
> > >
>
> I found the web page at http://www.exp.com/ , but it doesn't look like much
> has been going on for a while. the last press release was Feb. 1997. Are they
> still at 533Mhz or much faster now?

Sorry but like the Monty Python parrot, Exponential is quite dead.
For all you venture capitalists out there remember the following
score: CMOS 4 Bipolar 0
(RIP: BIT SPARC, BIT MIPS R6000, MicroUnity CPU, Exponential PPC)

However, one of their patents was for a CPU design that executed
both RISC and CISC instructions. When Exponential went mams up
the patent portfolio was sold off via secret bid. It turned out
S3 bought the patents. Apparently Intel is quite concerned that the
RISC/CISC CPU patent might encompass some of the x86 compatibility
features of IA-64 and S3 has been Intel best pal ever since :)

--
Paul W. DeMone The 801 experiment SPARCed an ARMs race of EPIC
Kanata, Ontario proportions to put more PRECISION and POWER into
dem...@mosaid.com architectures with MIPSed results but ALPHA's well
pde...@igs.net that ends well.

Sean Burke

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Jul 19, 1999, 3:00:00 AM7/19/99
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David Lau wrote:
>
> In article <3793116A...@webhouse.dk>,
> "Martin H. Kristiansen" <m...@webhouse.dk> wrote:
> > I've been wondering why IBM/Moto hasn't made a PPC750 Hotrod. Current
> > implementations are only 40mm^2 and burns <6W. It seems that emphasis
> is
> > on low power, but why??? When dissipating power up to 40W is trivial
> > these days.
> >
>
> It's probably a business decision.
>
> Currently, there's only two customers of desktop PPC parts (Apple and
> IBM). IBM builds the Power chips which they feel are appropriate for
> their workstations. So that only leaves Apple as a customer for a
> commercially-available very high Mhz, high-power consumption device.

Still, IBM has described their upcoming SOI PPC750 as being
"30%" faster than current implementations. Since current 750s
run at 450MHz, that would mean 600MHz parts will be out by
October. Now if Apple had ever done a Spec run on their PPC750s,
we'd have a basis for speculation! :^)

Also, has Moto released any details on this 4-way G4? I assume
a shared on-chip L2. I assume it would be a win to share the L1
as well, since this eliminates cache-coherency hardware.

-SEan


Bruce Hoult

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Jul 20, 1999, 3:00:00 AM7/20/99
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In article <37932EE8...@mjohnson.com>, Mark Johnson
<ma...@mjohnson.com> wrote:

> Whip out your trusty Internet search engine and look
> for "Exponential Technology" --- a company that built
> an extremely high-end Power PC. They agreed with
> you, dissipating lots of power is one way to boost
> the performance.

Nah. They were planning to ship at 500 MHz, but with a PPC601-like
machine with not much cache. Their chip would have been good if it hadn't
been for the 350 MHz 604e (which would thrash the Exponential 701 on
CPU-intensive code) and the PPC750 (which would thrash the 701 on anything
that used much memory).

There was a time that it would have been a great chip, but by the time it
looked like coming out it had been passed by.

-- Bruce

David Lau

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Jul 20, 1999, 3:00:00 AM7/20/99
to
In article <3793116A...@webhouse.dk>,
"Martin H. Kristiansen" <m...@webhouse.dk> wrote:
> I've been wondering why IBM/Moto hasn't made a PPC750 Hotrod. Current
> implementations are only 40mm^2 and burns <6W. It seems that emphasis
is
> on low power, but why??? When dissipating power up to 40W is trivial
> these days.
>

It's probably a business decision.

Currently, there's only two customers of desktop PPC parts (Apple and
IBM). IBM builds the Power chips which they feel are appropriate for
their workstations. So that only leaves Apple as a customer for a
commercially-available very high Mhz, high-power consumption device.

It doesn't make sense to spend so much time/effort/money on a
device whose existence depends solely on the whims of one customer.

By building mid-range parts like the 750/G3/G4 parts, the customer
base widens to high-end embedded customers (read non-PC customers).


When the Somerset design center got started, PPC had 3 design tracks.
The high-end one (620/630) produced chips which weren't much faster
then the mid-range (604). When they noticed that Apple did ok with
the mid-range parts, they cancelled the high-end track.

IBM is currently in the race to build the first Ghz processor with
a full-custom circuit design implementation. I don't know if this will
be available outside an IBM workstation/server.

David DiGiacomo

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Jul 20, 1999, 3:00:00 AM7/20/99
to
In article <3793D5D2...@igs.net>, Paul DeMone <pde...@igs.net> wrote:
> Sorry but like the Monty Python parrot, Exponential is quite dead.
> For all you venture capitalists out there remember the following
> score: CMOS 4 Bipolar 0
> (RIP: BIT SPARC, BIT MIPS R6000, MicroUnity CPU, Exponential PPC)

I don't like this scorecard because it mixes up ECL and ECL/CMOS with
"classic BiCMOS" (CMOS + NPN pullups). Of course, Exponential was happy to
do exactly that -- Mark Johnson must have been amused that they tried to
give their design legitimacy by calling it BiCMOS.

How about this:

ECL: 0/4 or 0/5
BIT MIPS R6000 - mostly a failure (late, problematic)
BIT SPARC (Sunburn/Suntan) - failure (never shipped)
ECL SPARC project #2 - failure (never shipped)
FTL - what was this? not a success
Exponential PPC (ECL/CMOS) - failure

BiCMOS: 1.5/3
Sun/TI Viking - late, slow, ultimately shipped in volume
Pentium - success
MicroUnity - failure

I'm sure there are more BiCMOS successes & failures that could be added.

Zalman Stern

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Jul 20, 1999, 3:00:00 AM7/20/99
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Paul DeMone <pde...@igs.net> wrote:
: (RIP: BIT SPARC, BIT MIPS R6000, MicroUnity CPU, Exponential PPC)

Hey! The R6000 shipped for many 10s of millions of dollars in revenue at a
key time in MIPS' history. None of those other parts shipped a single
machine to a paying customer if I'm not mistaken.

That said, I doubt anyone involved would want to repeat the R6000 "maybe
we'll get some working parts this month" experience, but given the choice
between having it and not having it, I think MIPS was happier having it.

And while you're dissing bipolar, don't forget to mentium the original
Pentium.

(Mark Johnson has been posting taunts to the bipolar afficiandos for the
better part of a decade now. If I grok the subtext correctly, a proper
reading is "Yeah sure you can try just throwing power at the problem to get
performance. But if that's your only strategy, you'd probably be better
off taking the venture capital to Vegas.")

-Z-

Zalman Stern

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Jul 20, 1999, 3:00:00 AM7/20/99
to
David DiGiacomo <da...@slack.com> wrote:
: FTL - what was this? not a success

I'm pretty sure this is the company that MIPS bought which became the
R6000. So it is in effect the same thing.

-Z-

Zalman Stern

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Jul 20, 1999, 3:00:00 AM7/20/99
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Zalman Stern <zal...@netcom15.netcom.com> wrote:
: And while you're dissing bipolar, don't forget to mentium the original
^^^^^^^
: Pentium.

Hmmm... So was it the scone or the latte they spiked this morning?

Perhaps more relevant to the thread, the only thing that makes more sense
than building single chip multiprocessors to go in a Macintosh is to fab
them in BiCMOS or perhaps even GaAs.

-Z-

Sean Burke

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Jul 20, 1999, 3:00:00 AM7/20/99
to


You might be underestimating the attraction. (You did intend
sarcasm, right?) Apple would get a 4way SMP capability without
(presumably) needing to build a specialized chipset or motherboard.

Apple's customers often run applications like Photoshop, which will
benefit from SMP. (But you knew that! :^) Also, many games of the
3D-interactive-blast-em sort are threaded, and will benefit from SMP.
A low-end SMP system could be attractive to both types of customer.

And of course, a low-power SMP chip would be attractive in all sorts
of embedded applications where PowerPC is currently popular.

-SEan


Paul DeMone

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Jul 20, 1999, 3:00:00 AM7/20/99
to

Zalman Stern wrote:
>
> Paul DeMone <pde...@igs.net> wrote:
> : (RIP: BIT SPARC, BIT MIPS R6000, MicroUnity CPU, Exponential PPC)
>
> Hey! The R6000 shipped for many 10s of millions of dollars in revenue at a
> key time in MIPS' history. None of those other parts shipped a single
> machine to a paying customer if I'm not mistaken.
>
> That said, I doubt anyone involved would want to repeat the R6000 "maybe
> we'll get some working parts this month" experience, but given the choice
> between having it and not having it, I think MIPS was happier having it.

The R6000 and BIT came darn closing to putting MIPS into
chapter 11 IIRC. One question: how does the R6000 stack
up to the R4000?

>
> And while you're dissing bipolar, don't forget to mentium the original

> Pentium.

The argument Intel brought forward to justify the tiny
bipolar content of the Pentium and Pentium Pro - namely
it made high fanout buffers a bit smaller and faster
was rather weak. I doubt the tiny incremental circuit
design benefit was worth the extra masking steps and
associate yield loss. Virtually everyone else designing
CPUs with 0.8, 0.5 and 0.35 um feature sizes (including
DEC semi who had extensive bipolar experience and were
designing for 2-3 times higher clock rates) saw fit
to using only pure CMOS.

Intel returned to the pure CMOS fold with the 0.25 um
Tillamook Pentium and the 0.35 um (0.28 um FET) kludge
process for the Klamath Pentium II.

>
> (Mark Johnson has been posting taunts to the bipolar afficiandos for the
> better part of a decade now. If I grok the subtext correctly, a proper
> reading is "Yeah sure you can try just throwing power at the problem to get
> performance. But if that's your only strategy, you'd probably be better
> off taking the venture capital to Vegas.")

Well everyone is throwing power at it these days. The datasheet for
the 0.35 um 21264 specs max power at 109 Watts at 600 MHz !!!
The real question is how efficiently can you convert watts into
computations.

The big advantage of CMOS is that it scales down to supply voltages
under 1 Volt. How far depends on your tolerance for subthreshold
leakage from transistor Vt's below 300 mV. A 1V CPU burning 100 W
of dynamic power is hardly going to notice 10 Amps of DC leakage
(although a CPU power down mode would be a relative concept ;-)
With CMOS there is a lot of flexibility to trade-off Vdd, Vt's,
and circuit design style for different levels of performance and
power dissipation. Down the road dual gate technology could offer
crisper device performance for very low threshold voltage CMOS. Also
FETs achieve specific transconductance performance comparable to BJTs
at gate lengths around 0.25 um (although I hear different values for
the cross over point from different sources - it is really comparing
two moving targets since bipolar processes continue to advance too
albeit at a much slower pace)

A bipolar chip needs a power supply with at least several strong
forward biased PN junction potentials to operate (or more, depending
on the number of stacked ECL/CML diff stages in complex gates).
Finally, bipolar gates burn bias current even when quiescent. It
would be hard to replicate the power savings from dynamic power
management schemes (e.g. not clocking FPU pipestages when no FP
instructions are active) in a bipolar CPU design.

>
> -Z-

All opinions strictly my own.

Zalman Stern

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Jul 21, 1999, 3:00:00 AM7/21/99
to
Paul DeMone <pde...@igs.net> wrote:
: The R6000 and BIT came darn closing to putting MIPS into
: chapter 11 IIRC.

I believe MIPS brush with chapter 11 somewhat predates the R6000. By the
time the R6000 was having yield hassles, the company had something like $57
million in the bank, but a lot of other problems.

: One question: how does the R6000 stack up to the R4000?

The R6000 FCS was more than a year before the R4000. In fact many of the
R4000 simulations were run on R6000 machines. (MIPS 6280s with 3/4 gig of
memory. Serious big iron for 1990/1991.) I can't recall the SPEC90 numbers
for the two, but the R4000 was probably a little less than twice as fast as
the R6000 at its highest non MCM clockspeed. The R4000 was of course
64-bit, though it hardly mattered to end users.

If the question is one of ECL vs. CMOS, the 21064 is the part that you want
to compare to. The R4000, while laying claim to the world's fastest title
for a little while, was not the decisive stroke it was expected to be. The
R4000 had a lot of business, as opposed to performance, oriented
requirements. It was targeted at three distinct CMOS processes and there
were features such as master checker mode that got added relatively late in
the game.

-Z-

Renu Raman

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Jul 21, 1999, 3:00:00 AM7/21/99
to

Hi David!

Of all the ECL projects, Sun's ECL machine actually worked, exceeded
speed goals (the chips, I meant) and could have shipped. The reason for
pulling the plug was not tecnical - but a business decision. The cost
of bringing that to market Vs the size and shape Sun was at that time.
I think it was the right call. To a large extent, MIPS R6000 distracted
the company.

w.r.t technology mainstream Vs exotic - there are interesting
lessons and possible futures

CMOS vs ECL
IP vs ATM
Magnetic storage Vs optical (RW)

and some of the evolutionary vs revolutionary fights

EDO/SDRAM vs Rambus

In article <3794...@news.spies.com> da...@slack.com (David DiGiacomo) writes:
>In article <3793D5D2...@igs.net>, Paul DeMone <pde...@igs.net> wrote:
>> Sorry but like the Monty Python parrot, Exponential is quite dead.
>> For all you venture capitalists out there remember the following
>> score: CMOS 4 Bipolar 0

>> (RIP: BIT SPARC, BIT MIPS R6000, MicroUnity CPU, Exponential PPC)
>

>I don't like this scorecard because it mixes up ECL and ECL/CMOS with
>"classic BiCMOS" (CMOS + NPN pullups). Of course, Exponential was happy to
>do exactly that -- Mark Johnson must have been amused that they tried to
>give their design legitimacy by calling it BiCMOS.
>
>How about this:
>
>ECL: 0/4 or 0/5
>BIT MIPS R6000 - mostly a failure (late, problematic)
>BIT SPARC (Sunburn/Suntan) - failure (never shipped)
>ECL SPARC project #2 - failure (never shipped)

>FTL - what was this? not a success

>Exponential PPC (ECL/CMOS) - failure
>
>BiCMOS: 1.5/3
>Sun/TI Viking - late, slow, ultimately shipped in volume
>Pentium - success
>MicroUnity - failure
>
>I'm sure there are more BiCMOS successes & failures that could be added.


--


Sander Vesik

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Jul 21, 1999, 3:00:00 AM7/21/99
to
In comp.arch Sean Burke <sean_...@earthlink.net> wrote:
> Zalman Stern wrote:
> >
> > Zalman Stern <zal...@netcom15.netcom.com> wrote:
> > : And while you're dissing bipolar, don't forget to mentium the original
> > ^^^^^^^
> > : Pentium.
> >
> > Hmmm... So was it the scone or the latte they spiked this morning?
> >
> > Perhaps more relevant to the thread, the only thing that makes more sense
> > than building single chip multiprocessors to go in a Macintosh is to fab
> > them in BiCMOS or perhaps even GaAs.


> You might be underestimating the attraction. (You did intend
> sarcasm, right?) Apple would get a 4way SMP capability without
> (presumably) needing to build a specialized chipset or motherboard.

> Apple's customers often run applications like Photoshop, which will
> benefit from SMP. (But you knew that! :^) Also, many games of the

You hit the nail. Photoshop will benefit from SMP. For whom do you
think were the (A)SMP Mac clones and 2/4-way processor replacement
cards targeted at?

> 3D-interactive-blast-em sort are threaded, and will benefit from SMP.
> A low-end SMP system could be attractive to both types of customer.

Maybe not. But I had the impression not many of those were tagerted at
Mac at all, and you can probably compensate it all somewhat by having
a multithreaded display/OpenGL drivers.

> And of course, a low-power SMP chip would be attractive in all sorts
> of embedded applications where PowerPC is currently popular.

I though not only Motorola but several others were making 2 processor
embedded boards. If the 4-way boards were just as easy to make as
1 processor boards (and just as cheap) why would the present users of
2-way boards not happily migrate?

The other kinds of users probably also use the special embedded processors.

> -SEan

--
Sander

There is no love, no good, no happiness and no future -
all these are just illusions.

Greg Pfister

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Jul 21, 1999, 3:00:00 AM7/21/99
to
Sander Vesik wrote:
>
> In comp.arch Sean Burke <sean_...@earthlink.net> wrote:
> > Zalman Stern wrote:
> > >
> > > Zalman Stern <zal...@netcom15.netcom.com> wrote:
[snip]

> > > Perhaps more relevant to the thread, the only thing that makes more sense
> > > than building single chip multiprocessors to go in a Macintosh is to fab
> > > them in BiCMOS or perhaps even GaAs.
>
> > You might be underestimating the attraction. (You did intend
> > sarcasm, right?) Apple would get a 4way SMP capability without
> > (presumably) needing to build a specialized chipset or motherboard.
>
> > Apple's customers often run applications like Photoshop, which will
> > benefit from SMP. (But you knew that! :^) Also, many games of the
>
> You hit the nail. Photoshop will benefit from SMP. For whom do you
> think were the (A)SMP Mac clones and 2/4-way processor replacement
> cards targeted at?
>
> > 3D-interactive-blast-em sort are threaded, and will benefit from SMP.
> > A low-end SMP system could be attractive to both types of customer.
>
> Maybe not. But I had the impression not many of those were tagerted at
> Mac at all, and you can probably compensate it all somewhat by having
> a multithreaded display/OpenGL drivers.

That part's easily overcome. Graphics in general has lots of
parallelism, and lots of graphics gets done on PCs. The problem
is that the apps aren't written first for the Mac, they're for
tne IBM PC, then ported. T

here are two reasons why I think SMPs won't appear there any time
soon, even though they could certainly be used well:

1) Difficulty of supporting it in Win95, wich which compability
must be maintained. Win95 isn't an OS, really, so maybe this
isn't as much of a problem. Still have to boot the thing, though.
Maybe if MS actually gets everybody moved to NT/2000 this will go
away.

2) It would cost Intel a lot of money, and none of the PC vendors
are willing to jeopardize their relationship with Intel. Intel
charges a BIG premium for the fastest chips -- I seem to recall
that a 2X speed difference was worth 10X in price. They really
don't want you plugging two (or maybe 3, or 4) cheap processors
in and getting the same performance as the fastest ones.

Greg Pfister
<not my employers' opinion>

Mike Albaugh

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Jul 21, 1999, 3:00:00 AM7/21/99
to
Sander Vesik (san...@haldjas.folklore.ee) wrote:

: > And of course, a low-power SMP chip would be attractive in all sorts


: > of embedded applications where PowerPC is currently popular.

: I though not only Motorola but several others were making 2 processor
: embedded boards. If the 4-way boards were just as easy to make as
: 1 processor boards (and just as cheap) why would the present users of
: 2-way boards not happily migrate?

As someone who has ridden the cycle from "one big engine" to
"small numbers of formerly-considered-big engines" and back a few times,
I'd suggest that it's at least partially because task partioning is
not "slam dunk" easy. And it doesn't get any easier when management
keeps changing the "Embedded OS of choice", and each has subtly different
synchronization primitives.

Mike
| alb...@agames.com, speaking only for myself

Alan W. Glaser

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Jul 21, 1999, 3:00:00 AM7/21/99
to
Greg Pfister <pfi...@us.ibm.com> wrote:

: Sander Vesik wrote:
:>
:> In comp.arch Sean Burke <sean_...@earthlink.net> wrote:
:> > 3D-interactive-blast-em sort are threaded, and will benefit from SMP.

:> > A low-end SMP system could be attractive to both types of customer.
:>
:> Maybe not. But I had the impression not many of those were tagerted at
:> Mac at all, and you can probably compensate it all somewhat by having
:> a multithreaded display/OpenGL drivers.
:
: That part's easily overcome. Graphics in general has lots of
: parallelism, and lots of graphics gets done on PCs. The problem
: is that the apps aren't written first for the Mac, they're for
: tne IBM PC, then ported. T
:
: here are two reasons why I think SMPs won't appear there any time
: soon, even though they could certainly be used well:
<snip>

Actually, Quake III Arena (http://www.quake3arena.com) now supports SMP
(at least on the Win32/Linux side) and is being simultaneously developed
by id software for Win32, Mac and Linux.

--
Alan Glaser "It's not a competition,
ECE Dept. it's just a mint..." - K
North Carolina State University
PGP fingerprint: 14 C8 D6 30 D0 A6 03 6F 23 F3 9F 1D 61 43 EE 8C

Zalman Stern

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Jul 21, 1999, 3:00:00 AM7/21/99
to
Sander Vesik <san...@haldjas.folklore.ee> wrote:
: You hit the nail. Photoshop will benefit from SMP. For whom do you

: think were the (A)SMP Mac clones and 2/4-way processor replacement
: cards targeted at?

All of which were relatively marginal from an economics point of view.
(I.e. noone builds those machines anymore and most of the companies
involved went out of business. Part of this has to do with Apple licensing
decisions, but the most successful clone vendor was Power Computing and I
don't recall them shipping SMP Macs. They may have OEM'ed the Daystar stuff
for a while...)

Photoshop SMP has always been a less than 50% solution. The stuff it helps
goes faster up to a point, but a relatively small amount of code is ever
parallelized. (The fact that it is relatively difficult to write
mutiprocessor code on the Mac has something to do with this.) And Amdahl's
law kicks in. But even more fundamentally, a lot of the Photoshop image
processing code is now memory bandwidth limited. Doubly so with AltiVec.

All said and done, it would be a miracle if single chip SMP can offer a 2x
speedup across the board on Photoshop vs. a contemporary single processor
when it ships. "Photoshop goes twice as fast" is not enough of a market to
justify the chip development.

And on a final note, you're probably happier buying extra RAM than buying
an extra processor for Photoshop use. Or even really fast disks.

There have been a lot of posts here about the software problems IA64
faces. Single chip SMP on the Mac is in the same boat. There is still no
strong software infrastructure for SMP on the Mac. (On top of the fact that
effective software parallelization is hard work in the best of
circumstances.)

-Z-

Terje Mathisen

unread,
Jul 21, 1999, 3:00:00 AM7/21/99
to
Alan W. Glaser wrote:
>
> Actually, Quake III Arena (http://www.quake3arena.com) now supports SMP
> (at least on the Win32/Linux side) and is being simultaneously developed
> by id software for Win32, Mac and Linux.

Right, if you check out one or more of the FPS/3D news pages
(http://www.bluesnews.com and many others) you'll notice that the SMP
(really two-cpu) version of Q3A is responsible for a lot of new interest
in NT.

According to Carmack, the SMP version is particularly attractive because
it helps the most when it matters most, i.e. with many dynamic objects
(players/monsters/rocket trails etc) visible at the same time.

Since this is the moment when you 'frag or be fragged', serious gamers
are doing all sorts of funky things, like using dual Celerons in
hacked-up motherboards just to get the cheapest possible fast SMP
machine.

Terje

(Not particularly interested in 3D games, except as a very interesting
programming problem.)

--
- <Terje.M...@hda.hydro.com>
Using self-discipline, see http://www.eiffel.com/discipline
"almost all programming can be viewed as an exercise in caching"

Paul DeMone

unread,
Jul 21, 1999, 3:00:00 AM7/21/99
to

Zalman Stern wrote:
>
> Paul DeMone <pde...@igs.net> wrote:
> : The R6000 and BIT came darn closing to putting MIPS into
> : chapter 11 IIRC.
>
> I believe MIPS brush with chapter 11 somewhat predates the R6000. By the
> time the R6000 was having yield hassles, the company had something like $57
> million in the bank, but a lot of other problems.
>
> : One question: how does the R6000 stack up to the R4000?
>
> The R6000 FCS was more than a year before the R4000. In fact many of the
> R4000 simulations were run on R6000 machines. (MIPS 6280s with 3/4 gig of
> memory. Serious big iron for 1990/1991.) I can't recall the SPEC90 numbers
> for the two, but the R4000 was probably a little less than twice as fast as
> the R6000 at its highest non MCM clockspeed. The R4000 was of course
> 64-bit, though it hardly mattered to end users.


It was actually a rhetorical question meant to show how bipolar
CPUs are born in a position of immediately needing to run hard
to stay ahead of the CMOS steamroller relentlessly grinding
forward. None do. Road kill. Here's some numbers:

R6000 R4000

process ECL 0.8 um CMOS
clock freq (MHz) 60 100
transistors 89k 1.35m
power (W) 23 12

Dhry MIPS 2.1 49 95
Linpack MFLOP/s 10 11
Stream/copy MB/s 53.5 61.5
SPECmark89 42.5 70.4
SPECint92 40.6 61.7
SPECfp92 45.1 63.4


The R4000 was followed relatively shortly by the R4000A, ahem R4400
which had doubled caches and ran faster - ah, progress.

"Better Computing through CMOS-stry"

>
> If the question is one of ECL vs. CMOS, the 21064 is the part that you want
> to compare to. The R4000, while laying claim to the world's fastest title

I don't understand this comment. Early Alphas took 2x clock inputs
using
AC coupled ECL signalling levels and had facilities for PECL
compatible
input voltage levels but all Alphas are/were pure CMOS devices
including
the 21064.

> for a little while, was not the decisive stroke it was expected to be. The
> R4000 had a lot of business, as opposed to performance, oriented
> requirements. It was targeted at three distinct CMOS processes and there
> were features such as master checker mode that got added relatively late in
> the game.

I have always wondered how much performance MIPS gave up having to be
process generic. Another thing is the partner's processes of that
era were ASIC oriented and not particularly aggressive enough for
building high performance micros. Over the years several MIPS people
have claimed that the price paid in not tuning for one process was
insignificant but my own experience designing and tuning high speed
circuits and layout into different processes suggests otherwise.

Jay Lessert

unread,
Jul 21, 1999, 3:00:00 AM7/21/99
to
In article <37951A75...@igs.net>, Paul DeMone <pde...@igs.net> wrote:
>
> The R6000 and BIT came darn closing to putting MIPS into
> chapter 11 IIRC.

Well, there's two (at least) pretty complicated sides to that story.
Suffice to say there were plenty of problems to go around, it was
plenty painful for *all* concerned, and *very* few of the problems
had anything to do with whether there was a collector implant
instead of gate oxide on the process. :-)

FWIW (jeez, I *hope* the statute of limitations has run out!), the
yield problems BIT had during the middle half of the R6000 project(s)
were a very subtle problem with a metal1 etch step, induced by changes
made to fab equipment in the aftermath of a fire. Again, nothing
intrinsic to bipolar, and there were plenty of other development
problems as well.

> One question: how does the R6000 stack
> up to the R4000?

Well, according to some very dusty old e-mail and Usenet logs, the
second generation R6000A (67MHz, 1H91) and the last generation R6000A
(80MHz, 2H92) straddle the R4000 (50/100MHz, 1H92) chronologically...

System Processor Cache SPECmark89 Source
------ --------- ----- ---------- ------
CDC 4680 R6000A 67Mhz 1MB+64/16 55.7 CDC SVO, comp.arch 4/91
CDC 4680-300 R6000A 80Mhz 2MB+64/16 75.4 CDC, comp.sys.cdc 9/92
SGI Crimson R4000 50/100MHz 1MB+8/8 70.0 comp.arch 6/92

Apologies for the SPECmark89 results, but AFAIK, CDC never submitted
SPECint92/SPECfp92 results for the 80Mhz-big-cache-MCM box. Their
customers mostly cared about TPC's and AIM numbers, I think. :-)

> at gate lengths around 0.25 um (although I hear different values for
> the cross over point from different sources - it is really comparing
> two moving targets since bipolar processes continue to advance too
> albeit at a much slower pace)

Right. This is quite simply the fundamental problem. There is just
such a massive world-wide investment in MOS process technology, so much
synergy. And it's mostly useless to bipolar folk (except for metal
systems).

> A bipolar chip needs a power supply with at least several strong
> forward biased PN junction potentials to operate (or more, depending
> on the number of stacked ECL/CML diff stages in complex gates).

Right. ECL loses about 25% gate density moving from 5V -> 3.3V because
you just have to drop one level of series-gating. And you can't really
go below that.

> Finally, bipolar gates burn bias current even when quiescent.

But that's not really much of a problem when your CV^^2F power is based
on a V (logic swing, not power supply, remember) of 500mV, or lower. :-)
--
Jay Lessert Portland, Oregon USA j...@teleport.com

Jay Lessert

unread,
Jul 21, 1999, 3:00:00 AM7/21/99
to
In article <37964626...@igs.net>, Paul DeMone <pde...@igs.net> wrote:
> It was actually a rhetorical question meant to show how bipolar
> CPUs are born in a position of immediately needing to run hard
> to stay ahead of the CMOS steamroller relentlessly grinding
> forward. None do. Road kill. Here's some numbers:
>
> R6000 R4000
>
> process ECL 0.8 um CMOS
> clock freq (MHz) 60 100
> transistors 89k 1.35m
> power (W) 23 12
>
> Dhry MIPS 2.1 49 95
> Linpack MFLOP/s 10 11
> Stream/copy MB/s 53.5 61.5
> SPECmark89 42.5 70.4
> SPECint92 40.6 61.7
> SPECfp92 45.1 63.4

An apples-to-apples (2H92) comparison shows SPECmark89=75.4 for an
80MHz R6000A. But what's really interesting here is something you
might not know-- The BIT process this stuff was built on was
essentially 2.0 um CMOS lithography/etch/etc.

So with that handicap, it's fairly amazing it manages to keep up. The
advantages of ECL (device gm, logic swing) are real, and were
substantial in the late 80's and early 90's. But not nearly enough to
stay ahead of the steamroller. :-)

Zalman Stern

unread,
Jul 22, 1999, 3:00:00 AM7/22/99
to
Paul DeMone <pde...@igs.net> wrote:
: It was actually a rhetorical question meant to show how bipolar
: CPUs are born in a position of immediately needing to run hard
: to stay ahead of the CMOS steamroller relentlessly grinding
: forward. None do. Road kill. Here's some numbers:

You'll get no disagreement from me. The issue here is that the R6000 was
significantly earlier than the R4000. Also the original clock target for
the R6000 was 80 MHz. Had it gone closer to plan, it would have been a
grand success. Both the R6k and the R4k had their share of problems. I
think the R6000 can be viewed as a marginal success given the systems
revenue to MIPS. But its hard to tell as the entire "gotta be a computer
company so we can get to a billion in revenue" strategy for MIPS was pretty
dubious.

[Alpha comments.]

The point is that 21064 better shows the superiority of performance at all
costs CMOS than the R4k does.

-Z-

Paul DeMone

unread,
Jul 22, 1999, 3:00:00 AM7/22/99
to

Zalman Stern wrote:
[snip]


> You'll get no disagreement from me. The issue here is that the R6000 was
> significantly earlier than the R4000. Also the original clock target for
> the R6000 was 80 MHz. Had it gone closer to plan, it would have been a
> grand success. Both the R6k and the R4k had their share of problems. I
> think the R6000 can be viewed as a marginal success given the systems
> revenue to MIPS.

I agree with you that that the R6000 was the closest monolithic
bipolar CPUs have come to success as a result of performance
leadership acruing from gate delay advantages. However, the
production problems BIT had (for whatever reasons, Jay) did
put a big cloud over the part.

The R6000 made it to market and made customers happy. The
other bipolar CPU roadkill expired far before this stage.
However, the lesson of the R6000 was it still couldn't keep
up. It is not *just* price/performance where CMOS wins, it
quickly gains the advantage of both much lower price and higher
absolute performance.


[snip]


> [Alpha comments.]
>
> The point is that 21064 better shows the superiority of performance at all
> costs CMOS than the R4k does.

Yes, the Alpha guys take CMOS to the extreme. Any bipolar CPU
enthusiasts out there nursing a business plan had better look
long and hard at what they are up against. BJTs have higher gm
per unit area? well FETs certainly closed the gap if not overtaken
them. Low voltage swings? The operand buses connecting reg files
and functional units in the Alpha 21264 only swing 200 mV.

Remember CMOS is a chameleon. You can mix static CMOS, dynamic
CMOS, differential logic, pass transistor logic, pseudo NMOS,
and many, many more logic implementation techniques and styles
(each with its own unique sets of pros and cons) all in the same
chip. I have designed in NMOS and bipolar but CMOS beats them
all hands down for flexibility, performance, and low power. I
have even observed a GaAs chip project that went from "the only way
to do job X" status at kickoff to "why the hell didn't we do this
$#!%@# chip in CMOS - its faster!" by tape out. :-0

Steinar Haug

unread,
Jul 25, 1999, 3:00:00 AM7/25/99
to
[Terje Mathisen]

| Since this is the moment when you 'frag or be fragged', serious gamers
| are doing all sorts of funky things, like using dual Celerons in
| hacked-up motherboards just to get the cheapest possible fast SMP
| machine.

You don't even need a hacked-up motherboard. The Abit BP6 is built for
dual Socket 370 Celerons, and works very well as an inexpensive SMP
solution. Intel probably doesn't like it...

Steinar Haug, Nethelp consulting, sth...@nethelp.no

Terje Mathisen

unread,
Jul 25, 1999, 3:00:00 AM7/25/99
to
Steinar Haug wrote:
>
> [Terje Mathisen]
>
> | Since this is the moment when you 'frag or be fragged', serious gamers
> | are doing all sorts of funky things, like using dual Celerons in
> | hacked-up motherboards just to get the cheapest possible fast SMP
> | machine.
>
> You don't even need a hacked-up motherboard. The Abit BP6 is built for
> dual Socket 370 Celerons, and works very well as an inexpensive SMP
> solution. Intel probably doesn't like it...

Yeah, I've followed that development. First you had to hack the mb, then
you got the 'slockets', so you could patch those, then someone started
selling them with the needed fix, and now you can buy a pre-patched mb.

This will almost certainly force Intel to cut one or two traces on
future low-end cpus, just to make it possible for them to maintain
market segregation.

I need a PIII machine to allow me to write code using the new
instructions, otherwise my next computer would have been one of those
over-clocked dual Celery stalks.

Terje

PS. A friend here at Hydro has one of the very first successfully
modified motherboards, according to him, they had to teach the German
guys how to make it work.

Paul Hsieh

unread,
Aug 1, 1999, 3:00:00 AM8/1/99
to
In article br...@hoult.actrix.gen.nz says...

> In article Mark Johnson wrote:
>
> > Whip out your trusty Internet search engine and look
> > for "Exponential Technology" --- a company that built
> > an extremely high-end Power PC. They agreed with
> > you, dissipating lots of power is one way to boost
> > the performance.
>
> Nah. They were planning to ship at 500 MHz, but with a PPC601-like
> machine with not much cache. Their chip would have been good if it hadn't
> been for the 350 MHz 604e (which would thrash the Exponential 701 on
> CPU-intensive code) and the PPC750 (which would thrash the 701 on anything
> that used much memory).
>
> There was a time that it would have been a great chip, but by the time it
> looked like coming out it had been passed by.

The story I've been told is that Apple, Motorola and IBM, for some
reason, did a one-two-three punch to kill Xponential (Jobs nuked the
clone manufacturers that were interested in using Xponential, while Mot
and IBM spread some FUD about how their next generation CPUs were going
to be faster than what Xponential had in hand), rather than support them
for a while to see whether they could sustain a second generation chip
which was less of a compromise.

The result? The Apple line is stuck with Motorola's mediocre PPC line
(since IBM couldn't seem to get their act together and design anything
interesting to Apple.) Had Apple at least supported Xponential, they
might easily have close to Ghz CPUs right now, as well as some
interesting leverage against Intel in the form of instruction switching
patents (that are now owned by S3.)

Oh well, so much for the road not travelled.

--
Paul Hsieh
q...@pobox.com

Alex Rosenberg

unread,
Aug 2, 1999, 3:00:00 AM8/2/99
to
In article <MPG.120dba291...@nntp.mindspring.com>, q...@pobox.com
(Paul Hsieh) wrote:

>The story I've been told is that Apple, Motorola and IBM, for some
>reason, did a one-two-three punch to kill Xponential (Jobs nuked the
>clone manufacturers that were interested in using Xponential, while Mot
>and IBM spread some FUD about how their next generation CPUs were going
>to be faster than what Xponential had in hand), rather than support them
>for a while to see whether they could sustain a second generation chip
>which was less of a compromise.

This is the side of the story told by Exponential's lawyers.

>The result? The Apple line is stuck with Motorola's mediocre PPC line
>(since IBM couldn't seem to get their act together and design anything
>interesting to Apple.) Had Apple at least supported Xponential, they
>might easily have close to Ghz CPUs right now, as well as some
>interesting leverage against Intel in the form of instruction switching
>patents (that are now owned by S3.)

Pretty much all you need to know at this point to understand the real
story is that the X701 was single issue. It's _only_ advantage was clock
speed and that was more than overcome by the 604's 4-way issue.

+------------------------------------------------------------+
| Alexander M. Rosenberg <mailto:alexr@_spies.com> |
| Nobody cares what I say. Remove the underscore to mail me. |

Paul Hsieh

unread,
Aug 3, 1999, 3:00:00 AM8/3/99
to
al...@spies.com says...

> q...@pobox.com (Paul Hsieh) wrote:
> >The story I've been told is that Apple, Motorola and IBM, for some
> >reason, did a one-two-three punch to kill Xponential (Jobs nuked the
> >clone manufacturers that were interested in using Xponential, while Mot
> >and IBM spread some FUD about how their next generation CPUs were going
> >to be faster than what Xponential had in hand), rather than support them
> >for a while to see whether they could sustain a second generation chip
> >which was less of a compromise.
>
> This is the side of the story told by Exponential's lawyers.

Well, some of their ex-employees believe this too. There is no other
reasonable explanation for what happened to them that I've ever heard.

> >The result? The Apple line is stuck with Motorola's mediocre PPC line
> >(since IBM couldn't seem to get their act together and design anything
> >interesting to Apple.) Had Apple at least supported Xponential, they
> >might easily have close to Ghz CPUs right now, as well as some
> >interesting leverage against Intel in the form of instruction switching
> >patents (that are now owned by S3.)
>
> Pretty much all you need to know at this point to understand the real
> story is that the X701 was single issue. It's _only_ advantage was clock
> speed and that was more than overcome by the 604's 4-way issue.

Yeah, I believe a little known processor called the 21064 started life
this way too and where are they now ... oh wait a second, their latest
incarnation the 21264 is the fastest (if we ignore dumb things like
putting 2MB of L1 cache on your processor) processor on earth isn't it?

--
Paul Hsieh
q...@pobox.com

Zalman Stern

unread,
Aug 3, 1999, 3:00:00 AM8/3/99
to
Paul Hsieh <q...@pobox.com> wrote:
: Well, some of their ex-employees believe this too. There is no other
: reasonable explanation for what happened to them that I've ever heard.

This is consistent with the netnews posts you've made over the last year or
so. (I.e. you aren't a very reliable source of information about these things.)

I never ran code on an the Exponential chip but people I trust who did were
somewhat unimpressed. On the one hand, they exceeded expectation by
actually producing something that worked. But the "blows everything away"
on performance claims were simply untrue. (And completely predictably so.
There is virtually nothing one can do in a CPU alone to get a 2X
performance advantage across a broad range of code in a competitive market.
Especially if the CPU has equal or worse memory bandwidth than the
competition.)

Exponential might have made it if their second design was a vast
improvement and the Mac clone market took off and they got a design win
with with IBM for RS/6000 highend. As such it wasn't the stupidest startup
idea I've seen, but it wasn't a very good one either. (Of course x86 clone
makers haven't done very well either. The notion that "anything that works
at all will sell" translates to "anything that works at all might make an
impact on margins for Intel and AMD for a few months.")

: Yeah, I believe a little known processor called the 21064 started life

: this way too and where are they now ... oh wait a second, their latest
: incarnation the 21264 is the fastest (if we ignore dumb things like
: putting 2MB of L1 cache on your processor) processor on earth isn't it?

The 21064 was both a screamer on clockspeed *and* instruction level
paralellism for its day. It was a two way superscalar with tight issue
rules at 1.5x to 2x the clockspeed of any other two way superscalar at the
time of its introduction. (I can't recall where HP was exactly at the time
so I'll give those folks a shot at correcting me.) The 21064 also had
competitively sized onchip cache for its time.

And despite all this advantage it was pretty easy to compile code for
competitively priced 21064 and Pentium NT boxes and see only a 10%-20%
performance increase on the Alpha. It was probably also easy to fix that,
but given the market, very few ISVs bothered to try. Had the 21064 been
launched by a startup, the 21164 probably never would have happened.

-Z-

pde...@igs.net

unread,
Aug 3, 1999, 3:00:00 AM8/3/99
to

Paul Hsieh wrote:
>
> al...@spies.com says...
[snip]


> > Pretty much all you need to know at this point to understand the real
> > story is that the X701 was single issue. It's _only_ advantage was clock
> > speed and that was more than overcome by the 604's 4-way issue.
>

> Yeah, I believe a little known processor called the 21064 started life
> this way too and where are they now

Actually the 21064 could dual issue an integer instruction and
a floating point instruction.

> ... oh wait a second, their latest
> incarnation the 21264 is the fastest (if we ignore dumb things like
> putting 2MB of L1 cache on your processor) processor on earth isn't it?

If you compare 0.25 um apples to 0.25 um apples (ie 21264A aka EV67
to the PA8500) you no longer need to add this caveat. It will be
interesting to compare Alpha and PA-RISC performance when both 1) are
in the same feature size process (or even better, in the same
process),
and 2) have large on chip caches (i.e. EV7 vs PA-8X00, x = 6 or 7)

BTW, the 21264A is currently the fastest clocking MPU *and* the most
sophisticated (in terms of out of order execution capabilities). I
guess it is king of both the brainiacs and the speed racers :)

>
> --
> Paul Hsieh
> q...@pobox.com

Allen J. Baum

unread,
Aug 3, 1999, 3:00:00 AM8/3/99
to
In article <MPG.121051a5...@nntp.mindspring.com>, q...@pobox.com (Paul Hsieh) wrote:

> al...@spies.com says...
> > q...@pobox.com (Paul Hsieh) wrote:
> > >The story I've been told is that Apple, Motorola and IBM, for some
> > >reason, did a one-two-three punch to kill Xponential (Jobs nuked the
> > >clone manufacturers that were interested in using Xponential, while Mot
> > >and IBM spread some FUD about how their next generation CPUs were going
> > >to be faster than what Xponential had in hand), rather than support them
> > >for a while to see whether they could sustain a second generation chip
> > >which was less of a compromise.
> >
> > This is the side of the story told by Exponential's lawyers.
>

> Well, some of their ex-employees believe this too. There is no other
> reasonable explanation for what happened to them that I've ever heard.

I've heard both sides. The AIM side is that they got run over by the CMOS
truck; the first Exponential chips didn't run anywhere near speed.
Apple ran the numbers, and decided that by the time it did, they'd have
CMOS chips with the same speed running out of much cheaper fabs,
that could be put into boxes with less stringent power supply and cooling
requirements, and weren't single sourced (more or less).

I don't know enough of the chronology to know if the IBM/Moto competitors
where FUDdy or not.

By the way, it isn't the only clone chip that was killed - to paraphrase Yoda
"There was another".

Paul Hsieh

unread,
Aug 3, 1999, 3:00:00 AM8/3/99
to
ab...@pa.dec.com says...

> q...@pobox.com (Paul Hsieh) wrote:
> > al...@spies.com says...
> > > q...@pobox.com (Paul Hsieh) wrote:
> > > >The story I've been told is that Apple, Motorola and IBM, for some
> > > >reason, did a one-two-three punch to kill Xponential (Jobs nuked the
> > > >clone manufacturers that were interested in using Xponential, while Mot
> > > >and IBM spread some FUD about how their next generation CPUs were going
> > > >to be faster than what Xponential had in hand), rather than support them
> > > >for a while to see whether they could sustain a second generation chip
> > > >which was less of a compromise.
> > >
> > > This is the side of the story told by Exponential's lawyers.
> >
> > Well, some of their ex-employees believe this too. There is no other
> > reasonable explanation for what happened to them that I've ever heard.
>
> I've heard both sides. The AIM side is that they got run over by the CMOS
> truck; the first Exponential chips didn't run anywhere near speed.
> Apple ran the numbers, and decided that by the time it did, they'd have
> CMOS chips with the same speed running out of much cheaper fabs,
> that could be put into boxes with less stringent power supply and cooling
> requirements, and weren't single sourced (more or less).

An Xponential guy I talked to about this said that indeed the "533Mhz"
demo was just that, a demo. However he claims they were definately able
to hit 400Mhz, which Motorola only got to earlier this year (and which at
the time was just shy of where Alpha was, and well ahead of Intel and
Motorola).

> I don't know enough of the chronology to know if the IBM/Moto competitors
> where FUDdy or not.

Well, we now know that anything that 'I' part of AIM said definately was
FUD. They failed to deliver on the 620 and they failed to deliver on
their "604" (and Xpontential) killer, and they eventually left the PPC
pact with Motorola. Motorola's PPC 750 actually *dropped* in clock rate
for some supposed architectural performance benefit.



> By the way, it isn't the only clone chip that was killed - to paraphrase Yoda
> "There was another".

I'm shocked that there were two other companies interested in getting
into what back then must have been an extremely tiny market.

--
Paul Hsieh
q...@pobox.com

Alex Rosenberg

unread,
Aug 3, 1999, 3:00:00 AM8/3/99
to
In article <MPG.12115012a...@nntp.mindspring.com>, q...@pobox.com
(Paul Hsieh) wrote:

>An Xponential guy I talked to about this said that indeed the "533Mhz"
>demo was just that, a demo. However he claims they were definately able
>to hit 400Mhz, which Motorola only got to earlier this year (and which at
>the time was just shy of where Alpha was, and well ahead of Intel and
>Motorola).

Didn't we just get finished explaining that clock speed is not the onyl
performance indicator here?

>ab...@pa.dec.com says...


>> I don't know enough of the chronology to know if the IBM/Moto competitors
>> where FUDdy or not.
>
>Well, we now know that anything that 'I' part of AIM said definately was
>FUD. They failed to deliver on the 620 and they failed to deliver on
>their "604" (and Xpontential) killer, and they eventually left the PPC
>pact with Motorola. Motorola's PPC 750 actually *dropped* in clock rate
>for some supposed architectural performance benefit.

You really have been toking on that anti-Apple bong of yours too much.

Anil T Maliyekke

unread,
Aug 4, 1999, 3:00:00 AM8/4/99
to
Paul Hsieh <q...@pobox.com> wrote:

> An Xponential guy I talked to about this said that indeed the "533Mhz"
> demo was just that, a demo. However he claims they were definately able
> to hit 400Mhz, which Motorola only got to earlier this year (and which at
> the time was just shy of where Alpha was, and well ahead of Intel and
> Motorola).

Of course that Xponential chip consumed over 6 times as much power than a
PPC750 and wouldn't have performed any better than 750 or 604e running at
half the clock speed due to its small caches and single issue design.
Plus being a bipolar design, it wouldn't have benefited from the rapid
improvements in CMOS processing technology.

Del Cecchi

unread,
Aug 4, 1999, 3:00:00 AM8/4/99
to
In article <37A7649A...@igs.net>,
pde...@igs.net writes:
|>
snip snip

|>
|> BTW, the 21264A is currently the fastest clocking MPU *and* the most
|> sophisticated (in terms of out of order execution capabilities). I
|> guess it is king of both the brainiacs and the speed racers :)
|>

|>

|> All opinions strictly my own.
|> --
|> Paul W. DeMone The 801 experiment SPARCed an ARMs race of EPIC
|> Kanata, Ontario proportions to put more PRECISION and POWER into
|> dem...@mosaid.com architectures with MIPSed results but ALPHA's well
|> pde...@igs.net that ends well.

Is it some kind of natural law that every thread on comp.arch, except maybe the
nintendo ones, ends up talking about alpha?
--

Del Cecchi
cecchi@rchland

Tim Olson

unread,
Aug 4, 1999, 3:00:00 AM8/4/99
to
> ab...@pa.dec.com says...

> > I've heard both sides. The AIM side is that they got run over by the CMOS
> > truck; the first Exponential chips didn't run anywhere near speed.
> > Apple ran the numbers, and decided that by the time it did, they'd have
> > CMOS chips with the same speed running out of much cheaper fabs,
> > that could be put into boxes with less stringent power supply and cooling
> > requirements, and weren't single sourced (more or less).

This is pretty much correct (if by "speed" you mean "overall
performance", and not just clock frequency). Exponential also got "run
over" by the large amount of "GCC" (Generic Crappy Code) that existed in
the Apple desktop world at the time; the 704's on-chip cache structure
was just not suited for it. It probably would have made a good
Photoshop cruncher (yes, many filters are processor, not memory
limited), but simulating its performance using Apple's internal code
trace suite (hardware collected, including app and OS code) showed that
it would have wound up in the middle of the pack, compared to
contemporaneous Somerset processors.


> Motorola's PPC 750 actually *dropped* in clock rate
> for some supposed architectural performance benefit.

The 750 was lower clock rate than the Mach-5 604, because it was
designed and manufactured in a less aggressive process (the Mach-5 had
many fewer microarchitectural changes, and was mainly wanted by IBM, so
it went into an newer, IBM-only process). However, the 750 performed
much better than the Mach-5 in Apple systems (as it was designed to do).

Peter Seebach

unread,
Aug 4, 1999, 3:00:00 AM8/4/99
to
In article <7o9e4b$tea$1...@news.rchland.ibm.com>,

Del Cecchi <dce...@vnet.ibm.com> wrote:
>Is it some kind of natural law that every thread on comp.arch, except maybe the
>nintendo ones, ends up talking about alpha?

Well, it's interesting and famous.

I just got my first personal-use alpha up and running this week. ;)

-s
--
Copyright 1999, All rights reserved. Peter Seebach / se...@plethora.net
C/Unix wizard, Pro-commerce radical, Spam fighter. Boycott Spamazon!
Will work for interesting hardware. http://www.plethora.net/~seebs/
Visit my new ISP <URL:http://www.plethora.net/> --- More Net, Less Spam!

Paul DeMone

unread,
Aug 4, 1999, 3:00:00 AM8/4/99
to

Del Cecchi wrote:
[snip]


> Is it some kind of natural law that every thread on comp.arch, except maybe the
> nintendo ones, ends up talking about alpha?

Sounds like someone is suffering from processor envy ;-)

It just seems that way to you because of the dearth of interesting
news or architectural and implementation innovations from the
Power/PPC
camp being made public. Only thing I heard in the last two weeks
re IBM semi was the rumour that a fab agreement with Compaq had been
finalized and Alpha has been sampled in their damascene copper
process.
Oops I said the scarlet "A" word again, so sorry. Would you rather we
rehash the pros and cons of the U.S. library system again?

Lets look ahead and see what's on the agenda. K7 performance is
disclosed next Monday. At microprocessor forum the microanarchy,
oops I mean microarchitecture of Merced will be revealed along
with Sun's new MAJC ISA (another ISA? do they think they are
Motorola or what?) and a whole bunch more. We should also be
seeing some interesting stuff come out of Hot Chips (this week
IIRC). Maybe we should start a thread for everyone's best guess
or scurrilous rumours about what the new Willamette x86 core will
look like (bonus marks to anyone who can their pet theory mentioned
at The Register) Personally I am suprised no one wanted to argue
over minutia in the IA-64 runtime conventions HP recently published
on their web site.

So everyone now, lets try real hard to generate some Alpha-free
content for Del; apparently he's on doctors orders to avoid
aggravating his blood pressure :)


All opinions strictly my own.
--
Paul W. DeMone The 801 experiment SPARCed an ARMs race of EPIC
Kanata, Ontario proportions to put more PRECISION and POWER into

dem...@mosaid.com architectures with MIPSed results but *****'s well
pde...@igs.net that ends well.

Zalman Stern

unread,
Aug 4, 1999, 3:00:00 AM8/4/99
to
Del Cecchi <cec...@signa.rchland.ibm.com> wrote:
: Is it some kind of natural law that every thread on comp.arch, except

: maybe the nintendo ones, ends up talking about alpha?

200 years from now when someone finally writes a FAQ for comp.arch, there
will be an item explaining what Alpha was and why it is sometimes used in
the context of "an architecture faster than any you can imagine, faster
than any that existed before or since." The Xanadu of computer
architecture. ("Where Alpha, the sacred procesor ran")

(And for IA64, we'll have a reference to one of my favorite poems of all
time, _Ozymandias_ by Percy Bysshe Shelley.)

-Z-


Larry Kilgallen

unread,
Aug 4, 1999, 3:00:00 AM8/4/99
to
In article <37A87006...@igs.net>, Paul DeMone <pde...@igs.net> writes:

> Del Cecchi wrote:
> [snip]


>> Is it some kind of natural law that every thread on comp.arch, except maybe the
>> nintendo ones, ends up talking about alpha?

> So everyone now, lets try real hard to generate some Alpha-free


> content for Del; apparently he's on doctors orders to avoid
> aggravating his blood pressure :)

Problem solved ! I have submitted the newsgroup to some folks
who are ready and willing to tell us how to:

MAKE MONEY FAST !!!

(I don't feel too guilty about this non-technical post, since it will
probably get filtered out by SPAM filters for a lot of you :-).

Larry Kilgallen

amoli...@visi-dot-com.com

unread,
Aug 4, 1999, 3:00:00 AM8/4/99
to
In article <1999Aug4.155958.1@eisner>,
Larry Kilgallen <Kilg...@eisner.decus.org.nospam> wrote:
> MAKE MONEY FAST !!!

RED THIS CAREFULLLY!!1!

SEND PHIVE ALPHA PROCESSORS TO EVERYONE ON THE LISTAND ADD
YR NAME TO THE BOTTOM OF IT!!! AFTER 5 WEEX U WILL HAVE 1
TRILLYM ALPHA PROCESSOTS WHICH U CAN SELL! REMEMBER YOU ARE
SELLING A SERVICE THE ALPHAPROCESSOR DISPOSAL SERVUICE!
THIS IS LEGUL AND IT WORX I MADE $500,00 LAST MONTH!

Del Cecchi
Del Cecchi
Del Cecchi
Del Cecchi
Andrew Molitor

Zalman Stern

unread,
Aug 4, 1999, 3:00:00 AM8/4/99
to
amoli...@visi-dot-com.com wrote:
: TRILLYM ALPHA PROCESSOTS

Trillium Alpha Processors? Holey Wafer Scale Integration Batman!

-Z-

Aaron Spink

unread,
Aug 4, 1999, 3:00:00 AM8/4/99
to
cec...@signa.rchland.ibm.com (Del Cecchi) writes:

>
> Is it some kind of natural law that every thread on comp.arch, except maybe the
> nintendo ones, ends up talking about alpha?
>

Yes. :)

aaron spink
not speaking for compaq

M. Ranjit Mathews

unread,
Aug 4, 1999, 3:00:00 AM8/4/99
to
Zalman Stern wrote:

> 200 years from now when someone finally writes a FAQ for comp.arch, there
> will be an item explaining what Alpha was and why it is sometimes used in
> the context of "an architecture faster than any you can imagine, faster
> than any that existed before or since." The Xanadu of computer
> architecture. ("Where Alpha, the sacred procesor ran")

... down to the sunless sea:-)

David Lau

unread,
Aug 4, 1999, 3:00:00 AM8/4/99
to
In article <7o9e4b$tea$1...@news.rchland.ibm.com>,

dce...@vnet.ibm.com wrote:
> Is it some kind of natural law that every thread on comp.arch, except
maybe the
> nintendo ones, ends up talking about alpha?
> --

Actually, I wish there were more threads on what makes Alpha fast and
how/if it has changed the way the rest of the industry implements their
designs. I agreed that notes whose contents are "Alphas are fast!"
aren't too interesting.

Too bad those in the know don't post more notes on the following:

a) in-house CAD tools which allow successful full custom design
with different types of dynamic circuits
b) A mind-set which believes synthesis/standard cells/automated
P&R tools are just not good enough for really high-speed design.
c) An environment where most designers have been there for many years
honing their skills instead of job-hopping after every project.
An environment where a designer of 5 years of experience is
still considered junior instead of a possible chip-leader.

Most of these factors are quite alien to other design groups.
Notice that I haven't listed architecture as a major factor.

dl

--
Usenet: Where the truely clueless can learn from
the profoundly ignorant.
Hey Buddy, it's only my opinion!


Sent via Deja.com http://www.deja.com/
Share what you know. Learn what you don't.

Hank Oredson

unread,
Aug 4, 1999, 3:00:00 AM8/4/99
to

Zalman Stern <zal...@netcom15.netcom.com> wrote in message
news:7oa82p$7...@dfw-ixnews16.ix.netcom.com...

I love it.
When asked why I read comp.arch my response is:

1. The humor.
2. Investment ideas.
3. Some great science.

... in that order ...

--

... Hank

http://horedson.att.net


Paul DeMone

unread,
Aug 4, 1999, 3:00:00 AM8/4/99
to

David Lau wrote:
>
> In article <7o9e4b$tea$1...@news.rchland.ibm.com>,
> dce...@vnet.ibm.com wrote:
> > Is it some kind of natural law that every thread on comp.arch, except
> maybe the
> > nintendo ones, ends up talking about alpha?
> > --
>
> Actually, I wish there were more threads on what makes Alpha fast and
> how/if it has changed the way the rest of the industry implements their
> designs. I agreed that notes whose contents are "Alphas are fast!"
> aren't too interesting.
>
> Too bad those in the know don't post more notes on the following:
>
> a) in-house CAD tools which allow successful full custom design
> with different types of dynamic circuits
> b) A mind-set which believes synthesis/standard cells/automated
> P&R tools are just not good enough for really high-speed design.
> c) An environment where most designers have been there for many years
> honing their skills instead of job-hopping after every project.
> An environment where a designer of 5 years of experience is
> still considered junior instead of a possible chip-leader.
>
> Most of these factors are quite alien to other design groups.
> Notice that I haven't listed architecture as a major factor.

As far as architecture goes the most important thing about
Alpha is it doesn't tend to get in the way. IMHO the neat
thing about each generation of Alpha core is the way the
microarchitecture and the circuit design/layout were appar-
ently carefully codeveloped in harmony rather than the
industry norm of the microarchitects doing their thing
honing IPCs and then throwing the mess over the wall to
the circuit and layout guys (did someone say merced?).

There is a lot of material published about the circuit
design techniques and tools used in each generation of
Alpha. For example, each of the '064, '164, and '264
three major generations used different flip-flop designs
and clock distribution methods. Here is an Alpha reading
list with bias towards the circuit and chip design side
of things (with a couple of Intel-centric biz analyst
viewpoints thrown in for comic relief):

1) R. Comerford, "How DEC developed Alpha", IEEE Spectrum
Vol 29, No 7, Jul 1992 p.26

2) D.W. Dobberpuhl et al, "A 200-MHz 64-b Dual-Issue CMOS
Microprocessor", IEEE JSSC Vol 27 No 11, Nov 1992

3) B.J. Benschneider et al, "A 300-MHz 64-b Quad-Issue CMOS
RISC Microprocessor", IEEE JSSC Vol 30 No 11, Nov 1995

4) L. Gwennap, "Digital 21264 Sets New Standard", Micro-
processor Report Vol 10 No 14, Oct 28, 1996 p.11

5) P.E. Gronowski et al, "A 433-MHz 64-b Quad-Issue RISC
Microprocessor", IEEE JSSC Vol 31 No11, Nov 1996

6) P.C. Judge, "DIGITAL's Struggle to Save its Alpha Chip",
Business Week, Dec 30, 1996

7) A.K. Jain et al, "1.38 cm2 550 MHz Microprocessor with
Multimedia Extensions", ISSCC97, Feb 7, 1997, p.174

8) B.A. Gieseke et al,"A 600MHz Superscalar RISC Micro-
processor with Out-Of-Order Execution", ISSCC97, Feb 7,
1997, p. 176

9) P.C. Judge et al, "Why the Fastest Chip Didn't Win"
Business Week, April 28, 1997, p.92

10) J.A. Farrell and T.C. Fischer, "Issue Logic for a 600
MHz Out-Of-Order Execution Microprocessor", 1997 Sympos-
ium on VLSI Circuits Digest, p.11

11) P. Gronowski, "Designing High Performance Microprocessors",
1997 Symposium on VLSI Circuits Digest, p.51

12) D. A. Carlson et al, "Multimedia Extensions for a 550 MHz
RISC Microprocessor", IEEE JSSC Vol 32 No 11, Nov 1997

13) T. Fischer and D. Leibholz, "Design Tradeoffs in Stall-
Control Circuits for 600 MHz Instruction Queues",
ISSCC98, Feb 6, 1998 p.232

14) V. von Kaenel et al, "A 600 MHz CMOS PLL Microprocessor
Clock Generator with a 1.2 GHz VCO", ISSCC98, Feb 7,
1998, p.396

15) H. Fair and D. Bailey, "Clocking Design and Analysis for
a 600 MHz Alpha Microprocessor", ISSCC98, Feb 7, 1998
p. 398

16) D. Carlson et al, "A 667MHz RISC Microprocessor Con-
taining a 6.0ns 64b Integer Multiplier", ISSCC98,
Feb 7, 1998, p.294

17) P.E. Gronowski et al, "High-Performance Microprocessor
Design", IEEE JSSC, Vol 33 No 5, May 1998 p.676

18) J.A. Farrell and T.C. Fischer, "Issue Logic for a 600
MHz Out-Of-Order Execution Microprocessor", IEEE JSSC
Vol 33 No 5, May 1998 p.707

19) L. Gwennap, "Alpha 21364 to Ease Memory Bottleneck",
Microprocessor Report, Vol 12, No 14, Oct 1998, p.12

20) D.W. Bailey and B.J. Benschneider, "Clocking Design and
Analysis for a 600 MHz Alpha Microprocessor", IEEE JSSC
Vol 33 No 11, Nov 1998 p.1627


HP PA-RISC designers occasionally write a paper on their designs
and design techniques, tools etc, but mostly in their internal
technical house rags. On the whole I would say that HP seems
more secretive, which is a shame.


All opinions strictly my own.
--
Paul W. DeMone The 801 experiment SPARCed an ARMs race of EPIC
Kanata, Ontario proportions to put more PRECISION and POWER into

dem...@mosaid.com architectures with MIPSed results but ALPHA's well
pde...@igs.net that ends well.

Del Cecchi

unread,
Aug 4, 1999, 3:00:00 AM8/4/99
to
Pete Zaitcev wrote:
>
> > Oops I said the scarlet "A" word again, so sorry. Would you rather we
> > rehash the pros and cons of the U.S. library system again?
>
> Paul, tell us something really nasty about SPARC in the IBM process.
>
> --Pete

Those snakes are making sparcs too? damn.

:-)

del cecchi

Pete Zaitcev

unread,
Aug 5, 1999, 3:00:00 AM8/5/99
to
>Is it some kind of natural law that every thread on comp.arch, except maybe the
>nintendo ones, ends up talking about alpha?
>--

>Del Cecchi
>cecchi@rchland

Not only here, read Slashdot.

But honestly, it is educating. Before I stormed into comp.arch to
clash with our local clown over the dead body of Elbrus I was
sure that Aplha is a bad joke. Now I think that Alpha is a very
good and very expensive joke. I wish I had one in my home zoo
but alas everything better than a 166MHz 21064 is beyond my means.

--Pete

Pete Zaitcev

unread,
Aug 5, 1999, 3:00:00 AM8/5/99
to

David Lau

unread,
Aug 5, 1999, 3:00:00 AM8/5/99
to
In article <37A8EADB...@igs.net>,

Paul DeMone <pde...@igs.net> wrote:
> As far as architecture goes the most important thing about
> Alpha is it doesn't tend to get in the way. IMHO the neat

Yes, that's true. But for the most part, the cleanness of the
current Alpha architecture helps in implementing something with less
bugs rather then helping with the frequency of the device.

Most of the controversial decisions made early on for frequency
(and made Alpha unique among architectures) have been reversed or have
been proven unnecessary:
a) no ld/store instructions smaller then longwords- made device
drivers too hard to write, so '164A implemented byte ld/stores.
b) imprecise FP exceptions - reorder buffers and other mechanisms
make precise exceptions still quite do-able.
c) somewhat incomplete IEEE FP implementation,
eg. lack of IEEE exception enables/rounding modes
- each chip generation implements more and more of the IEEE spec.

> There is a lot of material published about the circuit
> design techniques and tools used in each generation of

I was complaining about the lack of threads/appreciation about this
stuff on comp.arch, not the lack of published material.
Nice bibliography though!

Rob Young

unread,
Aug 5, 1999, 3:00:00 AM8/5/99
to
In article <7oa0o7$4...@dfw-ixnews12.ix.netcom.com>, Zalman Stern <zal...@netcom15.netcom.com> writes:
>
> 200 years from now when someone finally writes a FAQ for comp.arch, there
> will be an item explaining what Alpha was and why it is sometimes used in
> the context of "an architecture faster than any you can imagine, faster
> than any that existed before or since." The Xanadu of computer
> architecture. ("Where Alpha, the sacred procesor ran")
>
> (And for IA64, we'll have a reference to one of my favorite poems of all
> time, _Ozymandias_ by Percy Bysshe Shelley.)
>
> -Z-

Interesting.. speaking of which, what ever happened to
Fred True? He hasn't posted here in over 2 years.

For the less informed.. here is a chunk of
the poem:

I met a traveller from an antique land
Who said: Two vast and trunkless legs of stone
Stand in the desert ... Near them, on the sand,
Half sunk, a shattered visage lies, whose frown,
And wrinkled lip, and sneer of cold command,
Tell that the sculptor well those passions read
Which yet survive, stamped on those lifeless things,
The hand that mocked them, and the heart that fed:
And on the pedestal these words appear:
"My name is Ozymandias, king of kings:
Look on my works, ye Mighty, and despair!"
Nothing besides remains. Round the decay
Of that colossal wreck, boundless and bare
The lone and level sands stretch far away.

--Percy Bysshe Shelley, Ozymandias

Speaking of shattered visages ... a great book is:

A Shattered Visage
The Real Face of Atheism
-- Ravi Zacharias

ISBN 0-8010-9938-2

By the way, IA64 does have a chance at success eventually.

Deerfield in 2003 promises low-cost parts allowing for
affordable 64-bit desktops. Someday we will be able to
afford 64-bit Intel boxes... until then we will have to
settle for the "A"(1) platform.

Rob

(1) First letter of Greek alphabet, also: "I am the _ _ _ _ _ and the Omega,
the beginning and the end."

Zalman Stern

unread,
Aug 5, 1999, 3:00:00 AM8/5/99
to
Rob Young <you...@eisner.decus.org> wrote:
: By the way, IA64 does have a chance at success eventually.

Me thinks _Ozymandias_ had his day too, but his kingdom eventually drowned
in a sea of silicon anyway...

-Z-

Torben AEgidius Mogensen

unread,
Aug 5, 1999, 3:00:00 AM8/5/99
to
Zalman Stern <zal...@netcom15.netcom.com> writes:

>(And for IA64, we'll have a reference to one of my favorite poems of all
>time, _Ozymandias_ by Percy Bysshe Shelley.)

You mean

Nothing beside remains. Round the decay

Of that colossal wreck, boundless and bare
The lone and level sands stretch far away.

?

Torben Mogensen (tor...@diku.dk)

Dave Cherkus

unread,
Aug 5, 1999, 3:00:00 AM8/5/99
to
David Lau (l...@qedinc.com) wrote:
:
: Actually, I wish there were more threads on what makes Alpha fast and

: how/if it has changed the way the rest of the industry implements their
: designs. I agreed that notes whose contents are "Alphas are fast!"
: aren't too interesting.
:
: Too bad those in the know don't post more notes on the following:
:
: a) in-house CAD tools which allow successful full custom design
: with different types of dynamic circuits
: b) A mind-set which believes synthesis/standard cells/automated
: P&R tools are just not good enough for really high-speed design.

Too bad indeed. My chats with insiders indicated that PPC suffers from
ignorance of points (a) and (b) above but of course they weren't
willing to state this for the record.

It's still interesting to see that IBM can produce classic, anti-RISC
S/390 CPUs that clock around 575 MHz yet can't produce RISC PPCs much
beyond 450 MHz (both of these numbers are from memory - both may have
changed recently).

Yes, I know megahertz isn't everything, but it is *something*.

: c) An environment where most designers have been there for many years


: honing their skills instead of job-hopping after every project.
: An environment where a designer of 5 years of experience is
: still considered junior instead of a possible chip-leader.

As for (c), it seem a lot of the 'wetware' that produced 21164 and
21264 now works for AMD...

: Usenet: Where the truely clueless can learn from


: the profoundly ignorant.
: Hey Buddy, it's only my opinion!

Indeed.

--
Dave Cherkus ------- UniMaster, Inc. ------ Contract Software Development
Specialties: UNIX Internals/Kernel TCP/IP Alpha Clusters Performance ISDN
Email: che...@UniMaster.COM ------ Oz didn't give anything to the Tinman

Dennis O'Connor

unread,
Aug 5, 1999, 3:00:00 AM8/5/99
to

Torben AEgidius Mogensen <tor...@diku.dk> wrote ...

> Zalman Stern <zal...@netcom15.netcom.com> writes:
> >(And for IA64, we'll have a reference to one of my favorite poems of all
> >time, _Ozymandias_ by Percy Bysshe Shelley.)
>
> You mean
>
> Nothing beside remains. Round the decay
> Of that colossal wreck, boundless and bare
> The lone and level sands stretch far away.

On the other hand. modern railway guage was determined
(ultimately) by the width between the wheels of Roman chariots.

Empires rise and fall, but a ubiquitously-deployed
industry standard can live forever. ;-)
--
Dennis O'Connor
"Speak for ? Speak for ? I don't speak for anyone,
I'm just having fun." -- not quite a quote from "Dr. Who"


Timothy J. Bogart

unread,
Aug 5, 1999, 3:00:00 AM8/5/99
to

In article <7oc4nv$4h6$1...@nnrp02.primenet.com>,
Just when I was going to whine about the S/N, a jewel like this
pops up. Got any references for the chariot-rail connection?

Thanks!

Dave Hansen

unread,
Aug 5, 1999, 3:00:00 AM8/5/99
to
On 5 Aug 1999 14:17:40 GMT, t...@starbase.neosoft.com (Timothy J.
Bogart) wrote:

>
>In article <7oc4nv$4h6$1...@nnrp02.primenet.com>,
>Dennis O'Connor <dm...@primenet.com> wrote:

[...]


>>On the other hand. modern railway guage was determined
>>(ultimately) by the width between the wheels of Roman chariots.
>>
>>Empires rise and fall, but a ubiquitously-deployed
>>industry standard can live forever. ;-)

[...]


>Just when I was going to whine about the S/N, a jewel like this
>pops up. Got any references for the chariot-rail connection?
>

There are several on the web. The most authoritative I could find (in
two minutes) was from the Illinois Central RR site at
http://www.icrr.com/history/

Although they couch it with "It is said..."

If you look harder you may find something better.

Regards,

-=Dave
Just my (10-010) cents
I can barely speak for myself, so I certainly can't speak for B-Tree.
Change is inevitable. Progress is not.

David Lau

unread,
Aug 5, 1999, 3:00:00 AM8/5/99
to
In article <37a9...@News.Destek.net>,

che...@unimaster.com (Dave Cherkus) wrote:
> As for (c), it seem a lot of the 'wetware' that produced 21164 and
> 21264 now works for AMD...
>

Yes, I was hinting that with my previous post. With the diaspora from
the DEC->Compaq/Intel transition, this design style should be making
its way into a bunch of companies including AMD. I guess people didn't
notice the change at Nexgen/AMD.

IBM is changing, seems they have gotten the full custom/high speed
religion. They have published papers on their 1Ghz test chip and are
currently attempting a 1Ghz product.

dl

--


Usenet: Where the truely clueless can learn from
the profoundly ignorant.
Hey Buddy, it's only my opinion!

Douglas Patrone

unread,
Aug 5, 1999, 3:00:00 AM8/5/99
to

Przemek Klosowski

unread,
Aug 5, 1999, 3:00:00 AM8/5/99
to
zai...@bogus.com (Pete Zaitcev) writes:

> good and very expensive joke. I wish I had one in my home zoo
> but alas everything better than a 166MHz 21064 is beyond my means.

Considering that a a 166MHz 21064 (in the form of a Multia) can be had
for free (*), I sympathize. I didn't realize the high cost of living
in Silicon Valley is that bad :^)

(*) actually, you do have to pay shipping---c.f. a recent Slashdot thread:
http://slashdot.org/article.pl?sid=99/08/02/0219235&mode=thread


--
przemek klosowski <prz...@nist.gov> (301) 975-6249
NIST Center for Neutron Research (bldg. 235), E111
National Institute of Standards and Technology
Gaithersburg, MD 20899, USA
.. and for spam extractors, FCC Commisioners' email is:
wken...@fcc.gov,sn...@fcc.gov,pmis...@fcc.gov,mpo...@fcc.gov

Doug Josephson

unread,
Aug 5, 1999, 3:00:00 AM8/5/99
to
Paul DeMone <pde...@igs.net> wrote:
: HP PA-RISC designers occasionally write a paper on their designs

: and design techniques, tools etc, but mostly in their internal
: technical house rags. On the whole I would say that HP seems
: more secretive, which is a shame.

FYI, these HP Journal ("internal technical house rag") articles are
publicly available on the web:

http://www.hp.com/hpj/95apr/apr95.htm (PA-7100LC)
http://www.hp.com/hpj/feb96/feb96.html (PA-7200)
http://www.hp.com/hpj/97jun/jun97.htm (PA-7300LC)
http://www.hp.com/hpj/97aug/aug97.htm (PA-8000)

General PA-RISC uP page with some marketing fluff but also some
technical papers:

http://www.hp.com/ahp/framed/technology/micropro

Doug Josephson d...@fc.hp.com Fort Collins, CO

Paul DeMone

unread,
Aug 5, 1999, 3:00:00 AM8/5/99
to

"Timothy J. Bogart" wrote:
>
> In article <7oc4nv$4h6$1...@nnrp02.primenet.com>,
> Dennis O'Connor <dm...@primenet.com> wrote:

[snip]


> >On the other hand. modern railway guage was determined
> >(ultimately) by the width between the wheels of Roman chariots.
> >
> >Empires rise and fall, but a ubiquitously-deployed
> >industry standard can live forever. ;-)

> >--
> >Dennis O'Connor
> >"Speak for ? Speak for ? I don't speak for anyone,
> > I'm just having fun." -- not quite a quote from "Dr. Who"
> >

> Just when I was going to whine about the S/N, a jewel like this
> pops up. Got any references for the chariot-rail connection?

At last years Microprocessor Forum Nick Tredennick used
the story of rail gages in his satirical awards. He told
how modern rail standards essentially went back to Roman
chariots and the width needed for two horses. The punch
line was something along the lines of how industry standards
like the x86 can invariably be traced back to a couple of
horse's asses.

>
> Thanks!

Pete Zaitcev

unread,
Aug 5, 1999, 3:00:00 AM8/5/99
to
>>Dennis O'Connor <dm...@primenet.com> wrote:
>[...]

>>>On the other hand. modern railway guage was determined
>>>(ultimately) by the width between the wheels of Roman chariots.
>[...]

>>Just when I was going to whine about the S/N, a jewel like this
>>pops up. Got any references for the chariot-rail connection?

>There are several on the web. The most authoritative I could find (in


>two minutes) was from the Illinois Central RR site at
>http://www.icrr.com/history/

Does it explain the difference between European 1430mm gauge
and Russian/American 1520mm?

--Pete

Pete Zaitcev

unread,
Aug 5, 1999, 3:00:00 AM8/5/99
to
Przemek Klosowski <prz...@rrdjazz.nist.gov> writes:
>zai...@bogus.com (Pete Zaitcev) writes:

>> good and very expensive joke. I wish I had one in my home zoo
>> but alas everything better than a 166MHz 21064 is beyond my means.

>Considering that a a 166MHz 21064 (in the form of a Multia) can be had
>for free (*), I sympathize. I didn't realize the high cost of living
>in Silicon Valley is that bad :^)

Lay off Slashdot, ok? I have enough computer junk in my house
to add a Multia on the top.

--Pete

Paul DeMone

unread,
Aug 5, 1999, 3:00:00 AM8/5/99
to

Doug Josephson wrote:
>
> Paul DeMone <pde...@igs.net> wrote:
> : HP PA-RISC designers occasionally write a paper on their designs


> : and design techniques, tools etc, but mostly in their internal
> : technical house rags. On the whole I would say that HP seems
> : more secretive, which is a shame.
>

> FYI, these HP Journal ("internal technical house rag") articles are
> publicly available on the web:
>
> http://www.hp.com/hpj/95apr/apr95.htm (PA-7100LC)
> http://www.hp.com/hpj/feb96/feb96.html (PA-7200)
> http://www.hp.com/hpj/97jun/jun97.htm (PA-7300LC)
> http://www.hp.com/hpj/97aug/aug97.htm (PA-8000)

Yes I have looked at all these. But the info tends towards
the eye candy-ified block diagram level of detail found in
"IntelProcessor Support" and designed to wow customer CIOs.

Lets see some articles with the meat it takes to get into the
red rag (IEEE JSSC). I'd like to see a 4 or 5 page article
describing what it took to get the massive cache arrays in the
PA-8500 to run at over 400 MHz in Intel's 0.25 um process, the
redundancy design trade-offs, soft error concerns etc. This
info is really no more "secret sauce"-ish than the stuff the
Alphas guys published on the EV6 instruction issue circuits.


>
> Doug Josephson d...@fc.hp.com Fort Collins, CO

--

Bill Todd

unread,
Aug 5, 1999, 3:00:00 AM8/5/99
to

Pete Zaitcev <zai...@bogus.com> wrote in message
news:zaitcev.933887501@mallorn...

1520 mm sounds suspiciously close to 5 feet: perhaps for ease of measuring,
or perhaps created by the ancestors of Pontiac's marketing unit. Or perhaps
just to be ornery, and the Russians came on board just in case they ever
built a railroad bridge across the Bering Strait to their territory in
Alaska (actually, lend-lease could have had something to do with it too...).

Bryan O'Sullivan

unread,
Aug 5, 1999, 3:00:00 AM8/5/99
to
"Dennis O'Connor" <dm...@primenet.com> writes:

> On the other hand. modern railway guage was determined
> (ultimately) by the width between the wheels of Roman chariots.

No it wasn't; this is just a popular saw with libertarian-minded
Americans. There is no single standard railway gauge, for one
thing, and within the US, gauges weren't standardised until the
late 19th century.

For what it's worth, you're in good company; I have seen this same
error reported as fact before meetings of the NIST's ongoing (and
probably futile) programme to see the metric system more widely
used within the US.

<b

--
replies to bos .at. serpentine .dot. com

Doug Josephson

unread,
Aug 5, 1999, 3:00:00 AM8/5/99
to
Paul DeMone <pde...@igs.net> wrote:

: Doug Josephson wrote:
:>
:> Paul DeMone <pde...@igs.net> wrote:

:> : HP PA-RISC designers occasionally write a paper on their designs


:> : and design techniques, tools etc, but mostly in their internal
:> : technical house rags. On the whole I would say that HP seems
:> : more secretive, which is a shame.

:>
:> FYI, these HP Journal ("internal technical house rag") articles are

: Yes I have looked at all these. But the info tends towards
: the eye candy-ified block diagram level of detail found in
: "IntelProcessor Support" and designed to wow customer CIOs.

A reasonable assessment. You have to remember that the HP Journal is
geared to the HP engineering population at large, most of which is not
into high end processor design, so things are certainly a bit
"candy-ified". However, I can personally guarantee you that nobody
working on those articles was ever trying to "wow CIOs" :^P

: Paul W. DeMone The 801 experiment SPARCed an ARMs race of EPIC

Allen J. Baum

unread,
Aug 5, 1999, 3:00:00 AM8/5/99
to
In article <37A87006...@igs.net>, Paul DeMone <pde...@igs.net> wrote:

> Lets look ahead and see what's on the agenda. K7 performance is
> disclosed next Monday. At microprocessor forum the microanarchy,
> oops I mean microarchitecture of Merced will be revealed along
> with Sun's new MAJC ISA (another ISA? do they think they are
> Motorola or what?) and a whole bunch more. We should also be
> seeing some interesting stuff come out of Hot Chips (this week
> IIRC).

Ahem. The MAJC paper will be at Hot Chips next week.
( http://www.hotchips.org )

Allen J. Baum

unread,
Aug 5, 1999, 3:00:00 AM8/5/99
to
In article <37A8EADB...@igs.net>, Paul DeMone <pde...@igs.net> wrote:

> There is a lot of material published about the circuit
> design techniques and tools used in each generation of

> Alpha..... Here is an Alpha reading


> list with bias towards the circuit and chip design side
> of things (with a couple of Intel-centric biz analyst
> viewpoints thrown in for comic relief):

For one of the best overviews, read "Building the Alpha Processor"
in the July issue of IEEE Computer magazine.

Del Cecchi

unread,
Aug 5, 1999, 3:00:00 AM8/5/99
to
Paul DeMone wrote:
snip

> Lets see some articles with the meat it takes to get into the
> red rag (IEEE JSSC). I'd like to see a 4 or 5 page article
> describing what it took to get the massive cache arrays in the
> PA-8500 to run at over 400 MHz in Intel's 0.25 um process, the
> redundancy design trade-offs, soft error concerns etc. This
> info is really no more "secret sauce"-ish than the stuff the
> Alphas guys published on the EV6 instruction issue circuits.
>

> --


> Paul W. DeMone The 801 experiment SPARCed an ARMs race of EPIC
> Kanata, Ontario proportions to put more PRECISION and POWER into
> dem...@mosaid.com architectures with MIPSed results but ALPHA's well
> pde...@igs.net that ends well.

And you know that Intel fabs those parts? Has HP said that?

del cecchi

Chris Cox

unread,
Aug 5, 1999, 3:00:00 AM8/5/99
to
In article <7oa0o7$4...@dfw-ixnews12.ix.netcom.com>, Zalman Stern
<zal...@netcom15.netcom.com> wrote:

> Del Cecchi <cec...@signa.rchland.ibm.com> wrote:
> : Is it some kind of natural law that every thread on comp.arch, except


> : maybe the nintendo ones, ends up talking about alpha?
>

> 200 years from now when someone finally writes a FAQ for comp.arch, there
> will be an item explaining what Alpha was and why it is sometimes used in
> the context of "an architecture faster than any you can imagine, faster
> than any that existed before or since." The Xanadu of computer
> architecture. ("Where Alpha, the sacred procesor ran")
>

> (And for IA64, we'll have a reference to one of my favorite poems of all
> time, _Ozymandias_ by Percy Bysshe Shelley.)

Sometimes I'm not even sure it'll get far enough to put up statues...

Chris

Bruce Hoult

unread,
Aug 6, 1999, 3:00:00 AM8/6/99
to
In article <zaitcev.933887501@mallorn>, zai...@bogus.com (Pete Zaitcev) wrote:

> Does it explain the difference between European 1430mm gauge
> and Russian/American 1520mm?

And here in New Zealand the gauge is 1066.8 mm (3' 6").

I have no idea how many other "standard" gauges there are around the
world, but they certainly aren't all the same as Roman chariot wheels.

-- Bruce

Paul DeMone

unread,
Aug 6, 1999, 3:00:00 AM8/6/99
to

Del Cecchi wrote:
[snip]


> And you know that Intel fabs those parts? Has HP said that?

I posted on this maybe six months ago. Look up the process
specs in the HP paper "A 500MHz 64b RISC CPU with 1.5MB On-Chip
Cache" from ISSCC99. Now cross reference that with the Intel
P856 process described in "IC Vendors Prepare for 0.25-Micron
Leap" in Microprocessor report Vol 10, No 12, Sept 16, 1996.

Pay particular attention to the metal min sizes and pitches.
Now if you cannot see the clear match then you probably were
on OJ's jury. :-)

I don't know if either Intel or HP has officially acknowledged
the fab relationship for PA-8500. I also don't know what the
whole cloak and dagger act surrounding who spun PA-8500 wafers
was all about either. HP is a funny company sometimes. Like
why won't they give a power dissipation spec for any of their
CPUs since the PA-7200?

>
> del cecchi

Renu Raman

unread,
Aug 6, 1999, 3:00:00 AM8/6/99
to
In article Paul DeMone <pde...@igs.net> writes:
>
>
> was all about either. HP is a funny company sometimes. Like
> why won't they give a power dissipation spec for any of their
> CPUs since the PA-7200?


Why should I? If I don't sell those chips other than in a box sold
by HP. Why would anybody care (or need to).


--


Ketil Z Malde

unread,
Aug 6, 1999, 3:00:00 AM8/6/99
to
b...@best.com (Bryan O'Sullivan) writes:

> No it wasn't; this is just a popular saw with libertarian-minded
> Americans. There is no single standard railway gauge, for one
> thing, and within the US, gauges weren't standardised until the
> late 19th century.

Well, but with so many "standard" gauges, it would be extremely
unlikely that not one of them would coincide with the Roman Standard
for Chariots. And as for late 19th, well, that's standardization work
for you.

-kzm
--
If I haven't seen further, it is by standing in the footprints of giants

Brian Drummond

unread,
Aug 6, 1999, 3:00:00 AM8/6/99
to
On 5 Aug 1999 16:23:25 -0700, b...@best.com (Bryan O'Sullivan) wrote:

>"Dennis O'Connor" <dm...@primenet.com> writes:
>
>> On the other hand. modern railway guage was determined
>> (ultimately) by the width between the wheels of Roman chariots.
>

>No it wasn't; this is just a popular saw with libertarian-minded
>Americans. There is no single standard railway gauge, for one
>thing, and within the US, gauges weren't standardised until the
>late 19th century.

Or - there is a standard, (4 feet 8.5 inches) but the Americans don't
follow it. But then, the Romans never (to my knowledge) conquered
America or Russia, so why should they?

It's possible that railways weren't used in America until steam came
along. However there were (a few) railways under horse power. I think
they were very short, in mining areas. But there was _something_ for the
first steam locomotive (1803) to run on.



>For what it's worth, you're in good company; I have seen this same
>error reported as fact before meetings of the NIST's ongoing (and
>probably futile) programme to see the metric system more widely
>used within the US.

In a way it's surprising it isn't more widely used - like the United
States, the metric system rose out of an 18thC revolution.

- Brian


Peter Mayne

unread,
Aug 6, 1999, 3:00:00 AM8/6/99
to
Timothy J. Bogart <t...@starbase.neosoft.com> wrote in message
news:82368FFE7896976C.6D7FB4AA...@lp.airnews.net...

>
> Got any references for the chariot-rail connection?

Space shuttles and horses' backsides

The US Standard railroad gauge (distance between the rails) is 4 feet, 8.5
inches.

That's an exceedingly odd number. Why was that gauge used? Because that's
the way they built them in England, and the US railroads were built by
English expatriates.

Why did the English people build them like that? Because the first rail
lines were built by the same people who built the pre-railroad tramways, and
that's the gauge they used.

Why did "they" use that gauge then? Because the people who built the
tramways used the same jigs and tools that they used for building wagons,
which used that wheel spacing.

Okay! Why did the wagons use that odd wheel spacing? Well, if they tried to
use any other spacing the wagons would break on some of the old, long
distance roads, because that's the spacing of the old wheel ruts.

So who built these old rutted roads? The first long distance roads in Europe
were built by Imperial Rome for the benefit of their legions. The Roman
roads have been used ever since. And the ruts? The initial ruts, which
everyone else had to match for fear of destroying their wagons, were first
made by Roman war chariots. Since the chariots were made for or by Imperial
Rome they were all alike in the matter of wheel spacing.

Thus, we have the answer to the original questions. The United States
standard railroad gauge of 4 feet, 8.5 inches derives from the original
specification for an Imperial Roman army war chariot. Specifications and
bureaucracies live forever.

So, the next time you are handed a specification and wonder what horse's ass
came up with it, you may be exactly right. Because the Imperial Roman
chariots were made to be just wide enough to accommodate the back-ends of
two war horses.

Plus, there's an interesting extension of the story about railroad gauge and
horses' behinds. When we see a Space Shuttle sitting on the launch pad,
there are two big booster rockets attached to the sides of the main fuel
tank. These are the solid rocket boosters, or SRBs. The SRBs are made by
Thiokol at a factory in Utah. The engineers who designed the SRBs might have
preferred to make them a bit fatter, but the SRBs had to be shipped by train
from the factory to the launch site. The railroad line to the factory runs
through a tunnel in the mountains. The SRBs had to fit through that tunnel.
The tunnel is slightly wider than a railroad track, and the railroad track
is about as wide as two horses' behinds. So a major design feature of what
is arguably the world's most advanced transportation system was determined
by the width of a horse's backside.

PJDM
----
Peter Mayne, Compaq Computer Australia, Canberra, ACT
These are my opinions, and have nothing to do with Compaq.
"The wise man knows that he knows nothing." - Bill. "That's us, dude!" -
Ted.

Timothy J. Bogart <t...@starbase.neosoft.com> wrote in message
news:82368FFE7896976C.6D7FB4AA...@lp.airnews.net...
>
> In article <7oc4nv$4h6$1...@nnrp02.primenet.com>,


> Dennis O'Connor <dm...@primenet.com> wrote:
> >

> >Torben AEgidius Mogensen <tor...@diku.dk> wrote ...
> >> Zalman Stern <zal...@netcom15.netcom.com> writes:

> >> >(And for IA64, we'll have a reference to one of my favorite poems of
all
> >> >time, _Ozymandias_ by Percy Bysshe Shelley.)
> >>

> >> You mean
> >>
> >> Nothing beside remains. Round the decay
> >> Of that colossal wreck, boundless and bare
> >> The lone and level sands stretch far away.
> >

> >On the other hand. modern railway guage was determined
> >(ultimately) by the width between the wheels of Roman chariots.
> >

> >Empires rise and fall, but a ubiquitously-deployed
> >industry standard can live forever. ;-)
> >--
> >Dennis O'Connor
> >"Speak for ? Speak for ? I don't speak for anyone,
> > I'm just having fun." -- not quite a quote from "Dr. Who"
> >

> Just when I was going to whine about the S/N, a jewel like this
> pops up. Got any references for the chariot-rail connection?
>

> Thanks!
>
>

Angel E. Lozano

unread,
Aug 6, 1999, 3:00:00 AM8/6/99
to
Spain is also 1520 mm gauge

Pete Zaitcev wrote:

> >>Dennis O'Connor <dm...@primenet.com> wrote:

> >[...]


> >>>On the other hand. modern railway guage was determined
> >>>(ultimately) by the width between the wheels of Roman chariots.

> >[...]


> >>Just when I was going to whine about the S/N, a jewel like this
> >>pops up. Got any references for the chariot-rail connection?
>

> >There are several on the web. The most authoritative I could find (in
> >two minutes) was from the Illinois Central RR site at
> >http://www.icrr.com/history/
>

> Does it explain the difference between European 1430mm gauge
> and Russian/American 1520mm?
>

> --Pete

--
===================================
Angel E. Lozano
Polymer Synthesis Group
Department of Chemical Engineering
344 Riddick Hall
Box 7905
North Carolina State University
Raleigh, NC 27695-7905
Work 919-515-7176
Fax 919-515-3465
===================================

Greg Pfister

unread,
Aug 6, 1999, 3:00:00 AM8/6/99
to
Pete Zaitcev wrote:
>
> >>Dennis O'Connor <dm...@primenet.com> wrote:
> >[...]
> >>>On the other hand. modern railway guage was determined
> >>>(ultimately) by the width between the wheels of Roman chariots.
> >[...]
> >>Just when I was going to whine about the S/N, a jewel like this
> >>pops up. Got any references for the chariot-rail connection?
>
> >There are several on the web. The most authoritative I could find (in
> >two minutes) was from the Illinois Central RR site at
> >http://www.icrr.com/history/
>
> Does it explain the difference between European 1430mm gauge
> and Russian/American 1520mm?
>
> --Pete

No, and this alleged connection has been debunked quite
thoroughly, as they are wont to do, by the folks over at
alt.folklore.urban. See
http://www.urbanlegends.com/misc/railroad_gauge.html. High
points:

- The US originally had *many* different guages, not one; that
was, in fact, a significant economic inhibitor until it was
standardized.

- Europe also had many different guages. The 4' 8.5" one came
from Stephenson in northern England, and was originally 4'8"
even, widened later for technical rolling reasons.

- The Romans built smooth roads, not wagon ruts. In fact, that
was one of the differences between Greeks & Romans: Greeks just
made ruts -- a kind of rail system itself. (My addition: Ruts are
great for wagons, hence transporting goods, but the Romans built
their roads to transport troops by foot. Ruts aren't particularly
good for that.)

This is a great shame. It was a *wonderful* story. For those of
you who might like to see a better rendition of it, try
http://www.oerm.mus.ca.us/library/articles/trackgauge.html, which
makes it out to be an example of a Mil Std that has lasted
forever.

Greg Pfister
<not my employers' opinion, although I doubt it's much intersted
in railroad track guages>

Dennis Ritchie

unread,
Aug 6, 1999, 3:00:00 AM8/6/99
to
Greg Pfister wrote:
...

> No, and this alleged connection has been debunked quite
> thoroughly, as they are wont to do, by the folks over at
> alt.folklore.urban. See
> http://www.urbanlegends.com/misc/railroad_gauge.html. High
> points:

Ah well. The Romans standardized Latin too, and look what
happened in France, Spain, Romania, and even Italy.

Dennis

George Herbert

unread,
Aug 6, 1999, 3:00:00 AM8/6/99
to
Warning: this is off topic...

Peter Mayne <Peter...@compaq.com> wrote:
>> Got any references for the chariot-rail connection?
>

>Space shuttles and horses' backsides

>[...]


>Plus, there's an interesting extension of the story about railroad gauge and
>horses' behinds. When we see a Space Shuttle sitting on the launch pad,
>there are two big booster rockets attached to the sides of the main fuel
>tank. These are the solid rocket boosters, or SRBs. The SRBs are made by
>Thiokol at a factory in Utah. The engineers who designed the SRBs might have
>preferred to make them a bit fatter, but the SRBs had to be shipped by train
>from the factory to the launch site. The railroad line to the factory runs
>through a tunnel in the mountains. The SRBs had to fit through that tunnel.
>The tunnel is slightly wider than a railroad track, and the railroad track
>is about as wide as two horses' behinds. So a major design feature of what
>is arguably the world's most advanced transportation system was determined
>by the width of a horse's backside.

Space Shuttle SRBs have never been shipped by rail. Nor any other
very large solid rocket motors; rail travel is too hard on them,
they develop cracks and go BOOM instead of WHOOSH. They're shipped
by barge.


-george william herbert
gher...@crl.com


George Herbert

unread,
Aug 6, 1999, 3:00:00 AM8/6/99
to

I know of at least two non-HP boxes shipping with PA-8x00
CPUs in them.

However, presumably those vendors got the power dissipation
along with all the other info they needed.


-george william herbert
gher...@crl.com


Roger Ivie

unread,
Aug 6, 1999, 3:00:00 AM8/6/99
to
In article <7ofb2v$4...@crl3.crl.com>, George Herbert wrote:
>Space Shuttle SRBs have never been shipped by rail. Nor any other
>very large solid rocket motors; rail travel is too hard on them,
>they develop cracks and go BOOM instead of WHOOSH. They're shipped
>by barge.

Shipping things by barge is quite a trick from Northern Utah. You might
want to take a look at http://www.thiokol.com/RSRMcycl.htm most notably
the picture labelled "shipping".
--
Roger Ivie
TeraGlobal Communications Corporation
1770 North Research Park Way Suite 100
Logan, UT 84341
mailto:ri...@teraglobal.com
phoneto:(435)787-0555
faxto:(435)787-0516


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Angel E. Lozano

unread,
Aug 6, 1999, 3:00:00 AM8/6/99
to
Latin languages started to be spoken 4 hundreds years later, 4 centuries
after the roman empire had fallen.

Is the english a new language or it's coming from any ancient tongue?.
Don't you know that tongues change within time?. English too, or did
Shakespeare speak and write modern english?

Maynard Handley

unread,
Aug 6, 1999, 3:00:00 AM8/6/99
to
In article <7oc4nv$4h6$1...@nnrp02.primenet.com>, "Dennis O'Connor"
<dm...@primenet.com> wrote:

>Torben AEgidius Mogensen <tor...@diku.dk> wrote ...
>> Zalman Stern <zal...@netcom15.netcom.com> writes:
>> >(And for IA64, we'll have a reference to one of my favorite poems of all
>> >time, _Ozymandias_ by Percy Bysshe Shelley.)
>>
>> You mean
>>
>> Nothing beside remains. Round the decay
>> Of that colossal wreck, boundless and bare
>> The lone and level sands stretch far away.
>

>On the other hand. modern railway guage was determined
>(ultimately) by the width between the wheels of Roman chariots.
>

>Empires rise and fall, but a ubiquitously-deployed
>industry standard can live forever. ;-)

So they claim. I find this hard to believe given that the territory
covered by the same Roman empire has a variety of different railway gauges
across it.

Maynard

George Herbert

unread,
Aug 6, 1999, 3:00:00 AM8/6/99
to
Roger Ivie <ri...@teraglobal.com> wrote:
>George Herbert wrote:
>>Space Shuttle SRBs have never been shipped by rail. Nor any other
>>very large solid rocket motors; rail travel is too hard on them,
>>they develop cracks and go BOOM instead of WHOOSH. They're shipped
>>by barge.
>
>Shipping things by barge is quite a trick from Northern Utah. You might
>want to take a look at http://www.thiokol.com/RSRMcycl.htm most notably
>the picture labelled "shipping".

Most interesting... they built a factory in the South to build them
down there at one point, explicitly to avoid such rail shipping,
but it appears that it's changed (or that the factory was never used).


-george


Paul DeMone

unread,
Aug 6, 1999, 3:00:00 AM8/6/99
to

Renu Raman wrote:
>
> In article Paul DeMone <pde...@igs.net> writes:
> >
> >
> > was all about either. HP is a funny company sometimes. Like
> > why won't they give a power dissipation spec for any of their
> > CPUs since the PA-7200?
>
> Why should I? If I don't sell those chips other than in a box sold
> by HP. Why would anybody care (or need to).

They disclosed the die size, number or transistors, and dozens
of facts of interest only to chip heads. These facts weren't
required to be public either. The arbitrariness of what HP
discloses and doesn't disclose (power specs, official admission
of fab relationship with Intel, etc) strikes me as odd.

As far as an employee of Sun providing those power numbers,
I wouldn't expect that so feel free to go back to lurking. :)

>
> --

Bruce Hoult

unread,
Aug 7, 1999, 3:00:00 AM8/7/99
to
In article <7oe3sg$9...@usenet.pa.dec.com>, "Peter Mayne"
<Peter...@compaq.com> wrote:

> Timothy J. Bogart <t...@starbase.neosoft.com> wrote in message
> news:82368FFE7896976C.6D7FB4AA...@lp.airnews.net...
> >

> > Got any references for the chariot-rail connection?
>
> Space shuttles and horses' backsides

The least you could have done is credit "Connections".

-- Bruce

Sander Vesik

unread,
Aug 8, 1999, 3:00:00 AM8/8/99
to
In comp.arch "Dennis O'Connor" <dm...@primenet.com> wrote:

> Torben AEgidius Mogensen <tor...@diku.dk> wrote ...
> > Zalman Stern <zal...@netcom15.netcom.com> writes:
> > >(And for IA64, we'll have a reference to one of my favorite poems of all
> > >time, _Ozymandias_ by Percy Bysshe Shelley.)
> >
> > You mean
> >
> > Nothing beside remains. Round the decay
> > Of that colossal wreck, boundless and bare
> > The lone and level sands stretch far away.

> On the other hand. modern railway guage was determined
> (ultimately) by the width between the wheels of Roman chariots.

Roman charriots?

That means implying that Romans set the width of their chariots.
And that ain't so.

> Empires rise and fall, but a ubiquitously-deployed
> industry standard can live forever. ;-)

> --
> Dennis O'Connor
> "Speak for ? Speak for ? I don't speak for anyone,
> I'm just having fun." -- not quite a quote from "Dr. Who"

--
Sander

There is no love, no good, no happiness and no future -
all these are just illusions.

Peter Mayne

unread,
Aug 9, 1999, 3:00:00 AM8/9/99
to
I posted what I had. If there were any credits on it, I would have posted
those as well.

PJDM
----
Peter Mayne, Compaq Computer Australia, Canberra, ACT
These are my opinions, and have nothing to do with Compaq.
"The wise man knows that he knows nothing." - Bill. "That's us, dude!" -
Ted.

Bruce Hoult <bruce...@pobox.com> wrote in message
news:brucehoult-07...@bruce.bgh...

Maynard Handley

unread,
Aug 9, 1999, 3:00:00 AM8/9/99
to
In article <37AB365B...@unity.ncsu.edu>, "Angel E. Lozano"
<alo...@unity.ncsu.edu> wrote:

>Latin languages started to be spoken 4 hundreds years later, 4 centuries
>after the roman empire had fallen.
>
>Is the english a new language or it's coming from any ancient tongue?.
>Don't you know that tongues change within time?. English too, or did
>Shakespeare speak and write modern english?

Perhaps Dennis was too subtle. I believe his point was more one of
throwing up his hands in despair at the fact that, no matter what is
standardized, human beings will circumvent the standardization.
(One suspects this is something with which Dennis has first hand experience.)

Maynard

Mike Albaugh

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Aug 9, 1999, 3:00:00 AM8/9/99
to
Angel E. Lozano (alo...@unity.ncsu.edu) wrote:
: Spain is also 1520 mm gauge

: Pete Zaitcev wrote:

: >
: > Does it explain the difference between European 1430mm gauge
: > and Russian/American 1520mm?

Dunno about Spain, but a plausible explanation for Russia
is that when the South lost "The War Betweeen the States" (whereupon
it became known as the "American Civil War", which was essentially
_the_ point :-), a fair number of middle- and upper-class Southerners
left the country, including quite a few civil and railroad engineers.
About this time, Russia was embarking on a modernization program,
including a fair bit of railroad construction, and many of these
ex-pats found work there. Southern U.S. Railroads tended to be
5-foot gauge,... (Haveing an odd gauge was very helpful to the
Russians in WWII, when they could pull their equipment back with
them as they retreated, and not have to worry so much about the
German army using their rails to supply the invasion force. This
should gibe pause to those who favor the software monoculture
into which the U.S. is headed so swiftly :-)

The above is from memory, a bit old, but fits pretty well
with what I recall. The U.S. did not "standardize" on the "Roman
Chariot" gauge until later. Or perhaps "never", as there are still
narrow gauge (2, 3, and 3.5-foot) railroads in service in the US
(OK, the 2-footer is a tourist line... :-) Also Peru and Australia,
IIRC. The first mention of the "Roman Chariot" description I ever
saw was due to Isambard Kingdom Brunel, who was a major promoter
of broad-gauge in the U.K., so it may have been a marketting ploy
even then.

Meanwhile, in another part of this thread someone mentions
that the Metric system was introduced as part of an 18th century
revolution, and that is true, but neglects to mention that the
same fine folks who gave us that system also promoted a "decimal
time" system, (since abandoned) including making it a (capital?)
crime to use the old scheme. That sort of "Standard setting by
threat" may have had some part in the U.S. rejection... :-)

Mike
(who buys beer by the liter and milk by the gallon :-)

Larry Elmore

unread,
Aug 10, 1999, 3:00:00 AM8/10/99
to
Bill Todd <bill...@foo.mv.com> wrote in message
news:7od0k7$4b4$1...@pyrite.mv.net...
>
> Pete Zaitcev <zai...@bogus.com> wrote in message
> news:zaitcev.933887501@mallorn...

> > >>Dennis O'Connor <dm...@primenet.com> wrote:
> > >[...]

> > >>>On the other hand. modern railway guage was determined
> > >>>(ultimately) by the width between the wheels of Roman chariots.
> > >[...]
> > >>Just when I was going to whine about the S/N, a jewel like this
> > >>pops up. Got any references for the chariot-rail connection?
> >
> > >There are several on the web. The most authoritative I could find (in
> > >two minutes) was from the Illinois Central RR site at
> > >http://www.icrr.com/history/
> >
> > Does it explain the difference between European 1430mm gauge
> > and Russian/American 1520mm?
> >
> > --Pete
>
> 1520 mm sounds suspiciously close to 5 feet: perhaps for ease of
measuring,
> or perhaps created by the ancestors of Pontiac's marketing unit. Or
perhaps
> just to be ornery, and the Russians came on board just in case they ever
> built a railroad bridge across the Bering Strait to their territory in
> Alaska (actually, lend-lease could have had something to do with it
too...).

There's been a number of railroad gauges in use in the world at various
times. There's still a couple of narrow-gauge lines in the U.S. (if you're
ever in the Durango, Colorado area, _don't_ miss taking a day trip to and
from Silverton on the restored (coal-fired steam) Denver & Rio Grande
Railroad).

Among other reasons, the Russians chose a gauge different from that of her
principle land enemy, Germany, in order to complicate the supply problems of
an invading army. I suppose things might be different now, but I know France
also used a different gauge track than Germany. In 1870, at least, quite a
few German railway troops were employed in re-laying track as fast as they
could behind advancing German armies. German supply problems in Russia
during both World Wars were aggravated by the differences in track gauge and
rolling stock.

Larry

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