I have a doubt

[Dayananda]

Dear sir,
I have a doubt,
Can we use recursive functions in vhdl, for example for finding the
factorial of a number, can we call factorial<=fact(n); where the
function is written as
variable x:integer;
if n=0 then
return '1';
else
n<=n*(fact(n-1));
return n;
end if;

[Vijayvithal Jahagirdar]

daya...@yahoo.com (Dayananda) writes:

> Dear sir,
> I have a doubt,

> Can we use recursive functions in vhdl, ;
and how do you intend to synthesize it?

--
- XEROX never comes up with something original
Jahagirdar .V.S
IC Design Engineer , Texas Instruments (India) Ltd.
Ph (91)080-5099129(O)

[Marius Vollmer]

daya...@yahoo.com (Dayananda) writes:

> Can we use recursive functions in vhdl,

Yes. (Just try it!)

[Ray Andraka]

Yes, and recursive implementations can be synthesizable too, although
some of the tool vendors may think otherwise.

Vijayvithal Jahagirdar wrote:

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email r...@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

[Vijayvithal Jahagirdar]

Ray Andraka <r...@andraka.com> writes:

> Yes, and recursive implementations can be synthesizable too, although
> some of the tool vendors may think otherwise.
>

Are there any examples of synthesizable recursive functions available on
the net that I can look up?
Regards
Jags

--

[Srinivasan Venkataramanan]

Hi Jags,
Search on groups.google.com for "recursive function" (in VHDL
NG, of-course), here is what I found for LOG2

One example could be:

http://groups.google.com/groups?hl=en&selm=38E06F71.79E6CFFE%40Alcatel
.Be

---- Previous post from Jos ----

there's an elegant solution to it
by describing the log2 function recursive (no syntax):

log2(N) : if N=1 then return 0 else return 1+log2(N/2)

The reason is that this is for synthesis unrolled at
analysis time. So the function is expanded with concrete
numbers for N. And so it works as no further calculations
(others than SomeConstant+SomeConstant) are involved.

-----

HTH,
Srinivasan

--
Srinivasan Venkataramanan
ASIC Design Engineer
Software & Silicon Systems India Pvt. Ltd. (An Intel company)
Bangalore, India, Visit: http://www.simputer.org)

"Vijayvithal Jahagirdar" <a7c3eys...@sneakemail.comMONSENSE>
wrote in message news:p6xpu82...@dspsparc147.india.ti.com...

[Alexander Kobler]

Hi!

Have a look at Peter J. Ashenden's article "Recursive and repetitive VHDL
modelling". He describes how to instantiate components in a recursive way. It's
available at http://tech-www.informatik.uni-hamburg.de/vhdl/#DOCUMENTATION-LIST

Alex
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[Volker Hetzer]

I've tried stuff like that. Synopsys at the time could unroll recursion
as long as the depth was a) determinable at compile time and b) less
than 32.

Greetings!
Volker
--
Das meiste Geld habe ich fuer exklusive Restaurants, schnelle Autos und
teure Frauen ausgegeben. Den Rest habe ich verplempert.

[Ray Andraka]

A while back John McCluskey had a page up that had some examples that IIRC
generated trees for large AND gates recursively. THey worked with both
simplify and leonardo. Neither knew the depth of the tree (and hence the
number of recursions) ahead of time. I've done adder trees, barrel shifts
and a few other things. THese recurse using component instantiations rather
than using a function. Where I have had problems in the past, at least with
synplicity, is when each layer has std_logic-vectors as input that are not a
fixed width for all layers, such as what you get with an adder tree. The
adder tree I had trouble with simulated fine under both ALdec and Modelsim,
synthesized ok with leonardo, but got tripped up in synplicity. This was an
old version of synplicity, so it may be fixed now.

Vijayvithal Jahagirdar wrote:

--