WPRECIT values for 8KHA+
Ian
8KHA+ using WPCREDIT ?
Ta
Claus Witte
| Anyone know the Hex location and value to enable cpu cooling on an Epox
| 8KHA+ using WPCREDIT ?
As I remember the offset is 46 and you need to set bit 4 and 5.
That works fine on a Thunderbird 1,33 GHz on an KT133-board, but
on my EPOX 8KHA+ the CPU (XP 1700+) doesn't cool down.
Do you have the plugins for the KT266A ?
Regards
Claus
--
"He who is certain he knows the ending of things when he is only
beginning them is either extremely wise or extremely foolish; no
matter which is true, he is certainly an unhappy man, for he has
put a knife in the heart of wonder." (Tad Williams)
Bernhard Haim
Try to set register "92" to "E9" to enable the CPU idle-mode!
I've tested this setting using WPCREDIT and WPCRSET with an Epox EP-8KHA
and EP-8KHA+ (but I think it should work on every mainboard with a VIA
KT-266(A) chipset).
The average idle-temp of my CPU dropped about 8°C.
Bernhard
Susan
degrees and is now within 1 degree of case temp.
Does this do the same thing as the old Rain and Waterfall HLT utilities?
--
Susan
If it's to be it's up to me.
"Bernhard Haim" <mechat...@gmx.at> wrote in message
news:3C0158F1...@gmx.at...
Claus Witte
| Try to set register "92" to "E9" to enable the CPU idle-mode!
| I've tested this setting using WPCREDIT and WPCRSET with an Epox EP-8KHA
| and EP-8KHA+ (but I think it should work on every mainboard with a VIA
| KT-266(A) chipset).
| The average idle-temp of my CPU dropped about 8°C.
Hi Bernhard,
thanks for the tip - it works fine for me.
The average idle temp. of my CPU dropped about 9°C.
One question: I'm using the PCR-files for the KT266 chip, because I was
not able to find some for the KT266A chip inthe internet. Do you know
if there are any newer files available (somewhere) ?
Many thanks
Claus
Bernhard Haim
has the same effect as using a "cooling-utility".
It's just not so simple to setup and use.
Bernhard
Bernhard Haim
find one, that has the "cooling bit" documented at register 92...) it
should work just fine with the KT266A as -I think- the register settings
are not different.
Bernhard
P.S.: I've found the right "cooling-bit" for the KT266/A by looking
carefully at the register settings.
The old cooling trick that worked for the KT133/A -setting bit 7 at
register 52 to "1"- didn't work anymore, because register 52 cannot be
changed. When you look at the WPCREDIT program-screen (using a KT266/A
mainboard) you will notice that register 50-53 look identical to 90-93.
So I thought they could be "mirrored". I set register 92 (from "69") to
"E9" and register 52 was set to "E9" automatically.
Result: the cpu idle-mode worked! :-)
B Johnson
down 10C. Not bad. I've used wcprset to make this setting permenant. 8KHA+
w/ XP 1600 + OC'd to 1600mhz.news:3C040607...@gmx.at...
Bernhard Haim
has the cooling-bit description at register 92).
Here's the the link: http://www.vr-zone.com/downloads/kt266_pcr.zip
Bernhard
User wrote:
>
> Can you point us to where we can find these PCR files please . Since It's such a
> small file would it be so much trouble to post it here ?
Bernhard Haim
User wrote:
>
> Thank you Bernhard , I was able to load that file 11063099.pcr but after modified the
> data bit to read E9 (11101001) and used the SET command , my computer reboot . Unsure
> if it's a "good written" KT266 file , I then use WPCRSET as "quick fix" , in
> "register" I entered "92" in "data" I entered "E9" then reboot , but then my computer
> kept rebooting itself . Did I do something wrong ?
>
> My specs:
>
> Epox 8KHA+
> Tbird 1.4 running 1.5 @ 140x11
> vcore=1.8
> CPU=47 , Case=41
Claus Witte
Copy all lines between <---BEGIN> and <---END> and save them
to a file called "11063099.pcr" in your WPCREDIT directory.
<---BEGIN--->
PCR(PCI Configration Registers) Editor / WPCREDIT for WIN32
Copyright (c) 2000 H.Oda!
[COMMENT]=for viahardware.com
[MODEL]=VT8366 (KT266) Athlon NB
[VID]=1106:VIA
[DID]=3099:Host to PCI Bridge
(00)=Vendor Identification
(01)=Vendor Identification
(02)=Device Identification
(03)=Device Identification
(04:7)=Address / Data Stepping 0:no 1=yes
[04:6]=Parity Error Response 0:ignore 1=normal
(04:5)=VGA Palette Snoop 0:tradit'l 1=per-ISA-card comp
(04:4)=Mem Write/Invalidate Cmd 0:BMs must 1=BMs may gen MW,Inv
(04:3)=Special Cycle Monitoring 0=enable 1=disable
(04:2)=PCI Bus Master 0=never 1=can (default)
(04:1)=Memory Space 0=no 1=yes responds
(04:0)=I/O Space 0=no 1=yes responds
[05:7]=(Reserved)
[05:6]=(Reserved)
[05:5]=(Reserved)
[05:4]=(Reserved)
[05:3]=(Reserved)
[05:2]=(Reserved)
(05:1)=Fast Back-to-Back Cycle 0:same 1=different
(05:0)=SERR# Enable 0:disabled 1=enabled
[06:7]=Fast Back-to-Back Capablealways reads 0
[06:6]=User Definable Features always reads 0
[06:5]=66MHz Capable always reads 0
[06:4]=Supports New Capability always reads 1
[06:3]=(Reserved)
[06:2]=(Reserved)
[06:1]=(Reserved)
[06:0]=(Reserved)
[07:7]=Detected Parity Error 0=no error 1=error
[07:6]=Signaled System Error always reads 0
[07:5]=Signaled Master Abort 0=no abort 1=aborted
[07:4]=Received Target Abort 0=no abort 1=aborted
[07:3]=Signaled Target Abort 0=never signaled
[07:2]=DEVSEL# Timing 10=slow 11=reserved
[07:1]=00=fast 01=medium
[07:0]=Data Parity Error 0=no 1=error
(08)=Revision ID, 0x = KT266, 8x=KT266A?
(09)=Programming Interface always reads 00
(0A)=Sub Class Code 00 indicates Host Bridge
(0B)=Base Class Code 06 indicates Bridge Device
(0C)=(Reserved)
[0D:7]=Guaranteed Time Slice in PCI bus clocks
[0D:6]=(Same as bit7)
[0D:5]=(Same as bit7)
[0D:4]=(Same as bit7)
[0D:3]=(Same as bit7)
[0D:2]=(Reserved), always reads 0, read at (75:5)
[0D:1]=(Reserved), always reads 0, read at (75:4)
[0D:0]=(Reserved) always reads 0
(0E)=Header Type Code, reads 00: single function
(0F:7)=BIST Supported 0=no supported
(0F:6)=(Reserved) always reads 0
(0F:5)=(Reserved) always reads 0
(0F:4)=(Reserved) always reads 0
(0F:3)=(Reserved) always reads 0
(0F:2)=(Reserved) always reads 0
(0F:1)=(Reserved) always reads 0
(0F:0)=(Reserved) always reads 0
[10]=(Reserved)
[11]=(Reserved)
[13:7]=Upper Prog. Base Adr default=0
[13:6]=(Same as bit7)
[13:5]=(Same as bit7)
[13:4]=(Same as bit7)
[13:3]=Lower Prog. Base Adr(4-7)Bit 7 6 5 4 3 2 1 0
[13:2]=. X X X 0 0 0 0 0 32M . X X 0 0 0 0 0 0 64M
[13:1]=. X 0 0 0 0 0 0 0 128M . 0 0 0 0 0 0 0 0 256M
[13:0]=
[12:7]=Lower Prog. Base Adr(0-3)Bit 7 6 5 4 3 2 1 0
[12:6]=. X X X X X X X X 1M . X X X X X X X 0 2M
[12:5]=. X X X X X X 0 0 4M . X X X X X 0 0 0 8M
[12:4]=. X X X X 0 0 0 0 16M
[12:3]=(Reserved)
[12:2]=(Reserved)
[12:1]=(Reserved)
[12:0]=(Reserved)
[2C]=Subsystem Vendor ID Write-once, then RO
[2D]=Subsystem Vendor ID Write-once, then RO
[2E]=Subsystem ID Write-once, then RO
[2F]=Subsystem ID Write-once, then RO
[34]=Capability Pointer AGP Capability List Ptr
[35]=Capability Pointer AGP Capability List Ptr
[36]=Capability Pointer AGP Capability List Ptr
[37]=Capability Pointer AGP Capability List Ptr
(40)=VLink Specification ID always reads 00
(41:7)=(Reserved)
(41:6)=(Reserved) NB VLink Capability
(41:5)=VLink 16bit bus width 0=not supported 1=supported
(41:4)=VLink 16bit bus width 0=not supported 1=supported
(41:3)=VLink 4x rate 0=not supported 1=supported
(41:2)=VLink 2x rate 0=not supported 1=supported
(41:1)=(Reserved)
[42:7]=Vlink DnCmd Max Req Depth for NB
[42:6]=(same as above)
[42:5]=(same as above)
[42:4]=(same as above)
[42:3]=DnCmd Write Buffer Size (in doublewords)
[42:2]=(same as above)
[42:1]=(same as above)
[42:0]=(same as above)
(43:7)=UpCmd Max Request Depth (0000=1 UpCmd)
(43:6)=(same as above)
(43:5)=(same as above)
(43:4)=(same as above)
(43:3)=(Reserved)
(43:2)=(Reserved)
(43:1)=(Reserved)
(43:0)=(Reserved)
(44:7)=UpCmd P2C Write Buffer Size (max lines)
(44:6)=(same as above)
(44:5)=(same as above)
(44:4)=(same as above)
(44:3)=UpCmd P2P Write Buffer Size (max lines)
(44:2)=(same as above)
(44:1)=(same as above)
(44:0)=(same as above)
[45:7]=Timer for Normal PriorityReqs from SB (x4 VCLKs)
[45:6]=1001=16x4, 1010=32x4, 1011=64x4, 11xx=Own the
[45:5]=bus for as long as there is a request
[45:4]=(same as above)
[45:3]=Timer for High Priority Reqs from SB (x2 VCLKs)
[45:2]=1001=16x2, 1010=32x2, 1011=64x2, 11xx=Own the
[45:1]=bus for as long as there is a request
[45:0]=(same as above)
[46:7]=NB VLink DownStream High Priority 0=Disable 1=Ena
[46:6]=NB VLink Downlink Cycles 0=Norm Pri, 1=High Pri
[46:5]=Combine STPGNTs to VLink cmds 00=Compatible (1:1)
[46:4]=01=2 STPGNT per VLink cmd10=3:1, 11=4:1 ratios
[46:3]=VLink Master Access Order
[46:2]=(same as above)
[46:1]=(Reserved)
[47:7]=(Reserved)
[47:6]=(Reserved)
[47:5]=(Reserved)
[47:4]=(Reserved)
[47:3]=(Reserved)
[47:2]=VLink Auto-disconnect 0=Disable, 1=Enable
[47:1]=VLink Auto-disc on HALT 0=Disable, 1=Enable
[47:0]=VLink Auto-disc on STPGNT0=Disable, 1=Enable
[48:7]=(Reserved) NB/SB VLink configuration
[48:6]=VLink Rest Bus Width Supported 0=no 1=yes
[48:5]=VLink 16-bit Bus Width Supported 0=no 1=yes
[48:4]=VLink 8-bit Bus Width Supported 0=no 1=yes
[48:3]=VLink 4x Rate Supported 0=no 1=yes
[48:2]=VLink 2x Rate Supported 0=no 1=yes
[48:1]=(Reserved)
[48:0]=(Reserved)
(49:7)=(Reserved)
(49:6)=(Reserved) SB VLink Capability
(49:5)=VLink 16-bit Bus Width Supported 0=no 1=yes
(49:4)=VLink 8-bit Bus Width Supported 0=no 1=yes
(49:3)=VLink 4x Rate Supported 0=no 1=yes
(49:2)=VLink 2x Rate Supported 0=no 1=yes
(49:1)=(Reserved)
(49:0)=(Reserved)
(4A:7)=SB Vlink DnCmd Max Req Depth
(4A:6)=(same as above)
(4A:5)=(same as above)
(4A:4)=(same as above)
(4A:3)=SB VLink DnCmd Write Buffer Size in doublewords
(4A:2)=(same as above)
(4A:1)=(same as above)
(4A:0)=(same as above)
[4B:7]=SB Vlink UpCmd Max Req Depth (0000=1 UpCmd)
[4B:6]=(same as above)
[4B:5]=(same as above)
[4B:4]=(same as above)
[4B:3]=(Reserved)
[4B:2]=(Reserved)
[4B:1]=(Reserved)
[4B:0]=(Reserved)
[4C:7]=SB VLink UpCmd P2C Write Buffer Size (max lines)
[4C:6]=(same as above)
[4C:5]=(same as above)
[4C:4]=(same as above)
[4C:3]=SB VLink UpCmd P2P Write Buffer Size (max lines)
[4C:2]=(same as above)
[4C:1]=(same as above)
[4C:0]=(same as above)
[4D:7]=Timer for Normal PriorityReqs from NB (x4 VCLKs)
[4D:6]=1001=16x4, 1010=32x4, 1011=64x4, 11xx=Own the
[4D:5]=bus for as long as there is a request
[4D:4]=(same as above)
[4D:3]=Timer for High Priority Reqs from NB (x2 VCLKs)
[4D:2]=1001=16x2, 1010=32x2, 1011=64x2, 11xx=Own the
[4D:1]=bus for as long as there is a request
[4D:0]=(same as above)
[4E:7]=(Reserved) CCA Master Priority
[4E:6]=LAN/NIC High Priority 0=Low, 1=High
[4E:5]=(Reserved)
[4E:4]=USB High Priority 0=Low, 1=High
[4E:3]=(Reserved)
[4E:2]=IDE High Priority 0=Low, 1=High
[4E:1]=AC97 High Priority 0=Low, 1=High
[4E:0]=PCI High Priority 0=Low, 1=High
[4F:7] SB VLink Upstream High Priority Cmds 0=dis 1=ena
[4F:6]=(Reserved)
[4F:5]=(Reserved)
[4F:4]=(Reserved)
[4F:3]=(Reserved)
[4F:2]=(Reserved)
[4F:1]=(Reserved)
[4F:0]=DnCycle Wait for UpCycle Wr Flush 0=dis 1=enable
(54:7)=(Reserved)
(54:6)=CPU Frequency Select from SB 0=100MHz 1=133MHz
(54:5)=(Reserved)
(54:4)=(Reserved)
(54:3)=(Reserved)
(54:2)=(Reserved)
(54:1)=(Reserved)
(54:0)=(Reserved)
[55:7]=0WS BackToBack Write to diff DDR Bank 0=dis 1=ena
[55:6]=(Reserved)
[55:5]=DQS Input DLL Adjustment 0=disable 1=enable
[55:4]=DQS Output DLL Adjustment0=disable 1=enable
[55:3]=DQM Removal (Always do 4-burst RW) 0=dis 1=ena
[55:2]=DQS Output 0=disable 1=enable
[55:1]=Auto Precharge for TLB RdorCPU WB 0=disable 1=ena
[55:0]=Write Recovery Time 0=1T 1=2T
[58:7]=Bank 1/0 MA Map Type 000=16Mbit SDRAM
[58:6]=100=64/128Mbit SDRAM 101=256Mbitx32 SDRAM
[58:5]=110=256Mbitx16 SDRAM 111=256Mbitx8 or x4 SDRAM
[58:4]=Bank 1/0 Command Rate 0=2T 1=1T
[58:3]=Bank 3/2 MA Map Type 000=16Mbit SDRAM
[58:2]=100=64/128Mbit SDRAM 101=256Mbitx32 SDRAM
[58:1]=110=256Mbitx16 SDRAM 111=256Mbitx8 or x4 SDRAM
[58:0]=Bank 3/2 Command Rate 0=2T 1=1T
[59:7]=Bank 5/4 MA Map Type 000=16Mbit SDRAM
[59:6]=100=64/128Mbit SDRAM 101=256Mbitx32 SDRAM
[59:5]=110=256Mbitx16 SDRAM 111=256Mbitx8 or x4 SDRAM
[59:4]=Bank 5/4 Command Rate 0=2T 1=1T
[59:3]=Bank 7/6 MA Map Type 000=16Mbit SDRAM
[59:2]=100=64/128Mbit SDRAM 101=256Mbitx32 SDRAM
[59:1]=110=256Mbitx16 SDRAM 111=256Mbitx8 or x4 SDRAM
[59:0]=Bank 7/6 Command Rate 0=2T 1=1T
[5A]=Bank 0 Ending (HA[31:24])
[5B]=Bank 1 Ending (HA[31:24])
[5C]=Bank 2 Ending (HA[31:24])
[5D]=Bank 3 Ending (HA[31:24])
[5E]=Bank 4 Ending (HA[31:24])
[5F]=Bank 5 Ending (HA[31:24])
[56]=Bank 6 Ending (HA[31:24])
[57]=Bank 7 Ending (HA[31:24])
[60:7]=DRAM Type for Bank 7/6 00=SDRAM 10=DDR SDRAM
[60:6]=01=reserved 11=reserved
[60:5]=DRAM Type for Bank 5/4 00=SDRAM 10=DDR SDRAM
[60:4]=01=reserved 11=reserved
[60:3]=DRAM Type for Bank 3/2 00=SDRAM 10=DDR SDRAM
[60:2]=01=reserved 11=reserved
[60:1]=DRAM Type for Bank 1/0 00=SDRAM 10=DDR SDRAM
[60:0]=01=reserved 11=reserved
[64:7]=RAM Precharge to Active 0=TRP 2T 1=TRP 3T
[64:6]=RAM Active to Precharge 0=TRAS 5T 1=TRAS 6T
[64:5]=CAS Latency SDR: 00=1T 01=2T 10=3T
[64:4]=DDR: 01=2T 10=2.5T 11=3T
[64:3]=(Reserved)
[64:2]=ACTIVE to CMD 0=2T 1=3T
[64:1]=Bank Interleave 00=No Interleave
[64:0]=01=2-way 10=4-way 11=Reserved
[65:7]=DRAM Arbitration Timer for AGP (units of 4MCLKs)
[65:6]=(same as above)
[65:5]=(same as above)
[65:4]=(same as above)
[65:3]=DRAM Arbitration Timer for CPU (units of 4MCLKs)
[65:2]=(same as above)
[65:1]=(same as above)
[65:0]=(same as above)
[66:7]=SDR-FBClkSel DDR-DQSInDly0=Auto 1=Manual
[66:6]=DDR-DQS Output Delay Setting 0=Auto 1=Manual
[66:5]=Arbitration Park Policy 00=Park at last bus owner
[66:4]=01=Park at CPU 01=Park at AGP 11=reserved
[66:3]=AGP/CPU Priority (units of 4 MCLKs)
[66:2]=(same as above)
[66:1]=(same as above)
[66:0]=(same as above)
[67:7]=DDR-Strobe Input Delay bits 0..7 all used if DDR
[67:6]=(same as above)
[67:5]=(same as above)
[67:4]=(same as above)
[67:3]=(same as above)
[67:2]=(same as above)
[67:1]=SDRAM-MD Latch Delay 0x=Int.Clk 10=Ext.Clk
[67:0]=11=ext feedback clock
[68]=DDR DQS Output Delay
[69:7]=CPU Faster Than DRAM 0:CPU=DRAM 1:CPU+33=DRAM
[69:6]=DRAM Faster Than CPU 0:DRAM=CPU 1:DRAM+33=CPU
[69:5]=Dynamic CKE 0=disable 1=enable
[69:4]=SwapMD for SDR/DDR compat0=disable 1=enable
[69:3]=DRAM 8K Page Enable 0=disable 1=enable
[69:2]=DRAM 4K Page Enable 0=disable 1=enable
[69:1]=DIMM Type 0=Unbuffered 1=Registered
[69:0]=Multiple Page Mode 0=disable 1=enable
[6A]=Refresh Counter (in units of 16 CPUCLKs)
[6B:7]=Fast Read to Write t-a 0=disable 1=enable
[6B:6]=Page Kept Active when Cross Bank 0=dis 1=ena
[6B:5]=Burst Refresh 0=disable 1=enable
[6B:4]=CKE Function 0=disable 1=enable
[6B:3]=Swap CA22/CA14 0=disable 1=enable
[6B:2]=SDRAM Operation Mode Sel 000=Normal SDRAM Mode
[6B:1]=001=NOP Command Enable 010=All-banks-precharge
[6B:0]=011=MSR Ena 100=CBR CycleEnable 101-111=reserved
[6C:7]=SDRAM A Drive 00=Lowest .. 11=Highest
[6C:6]=(same as above)
[6C:5]=SDRAM B Drive 00=Lowest .. 11=Highest
[6C:4]=(same as above)
[6C:3]=DDR DQS Drive 00=Lowest .. 11=Highest
[6C:2]=(same as above)
[6C:1]=MD/MECC/CAS/CKE Early Clock Select
[6C:0]=00=Latest .. 11=Earliest
[6D:7]=Early Clock Select for SCMD, MA output for 1T
[6D:6]=Command 00=Latest .. 11=Earliest
[6D:5]=DQM Drive 00=Lowest .. 11=Highest
[6D:4]=(same as above)
[6D:3]=RAS# Drive 00=Lowest .. 11=Highest
[6D:2]=(same as above)
[6D:1]=Memory Data Drive (MD, MECC)
[6D:0]=00=Lowest .. 11=Highest
[6E:7]=ECC / ECMode Select 1=Chk,Rep and Correcting
[6E:6]=Perform Read-Modify-Writefor Partial Write
[6E:5]=Enable SERR# 0=Don't assert 1=assert
[6E:4]=Enable SERR# 0=Don't assert 1=assert
[6E:3]=ECC/EC Bank 7/6 (DIMM 3) 0=disable 1=enable
[6E:2]=ECC/EC Bank 5/4 (DIMM 2) 0=disable 1=enable
[6E:1]=ECC/EC Bank 3/2 (DIMM 1) 0=disable 1=enable
[6E:0]=ECC/EC Bank 1/0 (DIMM 0) 0=disable 1=enable
[6F:7]=Multi-bit Error Detected
[6F:6]=Multi-bit Error DRAM Bank
[6F:5]=(Same as bit6)
[6F:4]=(Same as bit6)
[6F:3]=Single-bit Error Detected
[6F:2]=Single-bit Error DRAM Ban
[6F:1]=(Same as bit2)
[6F:0]=(Same as bit2)
[70:7]=CPU to PCI Post-Write 0=disable 1=enable
[70:6]=(Reserved)
[70:5]=PCI Master to DRAM Prefetch
[70:4]=00=always x1=never 10=only for enhance cmd
[70:3]=(Reserved)
[70:2]=PCI Master Read Buffering0=disable 1=enable
[70:1]=Delay Transaction 0=disable 1=enable
[70:0]=(Reserved)
[71:7]=Retry Status 0=no 1=yes
[71:6]=Retry Timeout Action 0=retry 1=flush
[71:5]=Retry Count and backoff 00=2x, back off
[71:4]=01=16x 10=4x 11=64x
[71:3]=PCI Burst 0=disable 1=enable
[71:2]=(Reserved)
[71:1]=Config Cycle: 0=Fix Ad31 1=Compatible Type#1 AD31
[71:0]=IDSEL Control 0=AD11/AD121=AD30/AD31
[73:7]=(Reserved)
[73:6]=PCI Master 1W-State Write0=Zero wait 1=One wait
[73:5]=PCI Master 1W-State Read 0=Zero wait 1=One wait
[73:4]=WSC# 0=disable 1=enable
[73:3]=(Reserved)
[73:2]=(Reserved)
[73:1]=(Reserved)
[73:0]=PCI Master Broken Timer 0=disable 1=enable
[75:7]=Arbitration Mode 0=REQ-based 1=Frame-based
(75:6)=CPU Latency Timer read only
(75:5)=(same as above)
(75:4)=(same as above)
[75:3]=(Reserved)
[75:2]=PCI Master Bus Time-Out 000=Disable
[75:1]=001=1x32 PCICLKs 010=2x32 PCICLKs
[75:0]=011=3x32 PCICLKs ... 111=7x32 PCICLKs
[76:7]=I/O Port 22 Enable
[76:6]=(Reserved)
[76:5]=Master Priority Rotation 0x=every PCI master grant
[76:4]=10=after every 2 PCI 11=after every 3 PCI
[76:3]=REQn# to REQ4# Mapping 00=REQ4# 01=REQ0#
[76:2]=10=REQ1# 11=REQ2#
[76:1]=(Reserved)
[76:0]=REQ4# Is High Priority 0=disable 1=enable
[80:7]=Flush Page TLB 0=disable 1=enable
[80:6]=(Reserved)
[80:5]=(Reserved)
[80:4]=(Reserved)
[80:3]=(Reserved)
[80:2]=(Reserved)
[80:1]=(Reserved)
[80:0]=(Reserved)
(81)=(Reserved - test mode status)
[82]=(Reserved)
[83]=(Reserved)
[84:7]=Graphics Aperture Size 11111111 1M
[84:6]=11111110 2M 11111100 4M
[84:5]=11111000 8M 11110000 16M
[84:4]=11100000 32M 11000000 64M
[84:3]=10000000 128M 00000000 256M
[84:2]=
[84:1]=
[84:0]=
[88:7]=(Reserved)
[88:6]=(Reserved)
[88:5]=(Reserved)
[88:4]=(Reserved)
[88:3]=(Reserved)
[88:2]=(Reserved)
[88:1]=Graphics Aperture 0=disable 1=enable
[88:0]=(Reserved)
[89:7]=Graphics Aperture - Translation Table Base
[89:6]=(Same as bit7)
[89:5]=(Same as bit7)
[89:4]=(Same as bit7)
[89:3]=(Reserved)
[89:2]=(Reserved)
[89:1]=(Reserved)
[89:0]=(Reserved)
[8A:7]=Graphics Aperture - Translation Table Base
[8A:6]=(Same as bit7)
[8A:5]=(Same as bit7)
[8A:4]=(Same as bit7)
[8A:3]=(Same as bit7)
[8A:2]=(Same as bit7)
[8A:1]=(Same as bit7)
[8A:0]=(Same as bit7)
[8B:7]=Graphics Aperture - Translation Table Base
[8B:6]=(Same as bit7)
[8B:5]=(Same as bit7)
[8B:4]=(Same as bit7)
[8B:3]=(Same as bit7)
[8B:2]=(Same as bit7)
[8B:1]=(Same as bit7)
[8B:0]=(Same as bit7)
[90:7]=Disable ROM Table
[90:6]=(Reserved)
[90:5]=Read Data Delay
[90:4]=(same as above)
[90:3]=Write Data Delay
[90:2]=(same as above)
[90:1]=(same as above)
[90:0]=(same as above)
[91:7]=NB DataRcvrMux Initial Count
[91:6]=(same as above)
[91:5]=NB AddrRcvrMux Initial Count
[91:4]=(same as above)
[91:3]=(Reserved)
[91:2]=CPU Data/Addr Mux Preload Count
[91:1]=(same as above)
[91:0]=(same as above)
[92:7]=Disc when STPGNT# Detect 0=disable 1=enable
[92:6]=Write to Read Delay
[92:5]=Read to Write Delay
[92:4]=(same as above)
[92:3]=(Reserved)
[92:2]=Write Data Delay from SYSDC to CPU Data Output
[92:1]=(same as above)
[92:0]=(same as above)
[93:7]=MaxContigProbeSysDC
[93:6]=(same as above)
[93:5]=MaxContigReadSysDC
[93:4]=(same as above)
[93:3]=(same as above)
[93:2]=MaxContigWriteSysDC
[93:1]=(same as above)
[93:0]=(same as above)
[94:7]=SDRAM Self-Refresh when disconnected 0=dis 1=ena
[94:6]=Probe next Tag State T1 when PCI Master ReadCach Ena
[94:5]=(Reserved)
[94:4]=(Reserved)
[94:3]=DRAM Speculative Read 0=disable 1=enable
[94:2]=PCI Master Pipeline Request
[94:1]=P2C/C2P Concurrency 0=disable 1=enable
[94:0]=Fast R2W turnaround 0=disable 1=enable
[95:7]=MWQ Time Slot While MWQ is full (units of 8 CPUCLKs)
[95:6]=(same as above)
[95:5]=(same as above)
[95:4]=Write Policy CPU to RAM 0=FIFO>2 or idle 1=disable
[95:3]=PMR Cycle Control 0=Stall if MWQ full
[95:2]=FID Command Detect 0=disable 1=enable
[95:1]=HALT Command Detect 0=disable 1=enable
[95:0]=(Reserved)
[96:7]=RHOCTW
[96:6]=PMW Address Compare 0=compat 1=compare w/PMW
[96:5]=CPU2DRAM causes RdModWrt 0=partial only 1=enable
[96:4]=Concur Fw VLD&PSQH Ptr 0=compat 1=enable
[96:3]=PCI Master Pipeline Req 100/133DDR 0=compat 1=en
[96:2]=HBHIT Guard 0=compat 1=enable
[96:2]=(Reserved)
[96:1]=(Reserved)
[96:0]=(Reserved)
[97:7]=CPU Clock Division 0000=11 0001=12
[97:6]=0010=5 0011=6 0100=7 0101=8 0110=9 0111=10
[97:5]=1000=3 1001=4
[97:4]=(same as above)
[97:3]=Add 0.5 to above CPU Clk Divisor
[97:2]=S2K Drive Strength 0=by register 1=auto comp
[97:1]=Fast Address Out Decode 0=normal 1=fast
[97:0]=S2K Compensation Circuit 0=always 1=ena on disconn
[98:7]=S2K Pullup Drive Strength
[98:6]=(same as above)
[98:5]=(same as above)
[98:4]=(same as above)
[98:3]=S2K Pulldown Drv Strength
[98:2]=(same as above)
[98:1]=(same as above)
[98:0]=(same as above)
(99:7)=S2K Pullup Auto Compensation Result
(99:6)=(same as above)
(99:5)=(same as above)
(99:4)=(same as above)
(99:3)=S2K Pulldown Auto Compensation Result
(99:2)=(same as above)
(99:1)=(same as above)
(99:0)=(same as above)
(9A:7)=S2K Edge DQ Mode 0=Central DQ 1=Edge DQ
[9A:6]=S2K Strobe Delay (EdgeDQ)0000000=auto
[9A:5]=(same as above)
[9A:4]=(same as above)
[9A:3]=(same as above)
[9A:2]=(same as above)
[9A:1]=(same as above)
[9A:0]=(same as above)
[9B]=S2K Strobe DLL Delay Counter (Auto)
[9C:7]=S2K Compensation Circuit Trigger
(9C:6)=DLL AutoDetect
[9C:5]=Delay Compensation Counter Control
[9C:4]=S2K Pad AC Coupling to VREF Signal in Address /
[9C:3]=Data Output Clock
[9C:2]=S2K Pad Slew Rate Ctrl 000=weakest.111=strongest
[9C:1]=(same as above)
[9C:0]=(same as above)
[9D:7]=S2K Strobe Output DriveStrength P Control
[9D:6]=(same as above)
[9D:5]=(same as above)
[9D:4]=(same as above)
[9D:3]=S2K Strobe Output DriveStrength N Control
[9D:2]=(same as above)
[9D:1]=(same as above)
[9D:0]=(same as above)
(A0)=AGP ID always reads 02
(A1)=Pointer to Next Item always reads C0
(A2:7)=Major Specification Rev. always reads 0010b
(A2:6)=(Same as bit7)
(A2:5)=(Same as bit7)
(A2:4)=(Same as bit7)
(A2:3)=Minor Specification Rev. always reads 0000b
(A2:2)=(Same as bit3)
(A2:1)=(Same as bit3)
(A2:0)=(Same as bit3)
(A3)=(Reserved)
(A4:7)=(Reserved) always reads 0
(A4:6)=(Reserved) always reads 0
(A4:5)=4G Supported can write at AE
(A4:4)=Fast Write Supported can write at AE
(A4:3)=(Reserved) always reads 0
(A4:2)=4X Rate Supported can write at AE
(A4:1)=2X Rate Supported can write at AC
(A4:0)=1X Rate Supported always reads 1
(A5:7)=(Reserved)
(A5:6)=(Reserved)
(A5:5)=(Reserved)
(A5:4)=(Reserved)
(A5:3)=(Reserved)
(A5:2)=(Reserved)
(A5:1)=Supports SideBand Addressalways reads 1
(A5:0)=(Reserved) always reads 0
(A6)=(Reserved)
(A7)=Maximum AGP Requests always reads 1Fh
[A8:7]=(Reserved)
[A8:6]=(Reserved)
[A8:5]=4G Enable 0=disable 1=enable
[A8:4]=Fast Write Enable 0=disable 1=enable
[A8:3]=(Reserved)
[A8:2]=4X Mode Enable 0=disable 1=enable
[A8:1]=2X Mode Enable 0=disable 1=enable
[A8:0]=1X Mode Enable 0=disable 1=enable
[A9:7]=(Reserved)
[A9:6]=(Reserved)
[A9:5]=(Reserved)
[A9:4]=(Reserved)
[A9:3]=(Reserved)
[A9:2]=(Reserved)
[A9:1]=SideBand Addressing 0=disable 1=enable
[A9:0]=AGP Enable 0=disable 1=enable
[AA]=(Reserved)
[AB]=Request Depth always reads 0
(AC:7)=AGP Enabled
[AC:6]=AGP Read Synchronization 0=disable 1=enable
[AC:5]=AGP Read Snoop DRAM P-W-B0=disable 1=enable
[AC:4]=GREQ# Priority 0=disable 1=enable
[AC:3]=2X Rate Supported 0=not 1=supported
[AC:2]=LPR In-Order Access 0=not 1=executed
[AC:1]=AGP Arbitration Parking 0=disable 1=enable
[AC:0]=AGP-PCI Master/CPU-PCI TC0=2T or 3T 1=1T
[AD:7]=(Reserved)
[AD:6]=(Reserved)
[AD:5]=(Reserved)
[AD:4]=Choose First/Last Ready 0=Last 1=First
[AD:3]=AGP Data Phase Latency default=02h
[AD:2]=(Same as above)
[AD:1]=(Same as above)
[AD:0]=(Same as bit3)
[AE:7]=(Reserved)
[AE:6]=(Reserved)
[AE:5]=Greater Than 4GB of Supp.0=disable 1=enable
[AE:4]=Fast Write Supported 0=not supp. 1=supported
[AE:3]=(Reserved)
[AE:2]=4x Rate Supported 0=not supp. 1=supported
[AE:1]=(Reserved)
[AE:0]=(Reserved)
[AF:7]=AGP Strobe Output Drive Strength N Control
[AF:6]=(Same as above)
[AF:5]=(Same as above)
[AF:4]=(Same as above)
[AF:3]=AGP Strobe Output Drive Strength P Control
[AF:2]=(Same as above)
[AF:1]=(Same as above)
[AF:0]=(Same as above)
[B0:7]=AGP 4x Strobe VREF Ctrl 0=STB#/v-v 1=AGPREF
[B0:6]=AGP 4x Strobe & GD Pad 0=c-circuit 1=RxB1[7-0]
(B0:5)=AGP Compensation Circuit N Control Output
(B0:4)=(Reserved)
(B0:3)=(Reserved)
(B0:2)=AGP Compensation Circuit P Control Output
(B0:1)=(Reserved)
(B0:0)=(Reserved)
[B1:7]=AGP Output Buffer Drive - Strength N Ctrl(def=6)
[B1:6]=(Same as above)
[B1:5]=(Same as above)
[B1:4]=(Same as above)
[B1:3]=AGP Output Buffer Drive - Strength P Ctrl(def=3)
[B1:2]=(Same as above)
[B1:1]=(Same as above)
[B1:0]=(Same as above)
[B2:7]=GD/GBE/GDS, SBA/SBS Ctrl
[B2:6]=(Reserved)
[B2:5]=(Reserved)
[B2:4]=GD[31-16] Staggered Delay0=none 1=1ns
[B2:3]=(Reserved)
[B2:2]=(Reserved)
[B2:1]=AGP Voltage 0=1.5V 1=3.3V
[B2:0]=GDS Output Delay 0=none 1=0.4ns
[B4:7]=VLink NB Autocomp Output Value
[B4:6]=(same as above)
[B4:5]=VLink Pullup Compensation0=Auto 1=Manual(use b2-3)
[B4:4]=VLink Pulldown Comp 0=Auto 1=Manual(use b0-1)
[B4:3]=Pullup Compensation Manual Setting
[B4:2]=(same as above)
[B4:1]=Pulldown Compensation Manual Setting
[B4:0]=(same as above)
[B5:7]=VLink Strobe Pullup Manual Setting
[B5:6]=(same as above)
[B5:5]=VLink Strobe Pulldown Manual Setting
[B5:4]=(same as above)
[B5:3]=(Reserved)
[B5:2]=(Reserved)
[B5:1]=(Reserved)
[B5:0]=VLink Slew Rate Control 0=disable 1=enable
[B8:7]=VLink SB Autocomp Output Value
[B8:6]=(same as above)
[B8:5]=VLink Pullup Compensation0=Auto 1=Manual(use b2-3)
[B8:4]=VLink Pulldown Comp 0=Auto 1=Manual(use b0-1)
[B8:3]=Pullup Compensation Manual Setting
[B8:2]=(same as above)
[B8:1]=Pulldown Compensation Manual Setting
[B8:0]=(same as above)
[B9:7]=(Reserved)
[B9:6]=(Reserved)
[B9:5]=(Reserved)
[B9:4]=(Reserved)
[B9:3]=(Reserved)
[B9:2]=(Reserved)
[B9:1]=(Reserved)
[B9:0]=VLink Slew Rate Control 0=disable 1=enable
[BE:7]=MECC Drive Strength
[BE:6]=(same as above)
[BE:5]=(Reserved)
[BE:4]=(Reserved)
[BE:3]=(Reserved)
[BE:2]=(Reserved)
[BE:1]=(Reserved)
[BE:0]=(Reserved)
[BF:7]=MA/SCMD Pin Toggle Redux 0=disable 1=enable
[BF:6]=Slew Rate Ctrl MA/SCMD A 0=disable 1=enable
[BF:5]=Slew Rate Ctrl MA/SCMD B 0=disable 1=enable
[BF:4]=(Reserved)
[BF:3]=DIMM #3 MAA/MAB Select 0=MAA 1=MAB
[BF:2]=DIMM #2 MAA/MAB Select 0=MAA 1=MAB
[BF:1]=DIMM #1 MAA/MAB Select 0=MAA 1=MAB
[BF:0]=DIMM #0 MAA/MAB Select 0=MAA 1=MAB
(C0)=Power Management Capability ID (01h)
(C1)=Power Management New Pointer (00h)
(C2)=Power Management Capabilities I (02h)
(C3)=Power Management Capabilities II (00h)
[C4:7]=(Reserved)
[C4:6]=(Reserved)
[C4:5]=(Reserved)
[C4:4]=(Reserved)
[C4:3]=(Reserved)
[C4:2]=(Reserved)
[C4:1]=Power State 00=D0 01=reserved
[C4:0]= 10=reserved 11=D3 Hot
(C5)=Power Management Status (00h)
(C6)=PCI-to-PCI Bridge Support Ext (00h)
(C7)=Power Management Data (00h)
'00..01'=Vendor ID 1106 RO
'02..03'=Device ID 3099 RO
'04..05'=Command 0006 RW
'06..07'=Status 0210 WC
'08'=Revision ID Cn RO
'09'=Program Interface 00 RO
'0A'=Sub Class Code 00 RO
'0B'=Base Class Code 06 RO
'0C'=-reserved- 00
'0D'=Latency Timer 00 RW
'0E'=Header Type 00 RO
'0F'=Built In Self Test (BIST) 00 RO
'10..13'=Graphics Aperture Base 0000 0008 RW
'14..2B'=-reserved- 00
'2C..2D'=Subsystem Vendor ID 0000 W1
'2E..2F'=Subsystem ID 0000 W1
'30..33'=-reserved- 00
'34..37'=Capability Pointer 0000 00A0 RO
'38..3F'=-reserved- 00
'50'=S2K Timing Control I 00 RW
'51'=S2K Timing Control II 00 RW
'52'=S2K Timing Control III 70 RW
'53'=BIU Arbitration Control 00 RW
'54'=BIU Control 00 RW
'55'=Debug (Do Not Program)
'56..57'=Bank x Ending (HA[31:24]) 01 RW
'58..59'=MA Map Type 0040 RW
'5A..5F'=Bank x Ending (HA[31:24]) 01 RW
'60'=DRAM Type 00RW
'61..63'=-reserved- 00
'64'=DRAM Timing for All Banks EC RW
'68'=DRAM Control 00 RW
'69'=DRAM Clock Select 00 RW
'6A'=DRAM Refresh Counter 00 RW
'6B'=DRAM Arbitration Control 01 RW
'6C'=SDRAM Control 00 RW
'6D'=DRAM Control Drive Strength 00 RW
'6E'=ECC Control 00 RW
'6F'=ECC Status 00 RO
'70'=PCI Buffer Control 00 RW
'71'=CPU to PCI Flow Control 1 00 RW
'72'=CPU to PCI Flow Control 2 00 RW
'73'=PCI Master Control 1 00 RW
'74'=PCI Master Control 2 00 RW
'75'=PCI Arbitration 1 00 RW
'76'=PCI Arbitration 2 00 RW
'77'=Chip Test (do not program) 00 RW
'78'=PMU Control 00 RW
'79'=PMU Control 00 RW
'7A'=Miscellaneous Control 1 00 RW
'7B'=Miscellaneous Control 2 00 RW
'7C..7D'=-reserved- 00
'7E..7F'=PLL Test Mode (do not program) 00 RW
'80..83'=GART/TLB Control 0000 0000 RW
'84'=Graphics Aperture Size 00 RW
'85..87'=-reserved- 00
'88..8B'=Gr. Aperture TLB Base Register Base 0000 0000 RW
'8C..9F'=-reserved- 00
'A0'=AGP ID 02 RO
'A1'=AGP Next Item Pointer 00 RO
'A2'=AGP Specification Revision 20 RO
'A3'=-reserved- 00
'A4..A7'=AGP Status 1F00 0203 RO
'A8..AB'=AGP Command 0000 0000 RW
'AC'=AGP Control 00 RW
'AD'=AGP Latency Timer 02 RW
'AE'=AGP Miscellaneous Control 00 RW
'AF'=-reserved- 00
'B0'=AGP Pad Control / Status 8x RW
'B1'=AGP Drive Strength 63 RW
'B2'=AGP Pad Drive / Delay Control 00 RW
'B3'=CPU Strapping strapping RO
'B4'=S2K Compensation Strapping strapping RO
'B5'=S2K Compensation Result 00 RO
'B6..BF'=-reserved- 00
'BE..BF'=DRAM Power Control 00 RW
'C0'=Power Management Capability ID 01 RO
'C1'=Power Management New Pointer 00 RO
'C2'=Power Management Capabilities I 02 RO
'C3'=Power Management Capabilities II 00 RO
'C4'=Power Management Control / Status 00 RW
'C5'=Power Management Status 00 RO
'C6'=PCI-to-PCI Bridge Support Extension 00 RO
'C7'=Power Management Data 00 RO
'C8..FF'=-reserved- 00
<---END--->
Good luck
Bernhard Haim
the "cpu-cooling-bit-trick" doesn't seem to work.
Possible reasons:
- ACPI is disabled
- the PSU is too weak (there is a huge power consumption difference
between running state (~65 Watt) and idle-mode (~5-10 Watt) within a
very short period of time)
If your system meets this requirements, I don't know how to find a
solution, sorry...
Bernhard
User wrote:
>
> On Wed, 28 Nov 2001 21:56:48 +0100, Bernhard Haim <mechat...@gmx.at> wrote:
>
> >Does it work when you set your cpu/fsb to default clock?
>
> No , initially it booted OK , as soon as I opened the MBM5 it crashed and keep
> rebooting every time half way thru disk checking . I'm running winXP and have only
> few proggies load in startup (MSmouse,ATI video card ) My BIOS are set to
> optimum.Video card is in AGP , the only PCI device I have is the modem .
Ian
EP-8KHA+
1600+ XP @ 1432 (9.5 x 150)
Crucial PC2100 Cas 2.5 set to FAST
Vcore 1.825
CPU 48 case 32
User wrote:
> On Wed, 28 Nov 2001 20:17:20 +0100, Bernhard Haim <mechat...@gmx.at> wrote:
>
> >I've found a very well-documented PCR file for the VIA KT266 (it even
> >has the cooling-bit description at register 92).
> >Here's the the link: http://www.vr-zone.com/downloads/kt266_pcr.zip
> >
> >Bernhard
> >
> >
>
> Thank you Bernhard , I was able to load that file 11063099.pcr but after modified the
> data bit to read E9 (11101001) and used the SET command , my computer reboot . Unsure
> if it's a "good written" KT266 file , I then use WPCRSET as "quick fix" , in
> "register" I entered "92" in "data" I entered "E9" then reboot , but then my computer
> kept rebooting itself . Did I do something wrong ?
>
> My specs:
>
> Epox 8KHA+
> Tbird 1.4 running 1.5 @ 140x11
> vcore=1.8
> CPU=47 , Case=41
>
> >User wrote:
> >>
> >> Can you point us to where we can find these PCR files please . Since It's such a
> >> small file would it be so much trouble to post it here ?
--
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