taken from the AMD white papers #24309
and are the requirements for a cold boot (power on)
<SNIP>
7. The FID[3:0] signals are valid within 100 ns after PWROK is
asserted. The chipset must not sample the FID[3:0] signals
until they become valid. Refer to the AMD AthlonT
Processor-Based Motherboard Design Guide, order# 24363, for
the specific implementation and additional circuitry
required.
8. The FID[3:0] signals become valid within 100 ns after
RESET# is asserted. Refer to the AMD AthlonT Processor-
Based Motherboard Design Guide, order# 24363, for the
specific implementation and additional circuitry required.
<SNIP>
I though I was going to go crazy trying to find proof of what I have been
saying all along in the news groups. So if I read this right, on Pwr up
(cold) timings have to be < 100ns in order to cold boot the system. This
document also talks about the power must stablize within 10ns or no boot
either. So that is why AMD has Approved Power Suppl;ies.
Any comments?
---Hey Hey Hey, It's Kaptian 'K"---
Oh, jeez, I thought everybody knew that. ;)
Excellent detective work there. Ya done good.
Bill
--
"Give a man a fish, and you feed him for a day...
Force everybody else to give him fish, and he'll vote
for you forever."
A Taxpayer
ya actually...so what does all this mean for us no so techie types? I
understand a bit that the cpu has to kinda do it's thing first before it can
boot right? So it could be the power supply but it could still just be a
mobo cpu timing issue no? and if it's not the supply how do I fix it? I
e-mailed soltek to see if they had an answer and I did some more research on
my power supply...It has a combined output of 175w. Enhance (the type of
supply I have) "does" have athlon xp approved supplies but not the exact
model I have (mine is actually athlon approve up too xp)...figures eh! I
guess what I'd like to know is should I order the new psu or should I just
wait and see what soltek has to say or is there another fix, such as, bios
settings that can be done? appreciate all the research you've done
Kaptian...what a pain in the rumpess....hehehee...one more thing...This
enhance supply is loud...any recommendations on a quiet one? Thx again
matt
good luck
(Myself I have been looking into taking 2 - 250 watters and hooking them
together in parallel to provide a total output of 500w. Circuit board
design is almost finished and will make it available to all who want it
after I test it out on my own system. Circuit board will cost around $35.00
and have very stable current output through high quality voltage regulators
and filtering through a big bank of caps)
"Matt" <katm...@SpamNOhotmail.com> wrote in message
news:6Qtj8.5344$Oo3.200...@newssvr21.news.prodigy.com...
"Nitza666" <nitz...@FAhotmail.com> wrote in message
news:a6m1j9$k72$1...@nic.grnet.gr...
Matt
"Kaptian Krunch" <kaptiankrunch=remov...@comcast.net> wrote in message
news:3c8ebba7$1...@news.mhogaming.com...
KK
"Nitza666" <nitz...@FAhotmail.com> wrote in message
news:a6mjie$qsn$1...@nic.grnet.gr...
KK
"Nitza666" <nitz...@FAhotmail.com> wrote in message
news:a6mirm$qjo$1...@nic.grnet.gr...
Thanx all
KK
"Matt" <katm...@SpamNOhotmail.com> wrote in message
news:AnAj8.5498$Ds5.211...@newssvr21.news.prodigy.com...
thank you for your time to reply.
KK
"Nitza666" <nitz...@FAhotmail.com> wrote in message
news:a6okno$204$1...@nic.grnet.gr...
"Nitza666" <nitz...@FAhotmail.com> wrote in message
news:a6q7f6$plj$1...@nic.grnet.gr...
This means that if the motherboard does not apply an extra circuit to delay
the NB_RESET# signal after the FIDs are fully valid, the motherboard may
potentially get the wrong values from the FID lines. This is the reason why
the earlier motherboard versions cannot support the AthlonXP processor.
Getting the wrong FIDs may not always result in the system being unable to
boot up - but it may result in the motherboard using the wrong parameters to
initialise the processor, causing system instabilities under certain
circumstances. On the earlier Athlon processors the FIDs are always valid
after the Vcore of the processor is valid and this is why no motherboard has
a problem supporting the highest frequency of old Athlon.
In practice, this change is very subtle. Many AthlonXP processors will work
fine on earlier motherboard revisions. Others will work fine for some
percentage of the time, but will require a hard reset during boot if this
timing assertion is violated. However, only revision 1.3 of the motherboard
contains the necessary hardware modifications to fully support AMD's revised
timing specification. This is why ABIT cannot officially support the
AthlonXP processor on earlier motherboard revisions - although if you can
live with the occasional hard reset there is no problem. Furthermore, ABIT
have made attempts to improve the timing compatibility with the 64 BIOS
release, but still cannot officially support the processor on these
revisions.
No BIOS release will allow ABIT to properly support the AthlonXP on
motherboard versions prior to v1.3. However, in practice, the timing
difference is sufficiently subtle that many processors will work fine, and
others will simply require the occasional reset during boot. Once the
processor has booted, the stability should usually be the same on all
motherboards.
In some respects ABIT are simply being more honest than other motherboard
manufacturers. In most cases the AthlonXP will appear to work OK - or have
occasional instabilities. However, rather than pretending that a simple BIOS
update can resolve the problem, ABIT are only officially claiming that the
board with the proper additional circuitry can support these new processors.
I respect KK's research, but do not agree with his conclusions. The FID
specs tell you how long the chipset has to recognize the multiplier on the
cpu, they have nothing to do with power supplies. The FID specs changed
between the Thunderbird and the XP, and that meant that some motherboards
could handle the new chips without mods, some needed a bios update to work
reliably, and some wouldn't work at all. Newer motherboards were designed
with the XP in mind and have no such problems.
"Ed" <n...@home.com> wrote in message
news:evf39uotg2bfuuhg3...@4ax.com...
> That is for Motherboard Design Guides, really has nothing to do with a
> PSU. The Mobo has to do the timing tricks.
1. RESET# must be asserted before PWROK is asserted.
The AMD Athlon XP processor does not set the correct
clock multiplier if PWROK is asserted prior to a RESET# < relies on
PWR OK from power supply
assertion. It is recommended that RESET# be asserted at
least 10 nanoseconds prior to the assertion of PWROK.
In practice, a Southbridge asserts RESET# milliseconds
before PWROK is deasserted.
2. All motherboard voltage planes must be within
specification before PWROK is asserted.
PWROK is an output of the voltage regulation circuit on the
motherboard. PWROK indicates that VCC_CORE and all
other voltage planes in the system are within specification.
The motherboard is required to delay PWROK assertion for
a minimum of three milliseconds from the 3.3 V supply
being within specification. This delay ensures that the
< same here
system clock (SYSCLK/SYSCLK#) is operating within
specification when PWROK is asserted.
The processor core voltage, VCC_CORE, must be within
specification as dictated by the VID[4:0] pins driven by the
processor before PWROK is asserted. Before PWROK
assertion, the AMD Athlon processor is clocked by a ring
oscillator.
The processor PLL is powered by VCCA. The processor PLL
does not lock if VCCA is not high enough for the processor
logic to switch for some period before PWROK is asserted. <
power ok
VCCA must be within specification at least five
microseconds before PWROK is asserted.
In practice VCCA, VCC_CORE, and all other voltage planes
must be within specification for several milliseconds before
PWROK is asserted.
After PWROK is asserted, the processor PLL locks to its
operational frequency.
3. The system clock (SYSCLK/SYSCLK#) must be running
before PWROK is asserted.
When PWROK is asserted, the processor switches from
driving the internal processor clock grid from the ring
oscillator to driving from the PLL. The reference system
24309D-January 2002 AMD AthlonT XP Processor Model 6 Data Sheet <
same here
Preliminary Information
clock must be valid at this time. The system clocks are
designed to be running after 3.3 V has been within
specification for three milliseconds.
4. PWROK assertion to deassertion of RESET#
The duration of RESET# assertion during cold boots is
intended to satisfy the time it takes for the PLL to lock with
a less than 1 ns phase error. The processor PLL begins to
run after PWROK is asserted and the internal clock grid is
switched from the ring oscillator to the PLL. The PLL lock
time may take from hundreds of nanoseconds to tens of
microseconds. It is recommended that the minimum time
< hmmm more power ok
between PWROK assertion to the deassertion of RESET# be
at least 1.0 milliseconds. Southbridges enforce a delay of
1.5 to 2.0 milliseconds between PWRGD (Southbridge
version of PWROK) assertion and NB_RESET# deassertion.
5. PWROK must be monotonic and meet the timing
< power ok here too
requirements as defined in Table 13, "General AC and DC
Characteristics," on page 36. The processor should not
switch between the ring oscillator and the PLL after the
initial assertion of PWROK.
6. NB_RESET# must be asserted (causing CONNECT to also
assert) before RESET# is deasserted. In practice all
Southbridges enforce this requirement.
If NB_RESET# does not assert until after RESET# has
deasserted, the processor misinterprets the CONNECT
assertion (due to NB_RESET# being asserted) as the
beginning of the SIP transfer. There must be sufficient
overlap in the resets to ensure that CONNECT is sampled
asserted by the processor before RESET# is deasserted.
7. The FID[3:0] signals are valid within 100 ns after PWROK is
< power ok here again
asserted. The chipset must not sample the FID[3:0] signals
until they become valid. Refer to the AMD AthlonT
Processor-Based Motherboard Design Guide, order# 24363, for
the specific implementation and additional circuitry
required.
8. The FID[3:0] signals become valid within 100 ns after
RESET# is asserted. Refer to the AMD AthlonT Processor-
Based Motherboard Design Guide, order# 24363, for the
specific implementation and additional circuitry required.
Ok Ed, the Mother board design guide is a seprate document, but has info for
the additional circuitry
that the mobo manufacturers must impliment inorder to get the above timings
correct.
You say it has nothing to do with a power supply, however it does mention in
7 places about the PWROK signal
which comes from the power supply as well as the voltages associated with
it.
sorry group if this is so long, but some people need some education, and
some just cant be educated.
KK
"Ed" <n...@home.com> wrote in message
news:evf39uotg2bfuuhg3...@4ax.com...
> That is for Motherboard Design Guides, really has nothing to do with a
> PSU. The Mobo has to do the timing tricks.
>
> On Tue, 12 Mar 2002 02:58:34 -0500, "Kaptian Krunch"
> <kaptiankrunch=remov...@comcast.net> wrote:
>
> >Hey Kaptian Krunch Komes Through! Oh Joy, Oh Joy, Oh Joy!
> >If you have a cold boot problem with the XP processor This is a must read
> >post.
<snip to shorten>
"Skid" <sk...@attbi.com> wrote in message
news:Nrpk8.31836$WP2.8...@typhoon.atl.ipsvc.net...
> Thanks, Ed. That is my conclusion as well. These specs are really AMD's
> design advice for motherboard manufacturers, and they explain -- among
other
> things -- why the Athlon XP works fine in some older KT133A mobos and not
> others. This whole issue was hotly discussed in regards to the Abit KT7A,
> and this explanation is lifted from the FAQ at
<snip>
"Nitza666" <nitz...@FAhotmail.com> wrote in message
news:a6todb$hlf$1...@nic.grnet.gr...
"Nitza666" <nitz...@FAhotmail.com> wrote in message
news:a6u5c2$mh1$1...@nic.grnet.gr...
KK
-It is a proven fact that people can not hear with their mouths wide open -
"Nitza666" <nitz...@FAhotmail.com> wrote in message
news:a6u5c2$mh1$1...@nic.grnet.gr...