Why so many pins?
David
Can anyone explain why do fpgas have such a large number of pins? I
understand that for very large design you might need those 150 pins but
there are some applications where you need a lot of gates but only 10 I/O
pins would be more than enough. The chip takes a lot of place on the pcb and
it is a nightmare to do the layout. Why don't we have some mid-large fpgas
in terms of gate, but say in a standard 40 pin package?
Thanks
David
Phil Hays
> Can anyone explain why do fpgas have such a large number of pins? I
> understand that for very large design you might need those 150 pins but
> there are some applications where you need a lot of gates but only 10 I/O
> pins would be more than enough.
A design using a 64bit PCI, an intrface to a processor, a bank or two of
SDRAM and a couple of 64 bit (+control and address) interface to custom
hardware, plus another hundred plus for termination, reference levels,
clocking, debug, plus powers and ground, and 1156 might not be enough.
At the other end, once the package is about the same size as the die,
there isn't much reason to make it smaller. And as such packages and
die are cheap, there isn't much business case for a low pinout package.
--
Phil Hays
Ray Andraka
you aren't using. You can greatly simplify the layout for example, by using
only the I/O near the physical edge of the package and leaving the majority of
the interior pins either connected to ground, power or open. You can reduce
package ground bounce by wiring unused I/O to ground and then configuring those
pins as outputs permanently tied to a logic '0';
Phil Hays wrote:
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email r...@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Nicholas C. Weaver
Phil Hays <SpamPos...@attbi.com> wrote:
>At the other end, once the package is about the same size as the die,
>there isn't much reason to make it smaller. And as such packages and
>die are cheap, there isn't much business case for a low pinout package.
This is especially true of the small chip-scale and slightly larger
BGA packages.
EG, the FT256 BGA package is 182 usable I/Os, with a footprint of
1.7 cm x 1.7 cm. At a 1mm ball pitch, you can fit a LOT of IOs in
that footprint (16x16 grid for 256 pins, 182 usable I/Os).
--
Nicholas C. Weaver nwe...@cs.berkeley.edu
David
> SDRAM and a couple of 64 bit (+control and address) interface to custom
> hardware, plus another hundred plus for termination, reference levels,
> clocking, debug, plus powers and ground, and 1156 might not be enough.
Let's say I want to design a PCM to PWM converter...I need 2 inputs, 5
outputs + 3 debug = 10 pins. I'm stuck with a 156 pin device....I also need
the power of an fpga, since there are a lot of multiplications involving a
lot of bits. Using a dsp would be a nightmare.
David
"Phil Hays" <SpamPos...@attbi.com> wrote in message
news:3E32D405...@attbi.com...
Kuan Zhou
Are you going for the ISFPGA next month?
Where did you get so many details in hardware when you are a CS
student?
sincerely
-------------
Kuan Zhou
Nicholas C. Weaver
ISFPGA? Do you mean the ACM FPGA Conference in Monterey?
> Where did you get so many details in hardware when you are a CS
>student?
Easy, my thesis is on a fixed-frequency FPGA architecture. I have to
know these things. :)
Kuan Zhou
I got a poster in ACM FPGA.ISFPGA means International Symposium on ....
It's the same thing.Where did you get the hardware information?From
manuals?
Why you want to set a fixed frequency for all the applications?I am
curious.
But I can't go to the conference next month.My boss will go instead of
me.
Nicholas C. Weaver
> I got a poster in ACM FPGA.ISFPGA means International Symposium on
Most call it "FPGA", eg FPGA 2003. Just as IEEE Symposium on
Field-Programmable Custom Computing Machines is "FCCM".
What's your poster on?
>.... It's the same thing.Where did you get the hardware
>information?From manuals?
Manuals, intuition, also a couple designs (The best being the AES core
I built as a benchmark: 1.3 Gb AES core in 10 BlockRAMs and 800
slices, Spartan II-100-5 speedgrade (A $10 part). It's 1.7 Gb/s in a
Virtex E. Remove the pipelining and it is still >500 Mbps regardless
of feedback modes).
I've developed a pretty good intuition for "Brand X" from doing a few
designs, none at all for "Brand A".
Also reading Ray Andraka's, Peter Alfke's, and other posts here. Ray
Andraka especially is very informative.
Also, I'm a bit of a luddite and think in terms of LUTs and flip flops
and schematics. Which actually helps if you want to push the limits
of the architecture.
The difference between no pipelining and smart pipelining can be 2x or
even more. You CAN have tools do that automatically (I'm presenting
mine at FPGA), but the current systems don't really support that.
Hand layout can easily buy another 20-30% or more.
> Why you want to set a fixed frequency for all the applications?I am
>curious.
Higher throughput. Designs will ALWAYS meet the array's architectural
throughput if feed-forward or have sufficient task-level parallelism.
Not to mention pipelined interconnect to enable higher clock
frequencies.
Easier to integrate as a coprocessor or system-on-a-chip, as there are
now only one clock to deal with, no design-dependant clock domains.
Faster tools (route & retime a 6000 LUT design in ~1 minute, route and
retime an AES core in 12 seconds).
Kuan Zhou
I may not be able to come to FPGA 2003.So you can only see the
abstract of my poster in the proceedings.I am a circuit designer.Not like
you, you concerntrate on the design using FPGAs.I am designing a new
family of FPGA using SiGe technology (not CMOS).My boss may present a
paper in the conference.I am the 3rd author of that regular paper.There
are lots of mistakes in that paper.But the idea is there.
Will Peter Alfke, Ray Andraka go to attend the conference?
sincerely
-------------
Kuan Zhou
ECSE department
On Sun, 26 Jan 2003, Nicholas C. Weaver wrote:
Nicholas C. Weaver
Kuan Zhou <zh...@rpi.edu> wrote:
>Hi,
> I may not be able to come to FPGA 2003.So you can only see the
>abstract of my poster in the proceedings.I am a circuit designer.Not like
>you, you concerntrate on the design using FPGAs.I am designing a new
>family of FPGA using SiGe technology (not CMOS).My boss may present a
>paper in the conference.I am the 3rd author of that regular paper.There
>are lots of mistakes in that paper.But the idea is there.
Pipelined lut or pipelined interconnect? A 20 GHz FPGA is pretty darn
useless if you can't route it.
Do you have the paper online somewhere?
> Will Peter Alfke, Ray Andraka go to attend the conference?
Ray Andraka is on the program committe, he probably will be there.
Peter Alfke has been there in the past, but I don't know.
John_H
If you long for the days of yore when prototyping was done with dips and
wire wrap, the new FPGAs have evolved past these slow ancestors. The edge
rates delivered by the I/O and the sheer dynamic current demands due to the
internals are so strong that the idea of a single VCC and ground pair on
opposite corners of the chip would make many of todays engineers chuckle at
the absurdity. For today's devices we need a significant number of power
and ground pins for both the IO and internal requirements.
If you can get by with the densities offered, the lower cost series devices
such as the Spartan-II and Spartan-IIE may have some quad flat packs that
are more liked by those unhappy with BGAs. It's tougher than socketing a
40-pin dip but you can go much faster than 25 MHz, too.
If you want the densities and performance, the fine pitch BGAs are worth the
manufacturing hassle in this engineer's opinion.
Me, I want more pins on the smaller FPGAs. I've been "buying up" in the
Spartan-II(E) series just to get the pin count even though I could get by
with a 100K or 150k device for my logic needs.
FPGA vendors do a decent job of covering a wide spectrum but there will
always be those who want something "far out" (compared to the majority of
the market).
"David" <gret...@hotmail.com> wrote in message
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