[PATCH] Support for ES2.2 pandaboard
Sebastien Jan
x-loader tree:
X-Loader: Change for the ES2.2 support
Modified the OMAP revision code to only compare
the upper nibble of the most significant byte as this
denotes the OMAP revision.
Signed-off-by: Dan Murphy <dmu...@ti.com>
Signed-off-by: Sebastien Jan <s-...@ti.com>
---
board/omap4430panda/clock.c | 6 +++---
board/omap4430panda/omap4430panda.c | 4 ++--
cpu/omap4/cpu.c | 9 ++++++---
include/asm/arch-omap4/cpu.h | 1 +
include/asm/arch-omap4/omap4430.h | 4 +++-
5 files changed, 15 insertions(+), 9 deletions(-)
diff --git a/board/omap4430panda/clock.c b/board/omap4430panda/clock.c
index 792e5d6..8dd781f 100644
--- a/board/omap4430panda/clock.c
+++ b/board/omap4430panda/clock.c
@@ -423,7 +423,7 @@ static void configure_core_dpll(clk_index)
dpll_param_p = &core_dpll_param_l3_190[clk_index];
else if(omap_revision() == OMAP4430_ES2_0)
dpll_param_p = &core_dpll_param[clk_index];
- else if(omap_revision() == OMAP4430_ES2_1)
+ else if(omap_revision() >= OMAP4430_ES2_1)
dpll_param_p = &core_dpll_param_ddr400[clk_index];
/* Disable autoidle */
@@ -482,7 +482,7 @@ void configure_core_dpll_no_lock(void)
dpll_param_p = &core_dpll_param_l3_190[clk_index];
else if(omap_revision() == OMAP4430_ES2_0)
dpll_param_p = &core_dpll_param[clk_index];
- else if(omap_revision() == OMAP4430_ES2_1)
+ else if(omap_revision() >= OMAP4430_ES2_1)
dpll_param_p = &core_dpll_param_ddr400[clk_index];
/* Disable autoidle */
@@ -530,7 +530,7 @@ void lock_core_dpll_shadow(void)
dpll_param_p = &core_dpll_param_l3_190[6];
else if(omap_revision() == OMAP4430_ES2_0)
dpll_param_p = &core_dpll_param[6];
- else if(omap_revision() == OMAP4430_ES2_1)
+ else if(omap_revision() >= OMAP4430_ES2_1)
dpll_param_p = &core_dpll_param_ddr400[6];
/* CM_SHADOW_FREQ_CONFIG1: DLL_OVERRIDE = 1(hack), DLL_RESET = 1,
diff --git a/board/omap4430panda/omap4430panda.c b/board/omap4430panda/omap4430panda.c
index 5695733..a91e2aa 100644
--- a/board/omap4430panda/omap4430panda.c
+++ b/board/omap4430panda/omap4430panda.c
@@ -252,7 +252,7 @@ static int emif_config(unsigned int base)
ddr_regs = &ddr_regs_380_mhz;
else if (rev == OMAP4430_ES2_0)
ddr_regs = &ddr_regs_200_mhz_2cs;
- else if (rev == OMAP4430_ES2_1)
+ else if (rev >= OMAP4430_ES2_1)
ddr_regs = &ddr_regs_400_mhz_2cs;
/*
* set SDRAM CONFIG register
@@ -602,7 +602,7 @@ static scale_vcores(void)
*(volatile int*)(0x4A307BA0) = 0x316112;
else if (rev == OMAP4430_ES2_0)
*(volatile int*)(0x4A307BA0) = 0x296112;
- else if (rev == OMAP4430_ES2_1)
+ else if (rev >= OMAP4430_ES2_1)
*(volatile int*)(0x4A307BA0) = 0x2A6112;
*(volatile int*)(0x4A307BA0) |= 0x1000000;
while((*(volatile int*)(0x4A307BA0)) & 0x1000000);
diff --git a/cpu/omap4/cpu.c b/cpu/omap4/cpu.c
index 698bbdf..7306fc1 100644
--- a/cpu/omap4/cpu.c
+++ b/cpu/omap4/cpu.c
@@ -63,17 +63,20 @@ unsigned int cortex_a9_rev(void)
unsigned int omap_revision(void)
{
+ unsigned int chip_rev = 0;
unsigned int rev = cortex_a9_rev();
switch(rev) {
case 0x410FC091:
return OMAP4430_ES1_0;
case 0x411FC092:
- if (__raw_readl(0x4a002204) == 0x3b95c02f)
+ chip_rev = (__raw_readl(OMAP44XX_CTRL_ID_CODE) >> 28) & 0xF;
+ if (chip_rev == 3)
return OMAP4430_ES2_1;
+ else if (chip_rev >= 4)
+ return OMAP4430_ES2_2;
else
return OMAP4430_ES2_0;
- default:
- return OMAP4430_SILICON_ID_INVALID;
}
+ return OMAP4430_SILICON_ID_INVALID;
}
diff --git a/include/asm/arch-omap4/cpu.h b/include/asm/arch-omap4/cpu.h
index 94aeb9f..4971ba4 100644
--- a/include/asm/arch-omap4/cpu.h
+++ b/include/asm/arch-omap4/cpu.h
@@ -452,6 +452,7 @@
#define OMAP4430_ES1_0 1
#define OMAP4430_ES2_0 2
#define OMAP4430_ES2_1 3
+#define OMAP4430_ES2_2 4
#ifndef __ASSEMBLY__
/*Functions for silicon revision */
diff --git a/include/asm/arch-omap4/omap4430.h b/include/asm/arch-omap4/omap4430.h
index 2f83621..46003d1 100644
--- a/include/asm/arch-omap4/omap4430.h
+++ b/include/asm/arch-omap4/omap4430.h
@@ -64,7 +64,9 @@
#define OMAP44XX_L4_IO_BASE OMAP44XX_CORE_L4_IO_BASE
/* CONTROL */
-//#define OMAP44XX_CTRL_BASE (OMAP44XX_L4_IO_BASE+0x2000)
+#define OMAP44XX_CTRL_GEN_CORE_BASE (OMAP44XX_L4_IO_BASE+0x2000)
+#define OMAP44XX_CTRL_ID_CODE (OMAP44XX_CTRL_GEN_CORE_BASE + 0x204)
+
#define OMAP44XX_CTRL_BASE 0x4a100000
/* TAP information dont know for 3430*/
--
1.7.1
Gadiyar, Anand
> Mostly inspired from Dan Murphy's patch on dev.omapzoom.org
> x-loader tree:
> X-Loader: Change for the ES2.2 support
>
> Modified the OMAP revision code to only compare
> the upper nibble of the most significant byte as this
> denotes the OMAP revision.
>
> Signed-off-by: Dan Murphy <dmu...@ti.com>
> Signed-off-by: Sebastien Jan <s-...@ti.com>
Applied and pushed out, thanks!
I don't have an ES2.2 Panda, but the changes do look sane to
me. So this is only lightly tested on my part.
- Anand
Jan, Sebastien
> Applied and pushed out, thanks!
>
> I don't have an ES2.2 Panda, but the changes do look sane to
> me. So this is only lightly tested on my part.
Btw, I boot tested on panda ES2.0 and 2.2 + checked DDR freq on both.
I also noticed that the MPU freq is set to 600MHz. We may want to
change that sometime :).
Seb
Koen Kooi
Salvetti has some patches for that :)
>
> Seb
>
> --
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Nishanth Menon
>
>
> Op 29 jan. 2011 om 00:08 heeft "Jan, Sebastien"<s-...@ti.com> het volgende geschreven:
>
>> On Fri, Jan 28, 2011 at 8:25 PM, Gadiyar, Anand<gad...@ti.com> wrote:
>>> Applied and pushed out, thanks!
>>>
>>> I don't have an ES2.2 Panda, but the changes do look sane to
>>> me. So this is only lightly tested on my part.
>>
>> Btw, I boot tested on panda ES2.0 and 2.2 + checked DDR freq on both.
>>
>> I also noticed that the MPU freq is set to 600MHz. We may want to
>> change that sometime :).
>
> Salvetti has some patches for that :)
Just FYI guys who like to switch frequencies with TWL - esp bumping up
voltages to higher ones for 1Gigish freqs, please use VC bypass to do so
- this is specific to TWL as well.. we found a "surprise"(at least for
me as a s/w guy who did not read the specs just a little too closely),
i2c1 access to vddx_vsel registers are implemented in a different
register inside twl compared to the i2c4(SR) register - the sr selection
bit in twl switches the DCDC voltage value selection from i2c1 to i2c4,
unfortunately, the defaults in i2c4 internal twl register would be
different from i2c1 voltage, resulting in a voltage dip when you set the
twl bit (but keep in mind that system needs higher voltage at this
point, causing a system hang).
--
Regards,
Nishanth Menon