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omap4430panda: enable clock gating for M6_DPLL_CORE
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Aaron Carroll  
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 More options Jan 28 2011, 12:30 am
From: Aaron Carroll <aar...@cse.unsw.edu.au>
Date: Fri, 28 Jan 2011 16:30:56 +1100
Local: Fri, Jan 28 2011 12:30 am
Subject: [PATCH] omap4430panda: enable clock gating for M6_DPLL_CORE
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The M6 clock from the core DPLL supplies a clock to the debug domain.
After the core DPLL is locked, the M6 clock appears to stop if clock
gating has been *disabled* for that output (reason unknown).  This
breaks JTAG debugging.

This patch enables clock gating on M6_DPLL_CORE before locking the
core DPLL, so the debugger continues to work.

Signed-off-by: Aaron Carroll <aar...@cse.unsw.edu.au>
---
 board/omap4430panda/clock.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/board/omap4430panda/clock.c b/board/omap4430panda/clock.c
index 792e5d6..2256b32 100644
--- a/board/omap4430panda/clock.c
+++ b/board/omap4430panda/clock.c
@@ -445,7 +445,7 @@ static void configure_core_dpll(clk_index)
                sr32(CM_DIV_M3_DPLL_CORE, 8, 1, 0x1);
                sr32(CM_DIV_M4_DPLL_CORE, 8, 1, 0x1);
                sr32(CM_DIV_M5_DPLL_CORE, 8, 1, 0x1);
-               sr32(CM_DIV_M6_DPLL_CORE, 8, 1, 0x1);
+               sr32(CM_DIV_M6_DPLL_CORE, 8, 1, 0x0);
                sr32(CM_DIV_M7_DPLL_CORE, 8, 1, 0x1);
        }

@@ -504,7 +504,7 @@ void configure_core_dpll_no_lock(void)
                sr32(CM_DIV_M3_DPLL_CORE, 8, 1, 0x1);
                sr32(CM_DIV_M4_DPLL_CORE, 8, 1, 0x1);
                sr32(CM_DIV_M5_DPLL_CORE, 8, 1, 0x1);
-               sr32(CM_DIV_M6_DPLL_CORE, 8, 1, 0x1);
+               sr32(CM_DIV_M6_DPLL_CORE, 8, 1, 0x0);
                sr32(CM_DIV_M7_DPLL_CORE, 8, 1, 0x1);
 //     }

--
1.7.0.4


 
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Discussion subject changed to "[PATCH] omap4430panda: enable clock gating for M6_DPLL_CORE" by Anand Gadiyar
Anand Gadiyar  
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 More options Jan 28 2011, 3:21 am
From: Anand Gadiyar <gadi...@gmail.com>
Date: Fri, 28 Jan 2011 13:51:15 +0530
Local: Fri, Jan 28 2011 3:21 am
Subject: Re: [x-loader] [PATCH] omap4430panda: enable clock gating for M6_DPLL_CORE
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On Fri, Jan 28, 2011 at 11:00 AM, Aaron Carroll <aar...@cse.unsw.edu.au> wrote:
> The M6 clock from the core DPLL supplies a clock to the debug domain.
> After the core DPLL is locked, the M6 clock appears to stop if clock
> gating has been *disabled* for that output (reason unknown).  This
> breaks JTAG debugging.

> This patch enables clock gating on M6_DPLL_CORE before locking the
> core DPLL, so the debugger continues to work.

> Signed-off-by: Aaron Carroll <aar...@cse.unsw.edu.au>

Thanks for sending this.

I discovered this issue a couple of days ago and posted to an internal mailing
list. We don't yet have a clear understanding of why enabling autoidle makes
things work. I've also noticed that you only need to enable autoidle once; you
could disable autoidle later and should still be able to connect with the JTAG.
We'll need a while to get to the bottom of this.

Meanwhile I'll go merge the patch in a bit so folks trying to get JTAG up and
running are unblocked.


 
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