The wide variety of platforms, networks, and uses of
multimedia makes it crucial to provide a flexible architec-
ture for defining and implementing multimedia services and
applications. The system software for the Orlando interac-
tive TV trial uses a distributed objects substrate for com-
munication among applications and services. The service
interfaces are all defined in standard CORBA IDL and imple-
mented in C++. This talk will give an overview of the
Orlando project with particular emphasis on the object sys-
tem infrastructure we have developed and how it is used for
media delivery, database access, and distributed application
development.
This seminar will be broadcast on the MBONE starting at
2:30. The seminar will start promptly at 2:30. 405 Soda
Hall is a relatively small seminar room (approx. 25 seats).
Folks at Berkeley might want to attend the seminar by watch-
ing it on your workstation, if it can receive MBONE
transmissions. For further information on accessing the
MBONE contact see the FAQ (/usr/sww/doc/faq/mbone.faq). You
can also look at the information accessible from
http://roger-rabbit.cs.berkeley.edu/298.html.
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The current schedule of seminars and abstracts are available
on-line in /ucb/csdiv/Seminars-Con/csdiv-seminars on
FTP.CS.berkeley.edu . It is also available via GOPHER. For
ftp instructions and/or to subscribe to UCB Seminars,
send e-mail to talk-r...@cs.berkeley.edu
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Reading smudge-free text typed on a white sheet of
paper is a relatively simple pattern recognition problem.
However, given a videotape of an automobile driving on a
highway, locating and reading the number on the license
plate of the car is a more difficult task. The primary dif-
ficulty comes not from recognizing the characters, but from
finding them in a realistic scene.
Researchers in speech recognition and music analysis
face an analogous problem, when designing systems for use in
realistic environments. My talk will be an overview of
recent research in applying the techniques of visual scene
analysis to auditory problems.
Part 1: UC Berkeley's ``Electronic Environmental Library''
Project
Robert Wilensky
Digital libraries offer the opportunity for a radically
new set of services quite unlike traditional libraries. In
particular, the concept of a limited intermediary is
replaced by a distributed system that can make all available
material universally accessible. We are focussing on the
following critical technologies: (1) Fully automated index-
ing and intelligent retrieval, (2) data base technology to
support digital library applications, (3) more effective
protocols for client/server information retrieval, (4) data
acquisition technology, (5) compression for networked brows-
ing, and (6) new paradigms of user interaction. To explore
these technologies, we are creating a ``California Elec-
tronic Environmental Library''. This testbed comprises a
large collection of diverse kinds of data about the Califor-
nia environment.
Part 2: World Wide Web Access to the Berkeley Distributed
VOD System
Lawrence A. Rowe
The design and implementation of a system will be
described that is capable of storing thousands of hours of
video material that users can play without having to know
the details of where it is located or how to play it. The
design of metadata database interfaces for locating videos
to be played and the problems supporting location indepen-
dent video playback through the World Wide Web will be dis-
cussed. Other issues relating to digitizing, storing, and
playing video and managing a 3-level storage hierarchy will
be discussed.
Many problems in Science and Engineering require the
computation of a few eigenvalues and associated eigenvectors
of a large sparse symmetric matrix. Many powerful numerical
methods for the computation of such eigenpairs are based on
the Lanczos method. Recently, Sorensen proposed a restarted
Lanczos method for this purpose. This method may be viewed
either as a truncated QR algorithm or as a polynomial
acceleration method. Similarly as for the QR algorithm, the
selection of shifts is important for the performance of the
method. We will discuss shift selection strategies suitable
when a few extreme or non-extreme eigenvalues and associated
eigenvectors are desired. The talk presents joint work with
J. Baglama, D. Calvetti and D. So
CS 294-3
Computer Science Colloquium
Dr. James N. Gray
McKay Fellow Lecturer
Computer Science Division
University of California, Berkeley
Parallel Database Techniques for
Scaleable Networks and Platforms (SNAP)
Wednesday, April 12, 1995
4:00 p.m. - 5:00 p.m.
Soda Hall Auditorium, Room 306
Database applications require scaleable designs, ones
that can provide speedup by adding more hardware or scaleup
by adding more hardware and data. Huge transaction process-
ing scaleup has been demonstrated--systems supporting ten
thousand clients are commonplace. There has also been
immense progress on scaling up batch transaction processing
(sometimes called decision support). Prototype systems
built over the last decade are now being commoditized. This
talk describes the concepts and techniques used to distri-
bute data and execution.
These prototype systems partition data among storage
devices, thereby getting embarrassing data parallelism. By
using a dataflow paradigm, they stream data to relational
operators. Since relational operators are closed under com-
position, pipelining the dataflow is easy. The real innova-
tion has been obtaining partition parallelism through inno-
vative algorithms. This talk describes these techniques and
algorithms. It exposes unsolved problems relating to
fault-tolerance, load balancing, and automated operation.
Dr. James N. Gray is a specialist in database and transac-
tion processing computer systems. He worked for IBM, Tandem,
and Digital on projects including System R, SQL/DS, DB2,
IMS-Fast Path, Encompass, NonStopSQL, Pathway, TMF, Rdb,
DBI, and ACMS. He is editor of the "Performance Handbook for
Database and Transaction Processing Systems," and co-author
of "Transaction Processing Concepts and Techniques". He
holds doctorates from Berkeley and Stuttgart, is a member of
the National Academy of Engineering, an ACM Fellow, a member
of the National Research Council's Computer Science and
Telecommunications Board, Editor-in-Chief of the VLDB Jour-
nal, Editor of the Morgan Kaufmann series on Data Manage-
ment, and serves on the Objectivity Technical Advisory
Board. He is currently a MacKay Fellow at Berkeley's Com-
puter Science Division.
CS 298-22
Programming Languages Seminar
Robert Rau
Hewlett-Packard Laboratories
Compiling for Instruction-Level Parallelism
Thursday, April 13, 1995
4:00 p.m. - 5:00 p.m.
505 Soda Hall
Instruction-level parallelism (ILP) is the principal
architectural mechanism by which the microprocessor industry
is currently maintaining the extraordinary rate of increase
of microprocessor performance that we have come to expect.
Both superscalar and VLIW architectures require compilers
which go beyond conventional optimizing compilers by employ-
ing techniques to expose, enhance and exploit ILP. In this
talk, I will discuss techniques for exposing and enhancing
ILP including the single assignment form, memory disambigua-
tion, load-store elimination, and critical path length
reduction. In addition, the talk discusses the structure of
ILP compilers and how it differs from that of conventional
optimizing compilers.
In this talk I will give a collection of results on
nonholonomic motion planning. This has to do with the gen-
eration of feasible paths for systems with non-integrable
constraints: Cartoons will be shown for comic relief. This
talk is primarily based on hard computing tools. However,
it is of interest to understand how these tools can be com-
bined with soft computing tools to produce motion planners
(such an effort been initiated by Charles Coleman, Datta
Godbole and John Lygeros).
The problem of motion planning, applied to wheeled
mobile robots is not just a problem in computational
geometry, because the robot is not allowed to move in all
directions instantaneously. Under the assumption that the
wheels of the car roll without slipping, each axle gives one
constraint on the velocity of the car. We will start off our
presentation with the familiar front-wheel drive car exam-
ple, and show how it can be generalized to apply to a car or
truck towing n trailers, where n is arbitrary. We will also
examine the fire truck, which has two steering wheels in
addition to the driving input. This example will be gen-
eralized to a multi-trailer, multi-steering system. (Joint
work with Dawn Tilbury, Linda Bushnell and Richard Murray).
CS 294-6
Multimedia
David Lundberg
Kaleida Labs.
Object-oriented Multimedia and ScriptX
Monday, April 17, 1995
4:00 p.m. - 5:30 p.m.
306 Soda Hall
The first part of this lecture will present the general
principles of object-oriented (OO) technologyand its appli-
cations in multimedia. Included will be an explanation of
fundamental concepts and terms of OO technology, and the
implications of using OO technology in multimedia applica-
tion development.
The later part of the lecture will summarize the
features and capabilities of ScriptX. ScriptX is a cross-
platform, dynamic, object-oriented programming language
with influences that include CLOS, Smalltalk, and Dylan, as
well as scripting languages such as Lingo and Hypertalk.
ScriptX has been developed specifically for creating mul-
timedia applications. Examples of ScriptX applications
will be shown.
CS 298-10
AI/Vision/Robotics Seminar
Mireille Broucke and Pravin Varaiya
California PATH and EECS, UC Berkeley
Hierarchical Control: The Automated
Highway System Example
Tuesday, April 18, 1995
4:00 p.m. - 5:30 p.m.
Soda Hall Auditorium, room 306
In 1991 Varaiya and Shladover [1] proposed a hierarchi-
cal control architecture for an automated highway system
(AHS). While the architecture proposes a general framework
for an AHS design, specific controllers for each layer have
been developed and have been incorporated in a micro-
simulator called SmartPath. Studies on capacity and safety
have been underway to estimate the performance of the archi-
tecture. Nevertheless, there remains a reliance on full
micro-simulation to understand the behavior of the system.
In this talk we will review the hierarchical architecture of
[1], give some background on hierarchical control, and
report on some preliminary results on how appropriate appli-
cation of abstraction of lower layer behavior can be used to
more realistically estimate one performance measure of the
system: capacity, without necessarily requiring micro-
simulation.
P. Varaiya and S. Shladover. Sketch of an IVHS systems
architecture. PATH Research Report UCB-ITS-PRR-91-3,
Institute of Transportation Studies, University of Califor-
nia, Berkeley, 1991.
Apple Computer Inc. recently announced QuickTime Con-
ferencing, a system extension to the Macintosh operating
system, and an additional component building upon the origi-
nal QuickTime architectural framework. QuickTime Conferenc-
ing (QTC) is both an end-user and developer technology,
focused on multimedia networking and collaborative applica-
tions.
The developer technology consists of a set of open API
specifications for multimedia networking, which allow appli-
cation, software, hardware and network developers to easily
add media conferencing to applications. QTC is compression,
transport, protocol and media device independent. QTC allows
for support of both standards based protocols (such as the
worldwide teleconferencing standard H.320), along with
proprietary protocols. The software allows for both mul-
tiparty conferencing and broadcast type applications sup-
porting point to point, multipoint and multicast connection
models. QTC runs on a variety of networks, such as Ethernet,
ISDN, Token Ring and ATM, and initially uses the AppleTalk
and TCP/IP network protocols. The QTC technology brings with
it some new elements, such as a software based H.261 codec
for PowerPC, and extensions to the AppleTalk protocol for
multicasting on enterprise networks.
The end-user component of QTC is a software applica-
tion, called Apple Media Conference, which allows users to
engage in multiparty conferencing, share and annotate mul-
timedia data, broadcast digital audio and video on to a net-
work and to record conversations into QuickTime movies. Via
support of the H.320 teleconferencing standard along with an
AV plug-in card, QTC users can video conference with users
of H.320 systems in the PC and PC compatible world, allowing
for cross-platform video conferencing interoperability.
QTC is considered a software foundation on which
interoperable conferencing applications can easily be built.
These applications can stay the same, as the underlying net-
work quality of service guarantees improve and the evolving
information highway gets wider and faster digital pipes.
CS 152
Computer Architecture and Engineering
Ken Yeager
Silicon Graphics, Inc.
The MIPS R10000
Friday, April 21, 1995
12:30 p.m. - 2:00 p.m.
306 Soda Hall
This talk will describe the features and configuration
of the MIPS R10000 microprocessor. Its pipelines and major
functional units will be described in detail.
The R10000 is a 4-way superscalar microprocessor which
dynamically executes instructions in five functional units.
Four instructions can be fetched and decoded from a 2-way
set-associative 32K-byte Instruction Cache. To save tem-
porary results and to simplify dependency check logic, logi-
cal (program visible) registers are renamed to 64 physical
registers. Instructions wait in three instruction queues
until all their operands are ready. The Integer Queue
issues instructions to two ALU's. The Floating- Point unit
issues instructions to fully-pipelined multiply and add
units or to iterative divide and square-root units. The
Address Queue issues instructions to a non-blocking 2-way
set-associative 32K-byte data cache. This cache is inter-
leaved in two banks.
Conditional branches are predicted. Instructions are specu-
latively fetched and decoded along the predicted path. Up
to four unresolved branch predictions may be nested.
Although the R10000 does extension out-of-order and
speculative execution, it maintains precise exceptions and
strong memory ordering. It is upward compatible from
R4000-series microprocessors.
The R10000 controls an external 128-bit wide secondary
cache, which uses synchronous static RAMs to provide high
bandwidth for refilling the primary caches. To build mul-
tiprocessor systems, up to four R10000 microprocessors can
be directly connected to a 64-bit transactional system bus.