some questions from IC newbies

[Xiangfu Liu]

Hi

I am learning the ic design recently. just start. still reading some books. :)
now I understand that a digital design will map to standard cells. so I have some question on toped:

1. what are the recommended cell libraries, recommended with toped?
2. for toped are cell libraries written in TELL?
3. what existing cell libraries exist for toped?
4. can stuff like vsclib be used with toped?
5. is "vsclib" the best open cell library? [http://www.vlsitechnology.org/html/vsc_description.html]

Another question is:(just curious :)
what is an exciting chip you think could be manufactured in a 100% open and 100% toped process one day?
what type of chip, what application?

Thanks and Best Regards
Xiangfu

[svilen]

Hi Xiangfu,

You of course understand that a proper answer to those questions will take a lot of typing - at least like writing an article :) So I'll try to be short - at least to give you some clues. Do not expect a definitive answer, but just an opinion.
IC design these days is complex enough process requiring skills from various disciplines. I'm in the business for a long time and I wouldn't claim that I know much about it. A lot of reasons, but in my opinion they can be summarized with the Moore's law and all the consequences from it. Of course it's all possible, because of the progress in Fab processes. I do remember 2 micron process, these days 20 nano process is already a reality. Those might seems just numbers, but there is a tremendous amount of science and technology behind those numbers. And software too. See further comments below.

On 02/07/2013 06:49 AM, Xiangfu Liu wrote:

Hi 

I am learning the ic design recently. just start. still reading some books. :)
now I understand that a digital design will map to standard cells. so I have some question on toped:

1. what are the recommended cell libraries, recommended with toped?

The layout representation of the digital (cell) libraries is probably the simplest one (compared with the rest for synthesys, timing analysis, place and route etc.) and the majority of the digital designers these days haven't even saw the layout of the library they are targeting in their design. Most of the digital libraries today are developed by the factories and are strictly for use by their customers. All the above is to say that a layout tool like Toped can't have preferences about the cell libraries. It shall simply work with any library (or rather its layout view) you can put your hands on. We can import from GDS, CIF and Oasis, which I believe is enough to import any library in existence or to be exact - its layout representation.

2. for toped are cell libraries written in TELL?

Strictly speaking - no. Again - a digital library implies a number of representations (views) and the layout is only one of them. Tell is strictly for layout scripting. The focus of the layout engineer today usually is on the analogue blocks of the IC. The digital part for a long time now is handled by other tools, the process is highly automated there, and the abstraction levels on which the digital designer works are way above the layout. A layout of a digital library alone is virtually useless in today's design process.
The question can be answered of course differently - One shall be able to write a set of Tell scripts which in turn can generate the layout of a cell library. There is no such library so far.
There is a demo library in Tell (work in progress) which I believe targets more common layout tasks in the analog domain rather.

3. what existing cell libraries exist for toped?

I think I answered that already. Any existing cell library shall be able to be imported. Toped doesn't have special requirements about that.

4. can stuff like vsclib be used with toped?

Yes I believe. There is a link on our web page to it.

5. is "vsclib" the best open cell library? [http://www.vlsitechnology.org/html/vsc_description.html]

I can not judge about that. I can only appreciate the effort of the people behind it. It is the only I know that doesn't have severe proprietary license.

Another question is:(just curious :)
  what is an exciting chip you think could be manufactured in a 100% open and 100% toped process one day?
  what type of chip, what application?

Once again - let's be clear. There is no Toped process. There is an IC design process of which layout is a small part of the back end flow, and Toped is trying to be an alternative there. There is no chip that can be designed from scratch by Toped only, and that of course is not the goal. The layout of the chip - yes, but that's it.  I guess Toped already can be helpful in the layouting of some serious blocks or even in the top level of the chips. What application? - it can be anything I guess (not sure about MEMS) .


Regards
Svilen