Suggestions

[moog]

Hi,

I've had a play, there are some immediate things I thought I would
want to do, so here are some suggestions for future enhancements.

It crashes if you enter "" (an empty string) for a text value in a
bus, this should be allowed as you might want to show a bus transition
without any specific value.

Add a name-value mapping for buses, e.g. 00=>nop 01=>add etc.

Add a differential signal/clock type, it would look like a bus and
behave as a signal, but have two names, e.g. sig and #sig.

Allow signals to be sensitve to both edges so that DDR signals can be
shown.

cheers,
Jason.

[dan_fabrizio]

Hi Jason,

See my comments below.

On Jun 29, 1:42 pm, moog <j.a.mor...@gmx.co.uk> wrote:

> Hi,
>
> I've had a play, there are some immediate things I thought I would
> want to do, so here are some suggestions for future enhancements.
>
> It crashes if you enter "" (an empty string) for a text value in a
> bus, this should be allowed as you might want to show a bus transition
> without any specific value.
>

Ok. I will add this feature.

> Add a name-value mapping for buses, e.g. 00=>nop  01=>add etc.
>

Yes, This has been suggested before and will be added soon.

> Add a differential signal/clock type, it would look like a bus and
> behave as a signal, but have two names, e.g. sig and #sig.
>

Ok. I will add this feature to the to-do list.

> Allow signals to be sensitve to both edges so that DDR signals can be
> shown.
>

In the pulse panel, you can select rising and falling edge sync so
when you add pulses, they occur every on each edge.

> cheers,
> Jason.

Let me know if you have any problems or more suggestions.
Thanks, Dan

[Jason Morgan]

Hi Dan,

Thanks for taking interest in my suggestions. I'm no java programmer (did a lot about 15 years ago but little since), but I'm farly ok with Python so if I can help in any way, just ask.

I found the margin object after I wrote the post which I did so after reading the manual which stated that clock jitter was not supported. I assumed this meant signal jitter too - should have played a bit more first.....

On trying to enter an exsting drawing I found I wanted to have a bus which is a state value (enum in VHDL), so a radix is meaningless.  Is there a way to have a bus without a radix?

Cheers,
jason

 

----- Original Message -----

From: dan_fabrizio

Sent: 30/06/11 01:08 AM

To: TimingAnalyzer

Subject: Re: Suggestions

[dan_fabrizio]

Hi Jason,

How are you doing?   

I've been working on the TimingAnalyzer a little more recently and finally getting to your suggestion of adding a differential signal.  Do you know if other programs allow you to add an edge/pulse to both signals at the same time?

I have added a DifferentialSignalDriver which simulates a real driver.   It generates the diff signals from a given input and you can specify propagation delay and skew times.  

Also, would you still be interested in helping with the development of the program.   I could really use some help since there is a lot to do.   Once a library of parts is added,  I want to add some more advanced features like cross clock domain analysis and more analysis type features.  

I have thought to switch to python and C++ and have experimented with C++ and SWIG to generate a DLL or shared lib of the all the data structure control part of the program and use Python for everything else.  

Maybe we could talk about sharing ownership if your interested.   If not,  do you anyone that might be.

Thanks, Dan