The Digital Electronics Blog Google Group

Digital World

2009-01-31T03:59:09Z

Digital World <[link]>
Digital World <[link]>
Digital World <[link]>
Digital World <[link]>
Digital World <[link]>

Interview Question 5

2009-01-11T15:55:27Z

There is a series combination of :
-- pmos---pmos--- pmos----nmos
leftmost pmos is connected to Vdd nmos to gnd and output is taken from
between 2nd and 3rd pmos. When an input combination is such that all
devices are turned on will the output be pulled up or pulled down?

Interview Question 7

2009-01-11T15:57:50Z

1. What happens if we increase the no of contacts or via from one
metal layer to the next?
2. In the design of a large inverter why do we prefer to connect small
transistors in parallel(thus increasing effective width) rather than
make one transistor with large width?
3. Suppose u have a combinational circuit between two flip flops

Interview Question 6

2009-01-11T15:56:06Z

There are three adjacent parallel metal lines. Two out of phase
signals pass through the outer two lines what are the waveforms in the
center line. What will be the waveform if signal in outer lines are in
phase with each other?

Interview Question 4

2009-01-11T15:51:16Z

Consider 2 NMOS transistors stacked one on another as Q1(bottom
transistor, Vb1 is the gate input) and Q2(top transistor, Vb2 is the
gate input). The drain of Q2 is connected to Vdd and the threshold
voltage of the transistor is 0.7V. Vb1=1v, Vb2=2v, When Vdd change
from 5V to 0V, draw the current flow through the transistors VS Vdd.

Interview Question 3

2009-01-11T15:49:48Z

1) Consider a NMOS where drain is connected to Vdd and output is taken
from source(Vo1). Input applied to gate.
2) Consider a PMOS where source is connected to Vdd and output is
taken from drain(Vo2). Input applied to gate.

if Vdd=5v, tell me what are Vo1 and Vo2 when Vin is 5V, 3V, 2.5V and 0V

Interview Question 3

2009-01-09T11:54:15Z

A FSM for an anti-lock brake system accepts two inputs =96 wheel and
time, and generates a single output =96 unlock. The wheel input pulses
high for one clock cycle each time the wheel rotates a small amount.
The time input pulses high for one clock cycle every 10ms. If the
machine detects two time pulses since the last wheel pulse, unlock is

Interview Question 2

2009-01-09T11:53:26Z

In many communication and networking systems such as 100Mbit Ethernet,
the signal transmitted on the communication line uses a non-return-to
zero inverted (NRZI) format. You are to design the circuit that
converts any message sequence of 0s and 1s to a sequence of NRZI
format. The NRZI encoding rules are as follows:

Interview Question

2009-01-09T11:45:38Z

Using adders, shift registers, multiplexers, flip-flops or anything
else that you need, sketch the data path for a 4-bit multiplier that
takes 4 cycles to generate an 8-bit unsigned product from two 4-bit
unsigned inputs.

Looking for solutions to these Interview Question!

2009-01-08T08:26:54Z

[link]
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Some of these questions were asked in my recent interview and was not

What is your idea of making yourself recession prrof?

2009-01-06T15:31:50Z

How can you make yourself recession proof?
Do you intend to learn new things?
Please share your ideas and opinions..