Groups
Groups
Sign in
Groups
Groups
The Digital Electronics Blog
Conversations
Labels
About
Send feedback
Help
The Digital Electronics Blog
1–3 of 3
Welcome to the official discussion group of
The Digital Electronics Blog
Mark all as read
Report group
0 selected
Administrator
,
Karthik Ramanathan
2
Jun 18
Design for Test: Interview question on Stuck at fault
A stuck-at-1 fault on input A of a 3-input AND gate makes A always 1, so the output depends only on B
unread,
Design for Test: Interview question on Stuck at fault
A stuck-at-1 fault on input A of a 3-input AND gate makes A always 1, so the output depends only on B
Jun 18
The Digital Electronics Blog
2
Jun 18
Design Verification: Interview Question
When validating a circuit's behavior under boundary conditions, assertions are generally
unread,
DV
InterviewQuestions
Design Verification: Interview Question
When validating a circuit's behavior under boundary conditions, assertions are generally
Jun 18
The Digital Electronics Blog
2
Jun 18
Design Verification: Interview Question - When do you use VIP's Vs BFM during Design Verification
Verification IPs (VIPs) are comprehensive, reusable components for verifying standard protocols (eg,
unread,
DV
InterviewQuestions
Design Verification: Interview Question - When do you use VIP's Vs BFM during Design Verification
Verification IPs (VIPs) are comprehensive, reusable components for verifying standard protocols (eg,
Jun 18
