Cache statistics

[Yasir]

Hi
I am running swradio-demod application (just for testing) on SFLR for
a 1024Bytes, 8byte block size, and 1-way set associative cache for SH
model. I have set the memory read and write latency to 3 cycles.
Please see the following results that I get
Memory Accesses: 18236
Read Hits: 4336
Read Miss: 191
Write Hits: 11985
Write Miss: 1724
CLK: 5291
ICLK: 59999
Time: 9.999833E-04
Instruction Count: 3400
Signal Transition: 425211
CPU Only Total Energy: 3.275412E-04
Average Power: 3.266946E-04


I have got a question here
Why the number of memory accesses (or cache accesses) is fairly higher
than CLK and even Instruction count. Is that a scaled quantity? If we
assume each instruction doing a single memory operation (which never
happens practically) still the number of memory accesses are higher.
I think it has not very much to do with miss penalty as if we see the
Write Hits only they are higher than CLK.

PS. I have tried various cache configurations and the trend is same.
Regards