Z67-IDE updates!

[Norberto Collado]

All,

Lately I’m being busy at work, working long hours and weekends. Next month, I shall have free cycles to continue the work the Z80 Speed board and to finished debugging some boards that I need to return; my apologies for the delay.

On the Z67-IDE there is a small change and it is to add a DBC (Decimal to Binary Converter) switch and to solder 4 cables to be able to support more than 1 VD per CF card. Today, I only support one VD per CF card, and what that means is that on a 2GB CF card I can only have one instance of HDOS or CP/M; waste of space….

Adding the DBC Switch, then I can take advantage of the extra space on the CF card.

For example:  2GB CF card

1.       I can create four VD’s (0-3 switch setting) which can be used for HDOS or CP/M.

2.       I will be testing the code this week time permitting.

 

On a 4GB CF card I can have the following VD’s;

 

1.       Switch setting from 0 to 6, will give me seven VD’s, which I can install HDOS or CP/M.

Overall, having two 4GB CD cards, I can have fourteen VD’s to boot from, and that is a lot of storage for the H8. This is an advantage for HDOS, having seven bootable disks with 8 HDOS partitions on each disk; 56 bootable HDOS partitions or an equivalent of 56 floppies with a capacity of 1.2MB each.

-          4GB CF card 0 – Allocate to HDOS or CP/M – can have seven boot disks times the partitions.

-          4GB CF Card 1 – Allocated only to CP/M – can have seven boot disks with 15 partitions of 8MB on each disk. This is equivalent of 105 bootable partitions of 8MB each for a total of  840MB.

Trying to access LBA’s beyond the CF card capabilities, the controller will send a check condition indicating that it exceed its storage capabilities. For example; trying to access a 2GB CF card with an LBA that belongs to a 4GB CF card.

On the FW, I‘m planning to enable the serial port to take inputs, so that I can send a command from the HyperTerminal to be able to copy from CF0 card to CF1 card for OS duplication and backup. Also I’m planning to write code to be able to read from an old Winchester drive and then save the data into a CF card to preserved the data that is in the Winchester. I think these are the last FW and hardware change to the Z67-IDE board.

Going forward, I have a need to learn the SPI protocol, and as time permits, I will down size the Z67-IDE controller to a single Microcontroller IC with two MMC cards attached to it. With this setup I do not need any longer the other components found on the original Z67_IDE board. The target is to add this new circuit to the H8-Z67 controller, so there is no need to have two boards. Also it will eliminate the 40 pin connectors and the termination. Eventually I will like to support the DOS file format on the Z67-IDE using the MMC cards. There is a lot of code that I can take advantage to add this feature going forward.

Thanks,

Norberto

[George Farris]

Good stuff Norberto!

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[Norberto Collado]

Hello George,

I tested the VD's changes and it works fine. On a 2GB CF card it took a
while to initialized four drives on a given CF card with CP/M, times 15
partitions to ensure that there was not any data corruption. It is nice to
boot from four different drives on a single 2GB CF card at any time. I test
it with CP/M and it works fine. I will need to test it with HDOS when I get
some time.

I added the FW that support such changes to the website. The link is as
follows;

http://www.koyado.com/Heathkit/Z67-IDE_files/Z67_IDE13.HEX.zip

The hardware changes are;
1. Buy a switch from Jameco; 136558 SWITCH,PB,BCD,10POS,28VDC $2.95 and a
2128059 SWITCH,BCD,END PLATES,2 IN PK, $0.95.

2 Solder 4 wires to the switch. The other end of the wires connects to
pin13,14 & 15 on the DS89C430 IC.
- DBC (D0) switch connects to pin13 side 2 on the DS89C430 microcontroller.
- DBC (D1) switch connects to pin14 side 2 on the DS89C430 microcontroller.
- DBC (D2) switch connects to pin15 side 2 on the DS89C430 microcontroller.
- DBC (D3) switch no connection
- DBC (Ground) switch connects to the GND plane on the Z67-IDE board.

During the weekend, I will send out some pictures on the setup.

BCD Switch: (two 2GB CF Cards)
HDOS / CP/M - CP/M
0 = Boot from VD0 on CF card 0 - Boot from VD0 on CF card 1
1 = Boot from VD1 on CF card 0 - Boot from VD1 on CF card 1
2 = Boot from VD2 on CF card 0 - Boot from VD2 on CF card 1
3 = Boot from VD3 on CF card 0 - Boot from VD3 on CF card 1
4 = illegal
5 = illegal
6 = illegal
7 = illegal
8 = illegal
9 = illegal

BCD Switch: (two 4GB CF Cards)
HDOS / CP/M - CP/M
0 = Boot from VD0 on CF card 0 - Boot from VD0 on CF card 1
1 = Boot from VD1 on CF card 0 - Boot from VD1 on CF card 1
2 = Boot from VD2 on CF card 0 - Boot from VD2 on CF card 1
3 = Boot from VD3 on CF card 0 - Boot from VD3 on CF card 1
4 = Boot from VD4 on CF card 0 - Boot from VD4 on CF card 1
5 = Boot from VD5 on CF card 0 - Boot from VD5 on CF card 1
6 = Boot from VD6 on CF card 0 - Boot from VD6 on CF card 1
7 = illegal
8 = illegal
9 = illegal

Thanks,

Norberto

On 1/23/12 7:12 PM, "George Farris" <farr...@gmail.com> wrote:

> Good stuff Norberto!
>
>

[George Farris]

Hi Norberto,

Thanks I'll give this a try when I get a chance. I am off to a seminar
for a couple of days and then I have family here from the mainland ,over
the weekend, so, I expect I won't get to it until after the weekend but
you never know.

George

[Norberto Collado]

Hello George,

Please wait until I take pictures and with Ken help, he can put a document
together with the details.

Last night it just hit me that everyone that is using the Z67-IDE board is
using the 2GB CF card. I will review the code tonight to enable seven
bootable hard drives per 2GB CF card or VD's. If this works without any data
corruption, then with two 2GB CF cards, you will have 14 bootable hard
drives for HDOS or CP/M (seven for HDOS and seven for CP/M times their
supported partitions.)

I will send out more information tonight on my testing is possible.

Thanks,

Norberto

[Glenn Roberts]

While you're at that Norberto, I notice from the raw dumps of the actual
data on the CF card that every 256 byte sector seems to actually use 512
bytes, the second half of which is filled with the information in the
attached picture. Since I don't have access to the firmware I've never been
able to investigate further but thought I'd mention it. Can this "wasted
space" be eliminated as part of the changes you're making?

- Glenn

Hello George,

Thanks,

Norberto

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[Norberto Collado]

Hello Glenn,

I was expecting this question a loooooooong time ago!

The transfers from the H8-Z67 to the Z67-IDE are 256 bytes long. The
transfers to the IDE bus are 512 bytes long. At the time I was coding, I had
three possibilities;

1. When transferring the 256 bytes from the H8-Z67 to the IDE bus, make two
copies of the same data for backup purposes.

Or

2. Just use it for spare and in the meantime add the controller information.
It is obvious that I selected this approach.

Or

3. When using a single card, use this location as drive 1.

Just to make the coding simple, when I get the LBA from the H8-Z67
controller, I just passed it to the IDE controller as received; no changes.

Using the external BCD switch, then I can control the LBA as needed. For
example a 2GB card can be sliced into 8 hard drives of 262MB. I just need to
verify that the OS does stays within its boundaries when using this approach
to avoid data corruption. Last night I started to test the code for such
changes and it takes time to create each partition. So far from a single 2GB
CF card, I can boot from 4 hard drives. I just need to keep working on it
tonight to finalized initializing the other four drives.

I'm open to new ideas to have a more powerful solution.

On the Z67-IDE FW, I will released it once I feel that is mature and it is
well documented, so that it can be maintain properly by the team. It is
written in assembly language. Also I'm planning to rewrite same assembly
code in BASIC language because it will be easier to maintain. The BASIC
compiler costs about $150.00 dollars and I already have a copy.

Thanks,

Norberto

[George Farris]

Hi all,

Could we please stay away from compilers that are not free to do this.
OR at least if we have the assembly language version. Specialized
compilers have a habit of not being available after a period of time and
it would be nice if in 20 years one could still play with the code and
compile it.

Just a thought.
George

[George Farris]

As a second thought. Norberto could you send the assembly code out
before you change it to BASIC?

George

[Norberto Collado]

 As a second thought. Norberto could you send the assembly code out
before you change it to BASIC?

 

>> I will do so after completing this new code changes and after cleaning up all the debug code that needs to be removed to understand better how everything works together. The assembler I'm using is free and it will be zipped along with the source code.  I expect that when the code is available, that the team will take the Z67-IDE support to the next level. At least all the low level work is done and it is working fine.

 

Just to make you aware, I'm using SCSI-1 definitions which applies to the SASI bus as well, and only supporting the minimum command set required by the H8-Z67 controller.

 

Below is an example;

 

Z67_IDEB        Z67 SASI TO IDE DISK CONTROLLER                                                               OCT-31-10   PAGE 1

                       1    ;-------------------------------------------------------------------------------------------------------
                                                                               ---------------------
                       2    ; Title: Z67_IDE11.ASM
                       3    ;
                       4    ; Z67 XEBEC 1410A (SASI) TO IDE DISK CONTROLLER
                       5    ; Version 2.0
                       6    ; Date: October 31, 2010
                       7    ; Author: Norberto Collado
                       8    ;
                       9    ; Hardware
                      10    ; - CPU: 89C450 @20MHz
                      11    ; - RAM: 1K BYTES
                      12    ; - RS232 INTERFACE
                      13    ; - SASI CONTROLLER: 8155H-2
                      14    ; - IDE CONTROLLER: 82C5AC-2
                      15    ; - SASI INITIATOR ID: 0
                      16    ; - SASI TARGET ID: 1
                      17    ; - Z67 PARITY: ENABLED ODD (as define in the WH-8-37 Controller OPERATION/SERVICE MANUAL 595-2859)
                      18    ; - SASI DATA TRANSFER: ASYNCHRONOUS
                      19    ;
                      20    ; Hardware/Program Features/Limitations
                      21    ;
                      22    ; - Serial ports will use interrupts
                      23    ; - Timer 0 will be used to calculate IDE/SASI delays plus to timeout on loops
                      24    ; - Int 0 will be used for SASI request interrupts from H67 controller (SEL)
                      25    ; Ports:
                      26    ; - Port 1.0 is used for H67 REQ signal
                      27    ; - Port 1.1 is used for H67 ACK signal
                      28    ; - Port 1.2 is used to read H67 PARITY signal
                      29    ; - Port 1.3 is used to detect how many IDE drives are attached to the controller - jumper SD/DD. Jumper on = Single Drive.
                      30    ; - Port 1.4 is used for H67 RESET signal
                      31    ; - Port 1.5 is used to turn "ON" the IDE I/O LED
                      32    ; - Port 1.6 is used for H67 BSY signal
                      33    ; - Port 1.7 is used to write H67 PARITY signal - needed to support HDOS boot
                      34    ; - Port 3.2 is used for H67 SEL signal (Int 0)
                      35    ;
                      36    ; Watchdog Timer:
                      37    ; If system gets hung, the watchdog timer will reset the Controller.
                      38    ;
                      39    ; CD/DVD ROM is not supported by this version of the FW.
                      40    ;
                      41    ;
                      42    ; Logical Addressing
                      43    ; Logical Address = (CylinderAddress*Number of heads per cylinder + Head Address) * (number of sectors p
                                                                               er track + Sector Address)
                      44    ;
                      45    ;
                      46    ; Compiler: ASM51 Z67_IDEx.ASM
                      47    ;               8051 Cross-Assembler, Version 1.2k
                      48    ;                    (c) Copyright 1984-1996 by MetaLink Corporation
                      49    ;
                      50    ;
                      51    ; Credit Where Credit Is Due:
                      52    ; http://www.pjrc.com/tech/8051/ide/
                      53    ; http://www.pjrc.com/tech/8051/ide/wesley.html
                      54    ; http://www.retroleum.co.uk/electronics-articles/an-8-bit-ide-interface/
Z67_IDEB        Z67 SASI TO IDE DISK CONTROLLER                                                               OCT-31-10   PAGE 2

                      55    ; http://borntechi.com/ide.php
                      56    ; http://www.gaby.de/gide/IDE-TCJ.txt
                      57    ; http://www.repairfaq.org/filipg/LINK/F_IDE-tech.html#IDETECH_002
                      58    ;
                      59    ;
                      60    ;
                      61    ;-------------------------------------------------------------------------------------------------------
                                                                               ---------------------
                      62   
                      63   
                      64    ; Primary Controls
                      65            $MOD32
                      66            $TITLE(Z67 SASI TO IDE DISK CONTROLLER)
                      67            $DATE(OCT-31-10)
                      68            $PAGEWIDTH(132)
                      69            $OBJECT(Z67_IDEb.HEX)
                      70    ;
                      71    ; Define Control Characters
  000D                72            CR              EQU     0DH     ;DEFINE ACSII CARRIAGE RET
  000A                73            LF              EQU     0AH     ;DEFINE ASCII LINE-FEED
  001B                74            ESC             EQU     1BH     ;DEFINE ASCII ESC
  007F                75            DEL             EQU     7FH     ;DEFINE ASCII DELETE
  0011                76            CNTL_Q          EQU     11H     ;CONTROL Q
  0013                77            CNTL_S          EQU     13H     ;CONTROL S
                      78           
                      79    ;
                      80    ;Define Conditional Variables
  0001                81            TRUE            EQU     01H     ;TRUE FLAG
  0000                82            FALSE           EQU     00H     ;FALSE FLAG
  0001                83            ON              EQU     TRUE
  0000                84            OFF             EQU     FALSE
  0000                85            INPUT           EQU     FALSE
  0001                86            OUTPUT          EQU     TRUE
                      87    ;
                      88    ; HARDWIRE SASI CONTROLLER ID =1  NOT REQUIRED FOR SASI BECAUSE IT IS USING H67 INTERRUPTS (INT0)
  0002                89            ISASI_ID        EQU     00000010B
                      90    ;
                      91    ;Define RAM BYTES (0 - 1FH) (USING FROM 10H -> 1FH)
  0010                92            SECONDS         EQU     10H     ;SECONDS COUNTER
  0011                93            MSECONDS        EQU     11H     ;MILISECONDS COUNTER
  0012                94            TEMP_BUFFER     EQU     12H     ;TEMPORARY BUFFER
  0013                95            LOW_BYTE        EQU     13H     ;TRANSFER LOW BYTE
  0014                96            HIGH_BYTE       EQU     14H     ;TRANSFER HIG BYTE
  0015                97            DATA_BUFFER     EQU     15H     ;REGISTER A DATA BUFFER
  0016                98            TEMPORARY_R7    EQU     16H     ;TEMPORARY R7 DATA BUFFER
  0017                99            IDE_LBA_3       EQU     17H     ;SAVE THE CONTENTS OF MASTER OR SLAVE DEVICE FOR LBA ACCESS
                     100    ;       SPARE           EQU     18H     ;FREE
  0019               101            PATTERN         EQU     19H     ;DATA PATTERN
  001A               102            TRANSFER_SIZE   EQU     1AH     ;CALCULATES BYTES TO TRANSFER
  001B               103            H67_BOOT_TSIZE  EQU     1BH     ;USE TO TRACK HOW MANY BYTES TO TRANSFER TO THE H67 CONTROLLER
  001C               104            LBA0            EQU     1CH     ;LBA0 - 4 BYTES, 28 bit Logical Block Address
  001D               105            LBA1            EQU     1DH     ;LBA1
  001E               106            LBA2            EQU     1EH     ;LBA2
  001F               107            LBA3            EQU     1FH     ;LBA3
                     108   
                     109    ;
                     110    ;Define RAM BITS (0-7FH)
  0000               111            MESSAGE         EQU     00H     ;0 = NO MESSAGE, 1 = TX IS WORKING     
Z67_IDEB        Z67 SASI TO IDE DISK CONTROLLER                                                               OCT-31-10   PAGE 3

  0001               112            CHAR_IN         EQU     01H     ;CHARACTER IN BIT
  0002               113            TIME_OUT        EQU     02H     ;1 = SASI/IDE TIMEOUT ERROR
  0003               114            DONE            EQU     03H     ;DONE BIT
  0004               115            ONCE            EQU     04H     ;RETRY'S - DO IT 2 TIMES ON CHECK CONDITION
  0005               116            NO_DRIVE        EQU     05H     ;NO DRIVE FLAG
  0006               117            CANCEL          EQU     06H     ;CANCEL ACTIVITY
  0007               118            ABORT           EQU     07H     ;ABORT EXTENDED MESSAGES
  0008               119            JOB_DONE        EQU     08H     ;JOB DONE FLAG FOR SEEK & READ/WRITE
  0009               120            SASI_WRITE      EQU     09H     ;H8 WANTS TO WRITE FROM DISK DRIVE 0/1
  000A               121            XON_XOFF_FLAG   EQU     0AH     ;XON XOFF FLAG
  000B               122            SASI_READ       EQU     0BH     ;H8 WANTS TO READ FROM DISK DRIVE 0/1
  000C               123            CONTROL_FLAG    EQU     0CH     ;CONTROL P, CONTROL T FLAG
  000D               124            NO_MSG          EQU     0DH     ;NO MESSAGE FLAG
  000E               125            CHECK_CONDITION EQU     0EH     ;CHECK CONDITION FLAG
  000F               126            H67_INTERRUPT   EQU     0FH     ;H8 IS BOOTING OR TRYING TO ACCESS HARD DRIVE 0/1
  0010               127            H67_RESET       EQU     10H     ;H67 ASSERTED RESET SIGNAL - MUST BE FOR THE QSCONFIG.COM PROGRAM
  0011               128            IDE_MASTER_HD   EQU     11H     ;IF SET WE HAVE AN IDE MASTER DRIVE
  0012               129            IDE_SLAVE_HD    EQU     12H     ;IF SET WE HAVE AN IDE SLAVE DRIVE
  0013               130            SASI_REQ_SENSE  EQU     13H     ;IF SET, SEND OUT FOUR BYTES OF DATA TO COMPLY WITH HEATHKIT Z67 HARDWARE
  0014               131            SASI_FORMAT     EQU     14H     ;IF SET, FORMAT DRIVE AS DEFINED IN THE MRX-101 SPECS.
                     132           
                     133    ;
                     134    ;Define Internal RAM Allocation for SASI
  0030               135            SAS1_MSG_OUTP   EQU     030H    ;MESSAGE OUT
  0031               136            SASI_COMMAND    EQU     031H    ;COMMAND DESCRIPTOR BLOCK (RESERVED 13 BYTES)
  003E               137            SASI_STATUS     EQU     03EH    ;STATUS
  003F               138            SASI_MSG_INP    EQU     03FH    ;MESSAGE IN
                     139    ;Define LBA RAM locations for calculations
  0040               140            MIN_LBK2        EQU     SASI_MSG_INP + 1 ;MINIMUM LOGICAL - BLOCK BYTE 2
  0041               141            MIN_LBK3        EQU     MIN_LBK2 + 1     ;BYTE 3
  0042               142            MIN_LBK4        EQU     MIN_LBK3 + 1     ;BYTE 4
  0043               143            MIN_LBK5        EQU     MIN_LBK4 + 1     ;BYTE 5
                     144    ;
                     145    ; DEFINE REQ AND ACK SIGNALS
  0090               146            SASI_REQ        BIT     P1.0    ;SASI REQ SIGNAL
  0091               147            SASI_ACK        BIT     P1.1    ;SASI ACK SIGNAL
                     148    ; DEFINE BUSY SIGNALS
  0096               149            SASI_BUSY       BIT     P1.6    ;SASI BUSY SIGNAL
                     150    ; DEFINE SASI SEL SIGNAL
  00B2               151            SASI_SEL        BIT     P3.2    ;SASI SEL SIGNAL
                     152    ; DEFINE H67 RESET SIGNAL
  0094               153            SASI_RESET      BIT     P1.4    ;SASI H67 RESET
                     154    ; DEFINE PARITY SIGNALS
  0097               155            SASI_PARITY_OUT BIT     P1.7    ;SASI PARITY SIGNAL
  0092               156            SASI_PARITY_IN  BIT     P1.2    ;SASI PARITY SIGNAL
                     157    ; DEFINE IDE LED I/O PORT
  0095               158            IDE_LED         BIT     P1.5    ;HIGH TURN ON THE IDE I/O LED
                     159    ; DEFINE AMOUNT OF IDE DRIVES ATTACHED TO THE CONTROLLER
  0093               160            SD_DD           BIT     P1.3    ;HIGH MEANS TWO DRIVES ATTACHED. LOW MEANS A SINGLE DRIVE ATTACH
                                                                               ED
                     161   
                     162    ;
                     163    ; DEFINE STACK POINTER MEMORY LOCATION
                     164    ;
  0052               165            STACK_POINTER   EQU     050H +2 ;STACK POINTER ADDRESS LOCATION
                     166    ;
Z67_IDEB        Z67 SASI TO IDE DISK CONTROLLER                                                               OCT-31-10   PAGE 4

                     167    ; Define SASI 8155H-2 Controller address base - Internal RAM address is from 0000H to 03FFH
  0400               168            SASI_81C55_BA   EQU     00400H                  ;BASE ADDRESS FOR I/O OPERATIONS
  0400               169            SASI_81C55_CMDE EQU     SASI_81C55_BA           ;INTERNAL COMMAND/STATUS REGISTER
  0401               170            SASI_81C55_PA   EQU     SASI_81C55_BA + 1       ;UNIVERSAL I/O PORT A
  0402               171            SASI_81C55_PB   EQU     SASI_81C55_BA + 2       ;UNIVERSAL I/O PORT B
  0403               172            SASI_81C55_PC   EQU     SASI_81C55_BA + 3       ;I/O PORT C (PC)
  0404               173            SASI_81C55_TL   EQU     SASI_81C55_BA + 4       ;TIMER COUNT LOWER POSITION 8 BITS (LSB)
  0405               174            SASI_81C55_TH   EQU     SASI_81C55_BA + 5       ;TIMER COUNT UPPER POSITION 6 BITS AND TIMER MOD
                                                                               E 2 BITS (MSB)
  0000               175            SASI_81C55_PAI  EQU     00000000B               ;PA0-7 - 0=INPUT
  0001               176            SASI_81C55_PAO  EQU     00000001B               ;PA0-7 - 1=OUTPUT
  0000               177            SASI_81C55_PBI  EQU     00000000B               ;PB0-7 - 0=INPUT
  0002               178            SASI_81C55_PBO  EQU     00000010B               ;PB0-7 - 1=OUTPUT
  000C               179            SASI_81C55_PCO  EQU     00001100B               ;PC0-5 - 11=OUTPUT
                     180            ;SASI PHASES
                     181            ;PBO - WRITES SASI I/O
                     182            ;PB1 - WRITES SASI C/D
                     183            ;PB2 - WRITES SASI MSG
                     184            ;PC0 - LED BLINKS IF NO IDE DRIVE PRESENT. LED "ON" IF IDE HD PRESENT
                     185    ;
                     186    ;
                     187    ; Define IDE 82C55AC-2 Controller base addresS
  8000               188            IDE_82C55_BA    EQU     08000H                  ;BASE ADDRESS FOR I/O OPERATIONS
                     189    ;
                     190    ; Hardware Configuration - http://www.pjrc.com/tech/8051/ide/
                     191    ;
                     192    ;8255 chip.  Change these to specify where the 8255 is addressed,
                     193    ;and which of the 8255's ports are connected to which ide signals.
                     194    ;The first three control which 8255 ports have the control signals,
                     195    ;upper and lower data bytes.  The last two are mode setting for the
                     196    ;8255 to configure its ports, which must correspond to the way that
                     197    ;the first three lines define which ports are connected.
                     198    ;
                     199    ;A15 = CS
                     200    ;A14 = A1
                     201    ;A13 = A0
                     202    ;
  8000               203            ide_8255_lsB    EQU     IDE_82C55_BA            ;lower 8 bits
  A000               204            ide_8255_msb    EQU     0A000H                  ;upper 8 bits
  C000               205            ide_8255_ctl    EQU     0C000H                  ;control lines
  E000               206            cfg_8255        EQU     0E000H                  ;configuration
  0092               207            rd_ide_8255     EQU     10010010B               ;ide_8255_ctl out, ide_8255_lsb/msb input
  0080               208            wr_ide_8255     EQU     10000000B               ;all three ports output
                     209   
                     210    ;ide control lines for use with ide_8255_ctl.  Change these 8
                     211    ;constants to reflect where each signal of the 8255 each of the
                     212    ;ide control signals is connected.  All the control signals must
                     213    ;be on the same port, but these 8 lines let you connect them to
                     214    ;whichever pins on that port.
                     215    ;
                     216    ;
  0001               217            ide_a0_line     EQU      001H                   ;direct from 8255 to ide interface
  0002               218            ide_a1_line     EQU      002H                   ;direct from 8255 to ide interface
  0004               219            ide_a2_line     EQU      004H                   ;direct from 8255 to ide interface
  0008               220            ide_cs0_line    EQU      008H                   ;inverter between 8255 and ide interface
  0010               221            ide_cs1_line    EQU      010H                   ;inverter between 8255 and ide interface
  0020               222            ide_wr_line     EQU      020H                   ;inverter between 8255 and ide interface
  0040               223            ide_rd_line     EQU      040H                   ;inverter between 8255 and ide interface
Z67_IDEB        Z67 SASI TO IDE DISK CONTROLLER                                                               OCT-31-10   PAGE 5

  0080               224            ide_rst_line    EQU      080H                   ;inverter between 8255 and ide interface
                     225   
                     226   
                     227    ;Symbolic constants for the ide registers, which makes the
                     228    ;code more readable than always specifying the address pins
                     229    ;
                     230    ;
  0008               231            ide_data        EQU     ide_cs0_line
  0009               232            ide_err         EQU     ide_cs0_line + ide_a0_line
  000A               233            ide_sec_cnt     EQU     ide_cs0_line + ide_a1_line
  000B               234            ide_sector      EQU     ide_cs0_line + ide_a1_line + ide_a0_line
  000C               235            ide_cyl_lsb     EQU     ide_cs0_line + ide_a2_line
  000D               236            ide_cyl_msb     EQU     ide_cs0_line + ide_a2_line + ide_a0_line
  000E               237            ide_head        EQU     ide_cs0_line + ide_a2_line + ide_a1_line
  000F               238            ide_command     EQU     ide_cs0_line + ide_a2_line + ide_a1_line + ide_a0_line
  000F               239            ide_status      EQU     ide_cs0_line + ide_a2_line + ide_a1_line + ide_a0_line
  0016               240            ide_control     EQU     ide_cs1_line + ide_a2_line + ide_a1_line
  0017               241            ide_astatus     EQU     ide_cs1_line + ide_a2_line + ide_a1_line + ide_a0_line
                     242   
                     243   
                     244    ;IDE Command Constants.
                     245    ;
                     246    ;
  0010               247            ide_cmd_recal   EQU     010H            ;IDE RECAL - NOT USED
  0070               248            ide_cmd_seek    EQU     070H            ;SEEK CMD - NOT USED
  0020               249            ide_cmd_read    EQU     020H            ;IDE READ
  0030               250            ide_cmd_write   EQU     030H            ;IDE WRITE
  0091               251            ide_cmd_init    EQU     091H            ;IDE INIT

  00EC               252            ide_cmd_id      EQU     0ECH            ;IDE HD ID
  00A1               253            ide_cmd_DVD_id  EQU     0A1H            ;IDE DVD IDE
  00A0               254            ide_cmd_DVD_pkt EQU     0A0H            ;IDE DVD PKT CMD
  0008               255            ide_cmd_DVD_sr  EQU     008H            ;IDE DVD SOFT RESET
  00E0               256            ide_cmd_spindown EQU    0E0H            ;IDE SPINDOWN
  00E1               257            ide_cmd_spinup  EQU     0E1H            ;IDE SPINUP
                     258    ;
                     259    ;Define External RAM Allocations - USE internal 1K RAM BUFFER
                     260    ;
  0000               261            ONE_K_RAM_START EQU     0000H           ;1K RAM STARTS AT 0000H
  03FF               262            ONE_K_RAM_END   EQU     03FFH           ;1K RAM ENDS AT   03FFH
                     263    ;
  0000               264            BUFFER          EQU     ONE_K_RAM_START ;A 512 BYTE BUFFER
  0201               265            BUFFER_END      EQU     BUFFER + 513    ;LENGTH - 512 BYTES + 1 RESERVED BYTE
  0110               266            COPYRIGHT_BUFFER EQU    272             ;START OF COPYRIGHT BUFFER (256 BYTES FOR CP/M + SPARE BYTE)
                     267    ;
                     268    ;/* SCSI COMMAND OPCODES */
  0000               269            OP_UNITESTRDY   EQU     000H    ;TEST UNIT READY
  0004               270            OP_FORMAT       EQU     004H    ;FORMAT
  0012               271            OP_INQUIRY      EQU     012H    ;INQUIRY
  0003               272            OP_REQ_SENSE    EQU     003H    ;REQUEST SENSE
  0015               273            OP_MODE_SEL     EQU     015H    ;MODE SELECT (6)
  001A               274            OP_MODE_SENSE   EQU     01AH    ;MODE SENSE (6)
  0008               275            OP_READ         EQU     008H    ;READ (6)
  000A               276            OP_WRITE        EQU     00AH    ;WRITE (6)
  002A               277            OP_WRITE_10     EQU     02AH    ;WRITE (10)
  003C               278            OP_READ_BUFFER  EQU     03CH    ;READ BUFFER
  0025               279            OP_READ_CAP     EQU     025H    ;READ CAPACITY
  000B               280            OP_SEEK         EQU     00BH    ;SEEK (6)
Z67_IDEB        Z67 SASI TO IDE DISK CONTROLLER                                                               OCT-31-10   PAGE 6

  001B               281            OP_START        EQU     01BH    ;START/STOP UNIT
  001D               282            OP_SENDDIAGS    EQU     01DH    ;SEND DIAGNOSTICS
  0005               283            OP_READBLOCK    EQU     005H    ;READ BLOCK LIMITS (TAPE)
  001B               284            OP_LOAD         EQU     01BH    ;LOAD/UNLOAD (TAPE)
  0001               285            OP_REWIND       EQU     001H    ;REWIND (TAPE)
  000C               286            OP_VENDOR       EQU     00CH    ;VENDOR UNIQUE
  0024               287            OP_VENDOR1      EQU     024H    ;VENDOR UNIQUE
  0009               288            OP_VENDOR2      EQU     009H    ;VENDOR UNIQUE
  00A0               289            OP_REPORT_LUN   EQU     0A0H    ;REPORT LUNS - NOTE: THE XEBEC CONTROLLER DOES NOT REPORT ANY
  0005               290            OP_CHECK_TRACK_FORMAT   EQU     005H    ;CHECK TRACK FORMAT - RESERVED FOR THE Z67 HEATHKIT CONTROLLER
                     291    ;
                     292    ;/* SCSI COMMAND STATUS CODE */
  0000               293            STS_GOOD        EQU     000H    ;GOOD STATUS
  0002               294            STS_CHECK       EQU     002H    ;CHECK CONDITION
  0008               295            STS_BUSY        EQU     008H    ;TARGET BUSY
  0018               296            STS_CONFLICT    EQU     018H    ;RESERVATION CONFLICT
                     297    ;
                     298    ;/* SCSI MESSAGES STATUS CODES */
  0000               299            MSG_CMD_C       EQU     000H    ;COMMAND COMPLETE
  0002               300            MSG_SAVE        EQU     002H    ;SAVE DATA POINTER
  0003               301            MSG_RESTORE     EQU     003H    ;RESTORE POINTERS
  0004               302            MSG_DISCONNECT  EQU     004H    ;DISCONNECT
  0005               303            MSG_ITRE        EQU     005H    ;INITIATE RECOVERY
  0006               304            MSG_ABORT       EQU     006H    ;ABORT
  0007               305            MSG_REJECT      EQU     007H    ;MESSAGE REJECT
  0008               306            MSG_NOP         EQU     008H    ;NO OPERATION
  0009               307            MSG_PARITY_E    EQU     009H    ;MESSAGE PARITY ERROR
  000C               308            MSG_BUS_DEVRST  EQU     00CH    ;BUS DEVICE RESET
  0080               309            MSG_IDENTIFY    EQU     080H    ;IDENTIFY
                     310   
                     311    ;
                     312    ;/* CPU REGISTERS MEMORY MAP */
                     313    ;       R0 = SPARE
                     314    ;       R1 = INTERNAL RAM ADDRESS
                     315    ;       R2 = CHARACTER IN
                     316    ;       R3 = SASI_DATA_TRANSFER
                     317            SASI_DATA_TRANSFER      SET     R3      ;USE TO CALCULATE DATA TRANSFER SIZE OF 256 BYTES
                     318    ;       R4 = TICK MS COUNTER
                     319    ;       R5 = TICK SECONDS COUNTER
                     320    ;       R6 = DRIVES AVAILABLE
                     321    ;       R7 = COMMAND/STATUS/MESSAGE BYTE COUNTER
                     322    ;
                     323    ; Note: Caution! All the above registers are shared with the SASI and IDE routines.
                     324    ;
                     325    ;/* TRACE FOR DEBUGGING PURPOSES ONLY */
  0000               326            DEBUG           EQU     OFF     ;ON/OFF DEBUG FLAG
  0001               327            H8              EQU     ON      ;ON = H8, OFF= H89
                     328    ;
                     329    ;
0000                 330            ORG             000H            ;EXECUTE PROGRAM
0000 0200CE          331            LJMP            START
                     332   
                     333    ;--------------------------------------------------------------------
                     334    ;Area for interrupt definitions
                     335    ;
                     336   
                     337    ;--------------------------------------------------------------------
Z67_IDEB        Z67 SASI TO IDE DISK CONTROLLER                                                               OCT-31-10   PAGE 7

0003                 338            ORG             003H            ;INT0, EXTERNAL - H67 SEL ASSERTED
                     339    ;
                     340    ;At this point an external interrupt was received at Port 0
                     341    ;
0003 020096          342            LJMP            INTZERO         ;PROCESS THE INTERRUPT
                     343    ;--------------------------------------------------------------------
                     344   
                     345    ;--------------------------------------------------------------------
                     346    ;
000B                 347            ORG             00BH            ;TIMER 0 INTERRUPT
000B 02009F          348            LJMP            TIMER_0
                     349    ;--------------------------------------------------------------------
                     350    ;
                     351   
                     352    ;--------------------------------------------------------------------
0013                 353            ORG             013H            ;INT1, EXTERNAL
0013 32              354            RETI
                     355    ;--------------------------------------------------------------------
                     356   
                     357    ;--------------------------------------------------------------------
0023                 358            ORG             023H            ;SERIAL PORT INTERRUPT FOR TX & RX
                     359    ;/* ROUTINE TO TRANSMIT A MESSAGE */
                     360    ;--------------------------------------------------------------------
0023                 361    TALK:
0023 C0E0            362            PUSH            ACC
                     363            ;CHECK IF INTERRUPT IS FROM TX OR RX
0025 2098D9          364            JB              RI,CHAR_IN
0028                 365    TALK0: 
0028 200A18          366            JB              XON_XOFF_FLAG,TALKEX    ;EXIT XOFF DETECTED
002B 200005          367            JB              MESSAGE,TALK1           ;NO MESSAGE RETURN
002E C299            368            CLR             TI
0030 D0E0            369            POP             ACC                     ;RESTORE ACC
0032 32              370            RETI
0033                 371    TALK1:
0033 C299            372            CLR             TI                      ;ERASE READY FLAG
0035 E4              373            CLR             A                       ;ZERO OFFSET
0036 93              374            MOVC            A,@A+DPTR               ;GET FIRST CHARACTER
0037 B41B04          375            CJNE            A,#ESC,TALK2            ;CHECK IF ESC FOUND    
003A C200            376            CLR             MESSAGE                 ;MESSAGE GONE
003C 8005            377            SJMP            TALKEX                  ;EXIT DONE
003E                 378    TALK2:
003E E4              379            CLR             A                       ;ZERO OFFSET
003F 93              380            MOVC            A,@A+DPTR               ;GET CHARACTER
0040 F599            381            MOV             SBUF,A                  ;MOVE CHARACTER FROM REG A TO SERIAL BUFFER
0042 A3              382            INC             DPTR                    ;INCREMENT MESSAGE COUNTER
0043                 383    TALKEX:
0043 D0E0            384            POP             ACC                     ;RESTORE ACC
0045 32              385            RETI
                     386    ;--------------------------------------------------------------------
                     387   
                     388    ;--------------------------------------------------------------------
0063                 389            ORG             063H                    ;Watchdog Timeout Interrupt
0063 32              390            RETI
                     391    ;--------------------------------------------------------------------
                     392   
                     393    ;--------------------------------------------------------------------
                     394    ;/* ROUTINE TO GET INCOMING CHAR AND PROCESS IT */
                     395    ;--------------------------------------------------------------------
Z67_IDEB        Z67 SASI TO IDE DISK CONTROLLER                                                               OCT-31-10   PAGE 8

                     396    ;
0064                 397    CHARIN:
0064 C298            398            CLR             RI                      ;CLEARS RX INT
0066 E599            399            MOV             A,SBUF
0068 B41404          400            CJNE            A,#14H,NO_CTL_T         ;CHECK FOR CONTROL T
006B D20D            401            SETB            NO_MSG
006D 80D4            402            SJMP            TALKEX
006F                 403    NO_CTL_T:
006F B41004          404            CJNE            A,#10H,NO_CTL_P         ;CHECK FOR CONTROL P
0072 D20D            405            SETB            NO_MSG
0074 80CD            406            SJMP            TALKEX
0076                 407    NO_CTL_P:
0076 B41306          408            CJNE            A,#CNTL_S,NO_CTL_S      ;CHECK FOR CONTROL S
0079 D20A            409            SETB            XON_XOFF_FLAG
007B C201            410            CLR             CHAR_IN                 ;RESET PREVIOUS CHARACTER
007D 80C4            411            SJMP            TALKEX
007F                 412    NO_CTL_S:
007F B41106          413            CJNE            A,#CNTL_Q,NO_CTL_Q      ;CHECK FOR CONTROL Q
0082 C20A            414            CLR             XON_XOFF_FLAG
0084 C201            415            CLR             CHAR_IN                 ;RESET PREVIOUS CHARACTER
0086 80BB            416            SJMP            TALKEX
0088                 417    NO_CTL_Q:
0088 B40304          418            CJNE            A,#03H,NO_CTL_C         ;CHECK FOR CONTROL C
                     419    ;YES IS CONTROL C
008B D206            420            SETB            CANCEL
008D 80B4            421            SJMP            TALKEX
008F                 422    NO_CTL_C:
008F C206            423            CLR             CANCEL                  ;NORMAL OPERATION
0091 FA              424            MOV             R2,A                    ;SAVE CHAR
0092 D201            425            SETB            CHAR_IN                 ;FLAG THAT A CHARACTER IS IN
0094 80AD            426            SJMP            TALKEX                  ;CHECK TX
                     427    ;--------------------------------------------------------------------
                     428   
                     429    ;--------------------------------------------------------------------
                     430    ;/* THIS ARE ALL THE INTERRUPTS DEFINE IN THE 80C31 CPU */
                     431    ;--------------------------------------------------------------------
                     432   
                     433    ;;--------------------------------------------------------------------
                     434    ;/* ROUTINE TO PROCESS INT 0 */
                     435    ;--------------------------------------------------------------------
                     436    ;
0096                 437    INTZERO:
                     438    ;PROCESS H8 INTERRUPT REQUEST
                     439    ;ASSERT BUSY - TARGET MODE
0096 D296            440            SETB            SASI_BUSY               ;SASI BUSY ASSERTED
0098 3096FB          441            JNB             SASI_BUSY,INTZERO       ;CHECK IF SASI BUSY ASSERTED - LOOP UNTIL BIT SET
009B 1204B9          442            LCALL           PROCESS_INT0            ;SEE WHAT THE HEATHKIT H8 COMPUTER WANTS TO DO!
009E 32              443            RETI                                    ;RETURN 

 

[George Farris]

This is awesome Norberto. At least it's easier to move forward if you
get "hit by a bus". My supervisor always uses that line and I hate
it:-)

George

> +DPTR ;GET FIRST CHARACTER

> 0037 B41B04 375 CJNE
> A,#ESC,TALK2 ;CHECK IF ESC FOUND
> 003A C200 376 CLR
> MESSAGE ;MESSAGE GONE
> 003C 8005 377 SJMP
> TALKEX ;EXIT DONE
> 003E 378 TALK2:
> 003E E4 379 CLR
> A ;ZERO OFFSET
> 003F 93 380 MOVC A,@A

> +DPTR ;GET CHARACTER

> --
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[Norberto Collado]

Hello,

I took a 2GB CF Card and Partitioned into 8 disk drives of 256 MB each. After initializing the 8 drives x15 partitions, I started to notice data corruption when using CP/M. I was not clear what was causing the issue and today it became clear to me today that the CP/M SASIX utility allows up to 9999 cylinders. On a 2GB CF card once I get to the high end cylinders then bit 20 and 21 will be set and data corruption will happen. The SASI bus supports up to 21 bits and because of that, I think I have one choice. Leave bits from D0-D20 alone per SASI/SCSI-1 specifications and partition the CF card as follows (Its use is restricted to 21-bit LBAs (1 GiB) and 8-bit Transfer Length fields per specs);

2GB = two drives of 1GB each per CF card (BDC switch selection: 0, 1)

4GB= four drives of 1GB each per CF card (BDC switch selection: 0, 1, 2, 3)

8GB= eight drives of 1GB each per CF card (BDC switch selection:0,1,2,3,4,5,6,7)

For HDOS this should not be an issue because the cylinders, heads and sectors are fixed.

I will retest the above configurations and if everything works fine, then I will support such configuration.

Thanks,

Norberto

 

BDC Switch:	Z67-IDE CPU PINS					CF CARD SIZE in GB
BIT3 (Not Used)	BIT2 (Pin 15)	BIT1 (Pin 14)	BIT0 (Pin 13)		Range
0	0	0	0		1GB
0	0	0	1		2GB	2 GB CF Card
0	0	1	0		3GB
0	0	1	1		4GB	4GB CF Card
0	1	0	0		5GB
0	1	0	1		6GB
0	1	1	0		7GB
0	1	1	1		8GB	8GB CF Card

[Norberto Collado]

Worse comes to worse, someone can build a new board without any issue and write new code for it. The most important parts are the HDOS and CP/M utilities to support the hard drive and they are already available. 

 

Going to a single Microcontroller and two MMC cards will reduce the current code by 50%. For summer, I should have this working and then I can make the H8-Z67 card size the same size as the H8-Z37 card with the heathkit heatsink and integrad both into one controller to support HDOS and CP/M.

 

Thanks,

 

Norberto

 

To unsubscribe from this group, send email to sebhc+un...@googlegroups.com.

[Jack Rubin]

Always nice to have something to look forward to!

best,

Jack

[Norberto Collado]

Hello Glenn,

 

Based on my testing, I'm going to enable the second half of the LBA for OS data. Below is my breakdown using the BCD switch;

 

Switch:            4GB CF CARD  Mapping

 

0                    First 256 bytes for drive 0

1                    Second 256 bytes for drive 1 using same LBA's as drive 0

 

Note: The above is one LBA which is 512 bytes x cylinders x heads x sectors.

 

2                    256 bytes for drive 2

3                    256 bytes for drive 3

 

4                    256 bytes for drive 4

5                    256 bytes for drive 5

 

6                    256 bytes for drive 6

7                    256 bytes for drive 7

 

 

The reads will be fast, but for the writes, I will need to get the 256 bytes from the H8-Z67 controller, then read from the IDE drive 512 bytes and then move the data read into the proper location, and then write the 512 bytes back into the IDE.

 

I hope to have the FW changes as time permits to test it out. The code is in there, it just needs to use the OS data instead of the controller information as shown on your picture.

 

Thanks,

 

Norberto

 

-------- Original Message --------
Subject: RE: [sebhc] Z67-IDE updates!

[Norberto Collado]

Updated Z67_IDE FW to support up to 8 drives with a 4GB CF card and 4 drives with a 2GB CF card. Testing is in progress with CP/M and hopefully everything will work fine.

 

I enabled the second 256 bytes of the LBA to be used as storage as well. I expected to send some pictures later on the HW setup. 

 

Attached document shows before and after FW changes when reading from LBA=0x00000000; one LBA = 512 bytes.

 

Thanks,

 

Norberto

 

[Norberto Collado]

 

I will post the new code after testing is complete.

 

Attached are the CP/M partitions tables to boot from 8 drives with a 4GB CF card or from 4 drives if using a 2GB CD card.

 

HDOS will support the above drive configuration as well.

 

Norberto

 

 

[Norberto Collado]

Preliminary testing under CP/M shows that everything is working fine. So far no data corruption observed. I was able to boot from the eight drives without any issues. More testing needs to be done on each disk partition. So far no HDOS testing done. Also no testing done on the 2GB CF card. It takes time to test all posssible combinations.

 

Attached is the latest FW for testing if interested (pictures will follow later);

 

Features:

 

1. Allows booting from 8 drives under CP/M or HDOS per 4GB CF card. On two 4GB CF cards you get 16 drives to boot from. WOW!

2. Requires adding a Decimal to Binary switch and four cables soldered to the Z67-IDE board.

3. New FW backwards compatible with previous release, even if the switch is not added.

4. Added check condition to alert CP/M, HDOS and the PAM Monitor if the disk access is Illegal. For example if trying to use a 2GB CF card to boot from drive 7, which is out of range; 

IDE ERROR DETECTED

 

%E - REQUESTED SECTORS ID FIELD NOT FOUND

%E - ILLEGAL DISK ADDRESS. ADDRESS IS BEYOND THE MAXIMUM ADDRESS

 

 

Well going to celebrate preliminary testing with a nice cold beer. I never thought of having such much storage capacity for the H8 and H89. :)

 

For next week:

 

Enable the Serial Port to allow duplicating a CF card from Slot 0 (Master IDE) to slot 1 (Slave IDE).

 

Serial Port Support to;

Read_sector;

Read a 512 byte sector, specified by the 32 bit number in the lba variable.

Write_sector

Write a sector to the drive, at the location specified by lba. The 512 bytes from the buffer are written.

Edit_sector

       Read a 512 byte sector, specified by the 32 bit number in the lba variable for editing in hex. Not sure which terminal to use putty under Windows or the H19 terminal.

 

Note: Under CP/M the SASIX.COM utility supports Read_sector, Write_sector and Edit_Sector.

 

Thanks,

 

Norberto

[Glenn Roberts]

Great work Norberto. Looking forward to the pix! 

 

From: se...@googlegroups.com [mailto:se...@googlegroups.com] On Behalf Of Norberto Collado
Sent: Saturday, January 28, 2012 10:39 PM
To: se...@googlegroups.com
Subject: RE: [sebhc] Z67-IDE updates!

 

Preliminary testing under CP/M shows that everything is working fine. So far no data corruption observed. I was able to boot from the eight drives without any issues. More testing needs to be done on each disk partition. So far no HDOS testing done. Also no testing done on the 2GB CF card. It takes time to test all posssible combinations.

--

[Norberto Collado]

 Attached is the document with some pictures. If more details needed, please let me know.

 

Thanks,

 

Norberto :)

 

-------- Original Message --------
Subject: RE: [sebhc] Z67-IDE updates!

[Norberto Collado]

Attached is latest FW updates for the Z67-IDE board.

 

Changes:

1. Display the switch setting during power-on to indicate if cables properly connected. For Example;

 

SWITCH SELECTION: #7 POSITION.

 

VIRTUAL DISK 7 SELECTED.

 

Controller Ready to transfer data to/from IDE DRIVE 0 OR DRIVE 1.

[Norberto Collado]

Added Z67_IDE Gerber files to the website...

http://www.koyado.com/Heathkit/Z67-IDE_files/Z67-IDE-V6.zip

[Norberto Collado]

Now that we have about eight drives per 4GB CF card, I encountered a corner case which at a given drive and a given partition, it will cause the H8-Z67 to hang. It took a while to figure out the issue, but finally found the code in question. The addition of more drives exposed a code bug that has been there since the first release. It was not seen before because I never went above 2002 cylinders in CP/M. Attached is latest FW that fixes this issue. If planning to use this FW for testing, please use new CF cards and secure existing ones until all testing is completed.

 

I will continue testing all the partitions per drive to ensure that we do have a robust solution.

 

Thanks,

 

Norberto