PSpice Gain/phase model for S/H and quantization in software loop (digital SMPS)

[Klaus Kragelund]

Hi

I have implemented a digital SMPS in a Cortex M3 controller. The feedback of the SMPS is done using the TL431 and opto coupler feedback.

The feedback is sampled by the ADC at 10kSa and the sampled values controls the duty-cycle of the SMPS.

It is stable, but I would like to simulate the loop in PSPice. The ADC has sample and hold along with quantiziation that affects the gain/phase. The timer generating the PWM has finite number of different dutycycles and that has a small scale effect also.

I would like to have a model both for transient and ac sweeps.

The ac sweep can be modelled by a sinc function, but how to model the quantization and PWM stage (discrete duty cycles)?

Also, for the transient simulation, the ADC can be modelled simple by a S/H. The quantization can be modelled by a floor function, and for the PWM I need another floor function and a couple of ABMs to model the PWM. But, is there a better method for this?

Thanks

Klaus

[Tim Wescott]

I think you're taking the right approach for the sample & hold and
quantization in the transient simulation.

You're almost right with the sampling in the frequency domain -- you're
not taking aliasing into account, but as long as your output filter
doesn't have appreciable gain above Nyquist then you're all set there.

Traditionally, the way to account for the quantization in the frequency
domain is to model it as noise injection. This makes sense if you think
about it right: the output of a quantization step is your desired signal
plus an error, so you just call that error "noise" and do some analysis.

You would like to be able to model it as being random, which would make
it white in the sampled-time domain, and roughly white but perfectly band-
limited to the sampling rate in the continuous-time domain. In reality,
this only happens if you have enough other noise in the circuit to keep
the quantization agitated -- the more pessimistic approach is to model
the quantization noise as being a sine wave that is 1.09 a quantization
step peak to peak (to account for the fact that it's a square wave), and
at the worst possible frequency. This accounts for the fact that -- if
all else is quiet -- your circuit will oscillate around a quantization
step.

Regardless of whether you assume random or worst-case noise, the way to
analyze it is to treat the quantization gain as a signal that's injected
at the quantizer, do a sweep to find the transfer function from there to
your output, then plug in one of the above two assumptions and see what
the noise is on your output.

Shameless plug: this method of treating quantization is covered briefly
in my book "Applied Control Theory for Embedded Systems". You'll find it
mentioned briefly in chapter 8 (Nonlinear Systems), and in depth in
chapter 10 (Software Implications).

http://www.wescottdesign.com/actfes/actfes.html

If you find that your PWM is too coarse to give good quantization
behavior, you may also find this article to be of benefit:
http://www.embedded.com/design/configurable-systems/4006431/Sigma-delta-
techniques-extend-DAC-resolution

or http://tinyurl.com/9dr5y5p, if you are long-URL challenged.

Note that you need to pay attention to the output filter bandwidth, and
that going to a 2nd-order sigma-delta modulator may be beneficial if you
can stand the code complexity.

--
My liberal friends think I'm a conservative kook.
My conservative friends think I'm a liberal kook.
Why am I not happy that they have found common ground?

Tim Wescott, Communications, Control, Circuits & Software
http://www.wescottdesign.com

[Klaus Kragelund]

Yes, that makes sense. Thats what I'm seeing on the scope, it really can never as opposed to an analog controller regulate to the exact target value.

>
> You would like to be able to model it as being random, which would make
>
> it white in the sampled-time domain, and roughly white but perfectly band-
>
> limited to the sampling rate in the continuous-time domain. In reality,
>
> this only happens if you have enough other noise in the circuit to keep
>
> the quantization agitated -- the more pessimistic approach is to model
>
> the quantization noise as being a sine wave that is 1.09 a quantization
>
> step peak to peak (to account for the fact that it's a square wave), and
>
> at the worst possible frequency. This accounts for the fact that -- if
>
> all else is quiet -- your circuit will oscillate around a quantization
>
> step.
>
>

Good insights, thanks :-)

> Regardless of whether you assume random or worst-case noise, the way to
>
> analyze it is to treat the quantization gain as a signal that's injected
>
> at the quantizer, do a sweep to find the transfer function from there to
>
> your output, then plug in one of the above two assumptions and see what
>
> the noise is on your output.
>
>
>
> Shameless plug: this method of treating quantization is covered briefly
>
> in my book "Applied Control Theory for Embedded Systems". You'll find it
>
> mentioned briefly in chapter 8 (Nonlinear Systems), and in depth in
>
> chapter 10 (Software Implications).
>
>

I just may need to buy that book ;-)

>
>
> If you find that your PWM is too coarse to give good quantization
>
> behavior, you may also find this article to be of benefit:
>
> http://www.embedded.com/design/configurable-systems/4006431/Sigma-delta-
>
> techniques-extend-DAC-resolution
>
>

My code supports sigma delta, but have not tried it yet, since I want to remove that from the closed loop analysis

>
>
> Note that you need to pay attention to the output filter bandwidth, and
>
> that going to a 2nd-order sigma-delta modulator may be beneficial if you
>
> can stand the code complexity.
>
>
>
> --
>
> My liberal friends think I'm a conservative kook.
>
> My conservative friends think I'm a liberal kook.
>
> Why am I not happy that they have found common ground?
>
>

Regards

Klaus

[Mark]

>
> > I have implemented a digital SMPS in a Cortex M3 controller. The
> > feedback of the SMPS is done using the TL431 and opto coupler feedback.
>
> > The feedback is sampled by the ADC at 10kSa and the sampled values
> > controls the duty-cycle of the SMPS.
>
> > It is stable, but I would like to simulate the loop in PSPice. The ADC
> > has sample and hold along with quantiziation that affects the
> > gain/phase.

you can approximate the phase (time delay) using a pspice transmission
line with a delay of 1/2 the sampling period

Mark

[Vladimir Vassilevsky]

"Klaus Kragelund" <klau...@hotmail.com> wrote in message
news:8e588d8c-d9ec-4794...@googlegroups.com...

The sampling delay in the band of interest could be approximated by allpass
filter section. PWM is done with sawtooth waveform and comparator.
Quantization error could be modelled by adding noise; however that won't
tell about possible limit cycles.

VLV