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Joerg  
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 More options Oct 9 2012, 7:18 pm
Newsgroups: sci.electronics.design
From: Joerg <inva...@invalid.invalid>
Date: Tue, 09 Oct 2012 16:18:34 -0700
Local: Tues, Oct 9 2012 7:18 pm
Subject: Re: Dumb question regarding SMPS

k...@att.bizzzzzzzzzzzz wrote:
> On Tue, 9 Oct 2012 14:30:10 -0700 (PDT), "langw...@fonz.dk" <langw...@fonz.dk>
> wrote:

>> On 9 Okt., 22:53, Joerg <inva...@invalid.invalid> wrote:
>>> k...@att.bizzzzzzzzzzzz wrote:
>>>> On Tue, 09 Oct 2012 09:49:57 -0700, Joerg <inva...@invalid.invalid> wrote:
>>>>> John Larkin wrote:
>>>>>> On Mon, 08 Oct 2012 21:06:21 -0700, Joerg <inva...@invalid.invalid>
>>>>>> wrote:
>>>>>>> John Larkin wrote:
>>>>>>>> On Mon, 08 Oct 2012 18:59:46 -0700, Joerg <inva...@invalid.invalid>
>>>>>>>> wrote:
>>>>>>>>> Jim Thompson wrote:
>>>>>>>>>> On Mon, 8 Oct 2012 20:21:35 -0400, "Martin Riddle"
>>>>>>>>>> <martin_...@verizon.net> wrote:
>>>>>>>>>>> "Jim Thompson" <To-Email-Use-The-Envelope-I...@On-My-Web-Site.com> wrote
>>>>>>>>>>> in messagenews:5396789ln236d2okjpbcv2m1on9gmejtqn@4ax.com...
>>>>>>>>>>>> On Mon, 08 Oct 2012 12:03:12 -0700, John Larkin
>>>>>>>>>>>> <jlar...@highlandtechnology.com> wrote:
>>>>>>>>>>>>> On Mon, 8 Oct 2012 09:52:15 -0700 (PDT), spamtrap1888
>>>>>>>>>>>>> <spamtrap1...@gmail.com> wrote:
>>>>>>>>>>>>>> If someone has a free moment, I'd like to know:
>>>>>>>>>>>>>> I'm on my third laptop right now. Every time I plugged my Dell's "fat
>>>>>>>>>>>>>> snake" into the wall, I drew quite an arc. The Lenovo's arc was not
>>>>>>>>>>>>>> noticeable, but now I get a noticeable arc with my new HP -- not as
>>>>>>>>>>>>>> big as the Dell's, however.
>>>>>>>>>>>>>> I know FA about switch mode power supplies, obviously, so I wonder
>>>>>>>>>>>>>> 1. What produces the arc?
>>>>>>>>>>>>>> 2. Why would different power supplies produce different arcs (does it
>>>>>>>>>>>>>> just depend on output power capability)?
>>>>>>>>>>>>>> 3. Why is there no arc when I pull the plug from the outlet?
>>>>>>>>>>>>> Dumb switching power supplies have a bridge rectifier and a big
>>>>>>>>>>>>> electrolytic filter capacitor. If you plug them in near the peak of
>>>>>>>>>>>>> the AC line waveform, the charging current will spark.
>>>>>>>>>>>>> Better supplies, with inrush limiters, or PFC (power factor corrected)
>>>>>>>>>>>>> front-ends, have much less inrush charge.
>>>>>>>>>>>>> Ask Jim for details. He is *so good* at designing switching power
>>>>>>>>>>>>> supplies.
>>>>>>>>>>>> Indeed I am >:-)
>>>>>>>>>>> I like the ucc28019a. works like a champ. Undervoltage lockout too ;)
>>>>>>>>>>> Cheers
>>>>>>>>>> So does the L6561.  But poorly documented and no model; and ST ignores
>>>>>>>>>> my pounding on their door >:-)
>>>>>>>>>> If I could make major changes I'd design ST out _forever_!
>>>>>>>>> Might be the new normal. I want to design in a National video driver,
>>>>>>>>> LMH6722. Has a thermal pad under its belly. In the datasheet they forgot
>>>>>>>>> to mention where its s'posed to be connected to. Probably V- but I'd
>>>>>>>>> rather make sure. Filed a support ticket with the new owner TI on 10/2.
>>>>>>>>> Got a service request number.
>>>>>>>>> Today is 10/8 and (finally! ... or so I thought) there was a message in
>>>>>>>>> the inbox this morning. A form letter, merely saying that, tada, a
>>>>>>>>> service request number has been issued. New number: Same as the old number.
>>>>>>>>> So I responded politely as to when I might be expecting an answer. No
>>>>>>>>> response all day.
>>>>>>>>> Hurumph!
>>>>>>>> Get one and ohm it out.
>>>>>>> No kidding, that may be the only way :-(
>>>>>>> Just made a CAD model for a 100-TQFP processor. Now I know why I chose
>>>>>>> to become an analog guy and not a digital one.
>>>>>> Do you mean a PCB decal, or an actual Autocad sort of thing?
>>>>>> PADS makes IC decals really fast, for sort of standard things with
>>>>>> rows of numbered pins.
>>>>>> Are you doing 3D Solidworks sort of physical modeling? It is fun to
>>>>>> finally spin that stuff around in space, or take a virtual walk under
>>>>>> the IC pins.
>>>>> No, just the schematic library part and footprint. A hundred pins, most
>>>>> of which have names like this:
>>>>> (OC0A/OC1C/PCINT7)PB7
>>>>> One typo and all hell can break loose because the routing resources in
>>>>> those uCs are sparse and can be unforgiving. Just had a major
>>>>> re-shuffling in one of them on another project, not because of an error
>>>>> but for a feature change. When those get maxed out in port pins the
>>>>> design can slow down as much as Van Ness at rush hour, mainly because of
>>>>> routing compromises.
>>>> You *should* be able to either grab the names from a spreadsheet or
>>>> cut-n-paste from a datasheet.  The vendors often have models already built
>>>> that can be used for a starting place, too.
>>> Only for some CAD packages, if at all. My CAD has a lot of the Atmels,
>>> just not this big one.
>> which one?

>>>>                                 ... OTOH, our CAD people demand that
>>>> chips look on the schematic like they do on the board - no functional
>>>> partitioning (except BGAs, for some reason).
>>> I insist on the same, I really hate netlist-style schematics where the
>>> front axle is on page 17 which the left front wheel it on page 32.
>>> Exceptions are logic gate and opamp multi-packs, of course. And I never
>>> use large BGAs, those can spell doom in a hi-rel environment.

>> isn't reliabily and BGAs something that was perfected many years ago?

> Sure, at least in the larger packages.  Joerg is living in the '80s.  They
> even worked well then but many didn't have the process down.

>> for something like a big FPGA I think it it makes sense to put core
>> power, jtag
>> configuration and such on one symbol and each bank on a separate
>> symbol

> Agree 100%.  Even "small" 144-pin QFPs are a mess when they're shown as one
> big box on a page with wires everywhere.  Joerg probably doesn't like busses,
> either (someone here objected to them a while back).

Actually I do like buses a lot. Especially the ones with comfy seats and
WiFi on board :-) ... Just kidding, I do like buses on schematics.

> I often break FPGAs up by I/O bank, if I haven't got the design very far
> along.  If know how it's going to flow, I'll break it up that way.  I can
> still do that with BGAs, but not QFPs or QFNs.  The CPoE has some really
> strange ideas on how a schematic is to look.  The CAD system sucks, too, but
> that's a different topic.  ;-)

Ever dealt with Asian-style schematics? Oh, there is still some white on
the page, let's cram the preamp in there. Then you start following a
line clear across the page and it goes to ... ground!

--
Regards, Joerg

http://www.analogconsultants.com/


 
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