>> I am  trying  to  analyse the  working  of  a  conventional phase
  >> frequency detector(NAND  based).I  would  like  to  know  why the
  >> deadzone is  high  for  it  specially  when  the  reset  delay is
  >> large.Please could anyone help me out with it atleast an article.

  > There is no dead zone. I've posted my simulated results on  abse -
  > if you don't get abse, here is the raw data - plot it on a log-log
  > plot. I've  measured real PFDs in the past,  and  obtained similar
  > results (although  I couldn't get down to 10fs in the  lab). These
  > are not exotic circuits, and contain no cleverness.

  Hi Mike,

  If your charge pump is fast enough to follow the width of  the reset
  pulse, then you will have no deadband, as your simulation shows.

  However, if  the charge pump is slower than the reset  pulse  to the
  latches, you  will have deadband. This is described in  my  PLL Data
  Recovery patent 3,810,234 (1974)

    "The basic configuration of the phase detector includes two D-type
    flip-flops with  feedback  to restore both  to  the  initial state
    after both  have  been  clocked.  A  delay  in  the  feedback path
    establishes the  minimum  time  that either  flip-flop  is  in the
    clocked state,  thus  establishing  a  minimum  time  that current
    sources are switched on."

    "The delay  is  selected to insure that both  current  sources are
    first turned fully on before they are turned off. This  feature is
    necessary to  eliminate dead-band whereby the phase  detector does
    not respond  properly to small phase errors (or  time differences)
    between the two input signals to the phase detector."

    http://www3.sympatico.ca/add.automation/patents/3810234.htm

  Thus, adding  delay  to  the feedback path  can  solve  the deadband
  problem. This  behavior is also described in the  Maxim  MAX9382 app
  note in the section "Eliminating Dead-Band Behavior"

    http://www.maxim-ic.com/appnotes.cfm/appnote_number/1130

  However, the added delay reduces the maximum operating  frequency of
  the pfd, as described in the above Maxim app note.

  Another solution is to filter the pfd output pulses so the following
  integrator does  not  have to track fast pulses from  the  pfd. This
  approach is  described  in Jim's MC4044 data sheet in  Figure  22 on
  page 6-30:

    http://www.analog-innovations.com/SED/MC4044_MC4344.pdf

  Here, the filter resistor is split in half and a small cap  is added
  to ground.  The  error amplifier no longer has to  respond  to short
  pulses, and  it can follow the low frequency variations  without the
  penalty of deadband.

  This solution  would be essential when operating at very  high clock
  frequencies. For example, OnSemi has phase/frequency  detectors that
  operate beyond 2GHz, such as the 100EP40.

  Clearly a charge pump is not feasible at these frequencies. The same
  solution is  shown in Fig. 11 on page 6 where a small  ripple filter
  is used  to remove the fast switching transients from the  pfd. Here
  are two url's in case the first one doesn't work:

    http://www.onsemi.co.jp/pub/Collateral/AND8040-D.PDF
    http://home.zcu.cz/fel/kae/aes2/pll/pdf/AND8040-D.pdf

  Another solution  that has been proposed is to add an offset  to the
  phase detector to move the quiescent operating point away from zero.
  This can  work,  but it will increase the  reference  sideband spurs
  present in  the vco output. An example is shown in Fig. 3 on  page 2
  of the National Semiconductor app note AN885:

    http://www.national.com/an/AN/AN-885.pdf

  There still  remains  an   amazing   amount  of  confusion  over the
  operation of the classic phase frequency detector. For  example, one
  poster in  this  thread  claimed the pfd  could  enter  a metastable
  condition, which would cause errors in the loop. This is echoed in a
  post on the SI-LIST:

    http://www.freelists.org/archives/si-list/08-2003/msg00314.html

  In actual  operation,  the  classic pfd  cannot  enter  a metastable
  state. The  latches or d-flops can only turn on when  a  clock pulse
  arrives. They  are turned off by the reset pulse, which has  a width
  of twice  the prop delay around the path. This guarantees  they will
  both be  reset properly.

  Another possible confusion is shown in the datasheet for the Philips
  HCT9046A chip:

    http://www.philipslogic.com/products/hc/pdf/74hct9046a.pdf

  On page 6, they claim that feeding a capacitor with a current source
  eliminates the  deadband  in  the   phase  detector.  They  show the
  resulting performance in Fig. 11 on page 11.

  The truth  is  the  cmos current sources  still  have  a  turnon and
  turnoff delay. If they are faster than the reset pulse from the pfd,
  there will  be no deadband. But just because it is a  current source
  feeding a  cap does not guarantee this will be true. The  prop delay
  of the phase detector has to be taken into account.

  So if  the  ic manufacturers can't get it right, it  looks  like the
  confusion over the deadband problem will continue as a topic  in the
  newsgroup.

  Hope this helps!

Best Wishes,