Phase frequency detector
Deepthi
detector(NAND based).I would like to know why the deadzone is high for
it specially when the reset delay is large.Please could anyone help me
out with it atleast an article.
Jim Thompson
wrote:
What IS "a conventional phase frequency detector (NAND based)"? Most
P-F Detectors are D-Flop (or equivalent latch logic) based.
...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice:(480)460-2350 | |
| E-mail Address at Website Fax:(480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
Mike
> On 25 May 2004 18:09:06 -0700, raodeep...@yahoo.com (Deepthi)
> wrote:
>
>>I am trying to analyse the working of a conventional phase frequency
>>detector(NAND based).I would like to know why the deadzone is high for
>>it specially when the reset delay is large.Please could anyone help me
>>out with it atleast an article.
>
> What IS "a conventional phase frequency detector (NAND based)"? Most
> P-F Detectors are D-Flop (or equivalent latch logic) based.
>
Didn't the Motorola PFD data sheet use only NAND gates? The schematic shown
in Gardner (2nd ed, p. 123) uses only nand gates, connected (mostly) as SR
flip-flops.
As for the dead-zone, that's another matter (and will have to wait for a
later reply).
-- Mike --
Jim Thompson
Sure... "(or equivalent latch logic) based"... the "9-gate-wonder"
;-)
Gardner, p123, is missing some connections.
Tim Wescott
If you mean a three-state phase detector with "up", "down" and
"middling" outputs, the usual cause of a deadzone is because of
metastability. The basic construction of the phase detector uses two
clocks, so both latches can go off at the same time (giving you
simultaneous up and down). There's a circuit that detects this and
resets both latches, but it's subject to metastability. Since the
target operating point of the usual PLL is to be right at he point of
simultaneous clocking you're just asking for trouble.
Motorola advertises "special circuitry" to minimize this metastability.
IIRC they're pretty vague about exactly how they do it. Phillips uses
some sort of clever pulse-absorption circuit that causes the PLL set
point to be about 10% away from the danger zone -- it's in their
synthesizer data sheets.
--
Tim Wescott
Wescott Design Services
http://www.wescottdesign.com
Winfield Hill
>
> Mike wrote:
>
>> Didn't the Motorola PFD data sheet use only NAND gates? The schematic
>> shown in Gardner (2nd ed, p. 123) uses only nand gates, connected
>> (mostly) as SR flip-flops.
>>
>> As for the dead-zone, that's another matter (and will have to wait
>> for a later reply).
>
> ;-)
>
> Gardner, p123, is missing some connections.
Is the 9-gate circuit shown on the MC4044 18-page datasheet
complete? It uses six 2-input NANDs and three 3-input NANDs.
BTW, that's a very nice detailed datasheet, who wrote it?
Thanks,
- Win
(email: use hill_at_rowland-dot-org for now)
Jim Thompson
<Winfiel...@newsguy.com> wrote:
>Jim Thompson wrote...
>>
>> Mike wrote:
>>
>>> Didn't the Motorola PFD data sheet use only NAND gates? The schematic
>>> shown in Gardner (2nd ed, p. 123) uses only nand gates, connected
>>> (mostly) as SR flip-flops.
>>>
>>> As for the dead-zone, that's another matter (and will have to wait
>>> for a later reply).
>>
>> Sure... "(or equivalent latch logic) based"... the "9-gate-wonder"
>> ;-)
>>
>> Gardner, p123, is missing some connections.
>
> Is the 9-gate circuit shown on the MC4044 18-page datasheet
> complete? It uses six 2-input NANDs and three 3-input NANDs.
It is complete.
>
> BTW, that's a very nice detailed datasheet, who wrote it?
>
> Thanks,
> - Win
Back in those days Motorola had a very good
applications/technical-writing department managed by Lothar Stern, but
Ron Treadway and I (as designers of the MC4044) worked very closely
with them to create the data sheet.
Likewise for the MC4024 (voltage-controlled multivibrator) and its ECL
equivalents (the core of the TTL version is actually ECL). I designed
the MC4024 and the ECL version (MC1658), as well as the MC1648, a
sinusoidal VCO (tank + varactor) with ECL clock outputs.
Most of these parts have been now been re-done in 12000 series PECL.
Winfield Hill
>
> Winfield Hill wrote:
>> Jim Thompson wrote...
>>> Mike wrote:
>>>
>>>> Didn't the Motorola PFD data sheet use only NAND gates? The
>>>> schematic shown in Gardner (2nd ed, p. 123) uses only nand gates,
>>>> connected (mostly) as SR flip-flops.
>>>>
>>>> As for the dead-zone, that's another matter (and will have to wait
>>>> for a later reply).
>>>
>>> Sure... "(or equivalent latch logic) based"... the "9-gate-wonder"
>>> ;-)
>>>
>>> Gardner, p123, is missing some connections.
>>
>> Is the 9-gate circuit shown on the MC4044 18-page datasheet
>> complete? It uses six 2-input NANDs and three 3-input NANDs.
>
> It is complete.
>
>> BTW, that's a very nice detailed datasheet, who wrote it?
>
> technical-writing department managed by Lothar Stern, but
> Ron Treadway and I (as designers of the MC4044) worked very
> closely with them to create the data sheet.
>
> Likewise for the MC4024 (voltage-controlled multivibrator) and its
> ECL equivalents (the core of the TTL version is actually ECL).
> I designed the MC4024 and the ECL version (MC1658), as well as the
> MC1648, a sinusoidal VCO (tank + varactor) with ECL clock outputs.
>
> Most of these parts have been now been re-done in 12000 series PECL.
The MC1648 oscillator, discontinued. "Replaced" by the MC12148,
also discontinued shortly thereafter. Damn nice parts, bummer.
Jim Thompson
<Winfiel...@newsguy.com> wrote:
Follow the links on my website to Lansdale... they're making damn near
everything I ever designed.
Can't find what you want? Contact Dale Lillard
<dale[at]lans[remove-this-text]dale[dot]com>
Tim Wescott
> On 26 May 2004 10:14:05 -0700, Winfield Hill
> <Winfiel...@newsguy.com> wrote:
-- snip --
>
> Back in those days Motorola had a very good
> applications/technical-writing department managed by Lothar Stern, but
> Ron Treadway and I (as designers of the MC4044) worked very closely
> with them to create the data sheet.
>
> Likewise for the MC4024 (voltage-controlled multivibrator) and its ECL
> equivalents (the core of the TTL version is actually ECL). I designed
> the MC4024 and the ECL version (MC1658), as well as the MC1648, a
> sinusoidal VCO (tank + varactor) with ECL clock outputs.
>
> Most of these parts have been now been re-done in 12000 series PECL.
>
> ...Jim Thompson
I alluded to this in my other post -- Phase-frequency detectors like
these are reputed to have problems with metastability when the two
pulses hit at exactly the same time. Since you have a loop filter that
is working _very hard_ to make just this situation occur, what did you
have to do to prevent it from being an issue? Or was the alleviation of
this trait just left as an exercise to the reader?
I vaguely remember either the 4044 datasheet or one of the synthesizer
data sheets making some statement of cleverness in relation to fixing
this, but I can only find a 12040 datasheet today, and it tells me to
look at the 4044 for the theory!
Winfield Hill
>
> Winfield Hill wrote:
>
>> The MC1648 oscillator, discontinued. "Replaced" by the MC12148,
>> also discontinued shortly thereafter. Damn nice parts, bummer.
>
> near everything I ever designed.
>
> Can't find what you want? Contact Dale Lillard
> <dale[at]lans[remove-this-text]dale[dot]com>
Good info.
Winfield Hill
>
> I vaguely remember either the 4044 datasheet or one of the synthesizer
> data sheets making some statement of cleverness in relation to fixing
> this, but I can only find a 12040 datasheet today, and it tells me to
> look at the 4044 for the theory!
I'll post it on a.b.s.e. for you (and any others who're interested).
Tim Wescott
Big file.
Thanks.
Jeroen Belleman
> I alluded to this in my other post -- Phase-frequency detectors like
> these are reputed to have problems with metastability when the two
> pulses hit at exactly the same time. Since you have a loop filter that
> is working _very hard_ to make just this situation occur, what did you
> have to do to prevent it from being an issue? Or was the alleviation of
> this trait just left as an exercise to the reader?
>
> I vaguely remember either the 4044 datasheet or one of the synthesizer
> data sheets making some statement of cleverness in relation to fixing
> this, but I can only find a 12040 datasheet today, and it tells me to
> look at the 4044 for the theory!
>
Well, I've been hit by this problem using the MC12140. It would throw
a metastibility fit a few times per second, causing little random
excursions in the PLL phase error, much like popcorn noise.
I 'solved' it by having the loop run with a small constant phase
error, injecting a small constant signal into the integral term of
the loop filter.
Jeroen Belleman
Winfield Hill
>
>Winfield Hill wrote:
>
>> Tim Wescott wrote...
>>
>>> I vaguely remember either the 4044 datasheet or one of the synthesizer
>>> data sheets making some statement of cleverness in relation to fixing
>>> this, but I can only find a 12040 datasheet today, and it tells me to
>>> look at the 4044 for the theory!
>>
>> I'll post it on a.b.s.e. for you (and any others who're interested).
>
Yep, 18 chock-filled pages.
Hmm, what's chock anyway? Hmm, chokkefulle. Hmm. Nuts. Hmmmmm.
Mike Monett
Win,
Only two files showed up at this server - parts 2 and 5. The datasheet
does not seem to be available anywhere on the web, and due to its
historical significance, I wonder if Jim would volunteer to post it on
his site?
Best Wishes
Mike
Winfield Hill
>
> Winfield Hill wrote ...
>> Tim Wescott wrote...
>>>
>>> I vaguely remember either the 4044 datasheet or one of the synthesizer
>>> data sheets making some statement of cleverness in relation to fixing
>>> this, but I can only find a 12040 datasheet today, and it tells me to
>>> look at the 4044 for the theory!
>>
>> I'll post it on a.b.s.e. for you (and any others who're interested).
Ron Treadway and Jim Thompson's MC4044 - data sheet - MC4044_MC4344.pdf
> Win,
>
> Only two files showed up at this server - parts 2 and 5. The datasheet
> does not seem to be available anywhere on the web, and due to its
> historical significance, I wonder if Jim would volunteer to post it on
> his site?
You're asking me? Anyway, yes the MC4044 has a great 18-page datasheet,
perhaps Jim will grab it from abse (or I can email it) and serve it up,
properly named so search engines can find it. Meantime, anyone wants a
copy, I'll be happy to send one (1.34MB on disk = 1.9MB attachment?),
just email me here, fixing the address, hill_at_rowland-dot-org
Spehro Pefhany
<Winfiel...@newsguy.com> wrote:
1 : a wedge or block for steadying a body (as a cask) and holding it
motionless, for filling in an unwanted space, or for blocking the
movement of a wheel
2 : a heavy metal casting (as on the bow or stern of a ship) with two
short horn-shaped arms curving inward between which ropes or hawsers
may pass for mooring or towing.
Best regards,
Spehro Pefhany
--
"it's the network..." "The Journey is the reward"
sp...@interlog.com Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog Info for designers: http://www.speff.com
Mike
> On Wed, 26 May 2004 08:13:51 -0700, Mike <mi...@nospam.com> wrote:
>
>>On Tue, 25 May 2004 22:10:41 -0700, Jim Thompson wrote:
>>
>>> On 25 May 2004 18:09:06 -0700, raodeep...@yahoo.com (Deepthi)
>>> wrote:
>>>
>>>>I am trying to analyse the working of a conventional phase frequency
>>>>detector(NAND based).I would like to know why the deadzone is high for
>>>>it specially when the reset delay is large.Please could anyone help me
>>>>out with it atleast an article.
>>>
>>> What IS "a conventional phase frequency detector (NAND based)"? Most
>>> P-F Detectors are D-Flop (or equivalent latch logic) based.
>>>
>>
>>Didn't the Motorola PFD data sheet use only NAND gates? The schematic shown
>>in Gardner (2nd ed, p. 123) uses only nand gates, connected (mostly) as SR
>>flip-flops.
>>
>>As for the dead-zone, that's another matter (and will have to wait for a
>>later reply).
>>
>>-- Mike --
>
> Sure... "(or equivalent latch logic) based"... the "9-gate-wonder"
> ;-)
DOH! I've always been able to speak in complete sentences... Maybe one of
these days I'll learn to read in complete sentences as well...
> Gardner, p123, is missing some connections.
>
Damn... That explains everything! ;-)
(Since it's a textbook, I figured those were left "as an exercise for the
reader").
-- Mike --
Jim Thompson
You probably have some system noise problems.
Jim Thompson
<Winfiel...@newsguy.com> wrote:
>Mike Monett wrote...
>>
[snip]
>> Only two files showed up at this server - parts 2 and 5. The datasheet
>> does not seem to be available anywhere on the web, and due to its
>> historical significance, I wonder if Jim would volunteer to post it on
>> his site?
>
> You're asking me? Anyway, yes the MC4044 has a great 18-page datasheet,
> perhaps Jim will grab it from abse (or I can email it) and serve it up,
> properly named so search engines can find it. Meantime, anyone wants a
> copy, I'll be happy to send one (1.34MB on disk = 1.9MB attachment?),
> just email me here, fixing the address, hill_at_rowland-dot-org
>
> Thanks,
> - Win
Win,
I have it here in an old Moto PLL data book, but you've created a
perfectly good PDF, and I'm a long way from filling my space
allocation on the website, so I'll put it up on the S.E.D/Schematics
Page of my website.
Thanks for the memories ;-)
Deepthi
I need help understanding why the deadzone of a conventional phase
frequency detector which consists of 6 two input NAND gates and 3
three input NAND gates is high specially when the reset delay path is
large
Deepthi
Mike
There is no dead zone. I've posted my simulated results on abse - if you
don't get abse, here is the raw data - plot it on a log-log plot. I've
measured real PFDs in the past, and obtained similar results (although I
couldn't get down to 10fs in the lab). These are not exotic circuits, and
contain no cleverness.
Time Charge
Diff. Output
(ps) (fC)
0.01 0.001
0.03 0.003
0.1 0.011
0.3 0.034
1 0.113
3 0.338
10 1.123
30 3.428
100 11.229
300 37.325
-- Mike --
Jim Thompson
<Winfiel...@newsguy.com> wrote:
[snip]
> perhaps Jim will grab it from abse (or I can email it) and serve it up,
> properly named so search engines can find it.
[snip]
> Thanks,
> - Win
>
> (email: use hill_at_rowland-dot-org for now)
Done.
Mike Monett
>
> On 27 May 2004 04:32:52 -0700, Winfield Hill
> <Winfiel...@newsguy.com> wrote:
>
> [snip]
> > perhaps Jim will grab it from abse (or I can email it) and serve it up,
> > properly named so search engines can find it.
> [snip]
> > Thanks,
> > - Win
> >
> > (email: use hill_at_rowland-dot-org for now)
>
> Done.
>
> ...Jim Thompson
Great. Thanks to both of you.
Best Wishes,
Mike Monett
Mike Monett
> On 25 May 2004 18:09:06 -0700, Deepthi wrote:
>> I am trying to analyse the working of a conventional phase
>> frequency detector(NAND based).I would like to know why the
>> deadzone is high for it specially when the reset delay is
>> large.Please could anyone help me out with it atleast an article.
> There is no dead zone. I've posted my simulated results on abse -
> if you don't get abse, here is the raw data - plot it on a log-log
> plot. I've measured real PFDs in the past, and obtained similar
> results (although I couldn't get down to 10fs in the lab). These
> are not exotic circuits, and contain no cleverness.
Hi Mike,
If your charge pump is fast enough to follow the width of the reset
pulse, then you will have no deadband, as your simulation shows.
However, if the charge pump is slower than the reset pulse to the
latches, you will have deadband. This is described in my PLL Data
Recovery patent 3,810,234 (1974)
"The basic configuration of the phase detector includes two D-type
flip-flops with feedback to restore both to the initial state
after both have been clocked. A delay in the feedback path
establishes the minimum time that either flip-flop is in the
clocked state, thus establishing a minimum time that current
sources are switched on."
"The delay is selected to insure that both current sources are
first turned fully on before they are turned off. This feature is
necessary to eliminate dead-band whereby the phase detector does
not respond properly to small phase errors (or time differences)
between the two input signals to the phase detector."
http://www3.sympatico.ca/add.automation/patents/3810234.htm
Thus, adding delay to the feedback path can solve the deadband
problem. This behavior is also described in the Maxim MAX9382 app
note in the section "Eliminating Dead-Band Behavior"
http://www.maxim-ic.com/appnotes.cfm/appnote_number/1130
However, the added delay reduces the maximum operating frequency of
the pfd, as described in the above Maxim app note.
Another solution is to filter the pfd output pulses so the following
integrator does not have to track fast pulses from the pfd. This
approach is described in Jim's MC4044 data sheet in Figure 22 on
page 6-30:
http://www.analog-innovations.com/SED/MC4044_MC4344.pdf
Here, the filter resistor is split in half and a small cap is added
to ground. The error amplifier no longer has to respond to short
pulses, and it can follow the low frequency variations without the
penalty of deadband.
This solution would be essential when operating at very high clock
frequencies. For example, OnSemi has phase/frequency detectors that
operate beyond 2GHz, such as the 100EP40.
Clearly a charge pump is not feasible at these frequencies. The same
solution is shown in Fig. 11 on page 6 where a small ripple filter
is used to remove the fast switching transients from the pfd. Here
are two url's in case the first one doesn't work:
http://www.onsemi.co.jp/pub/Collateral/AND8040-D.PDF
http://home.zcu.cz/fel/kae/aes2/pll/pdf/AND8040-D.pdf
Another solution that has been proposed is to add an offset to the
phase detector to move the quiescent operating point away from zero.
This can work, but it will increase the reference sideband spurs
present in the vco output. An example is shown in Fig. 3 on page 2
of the National Semiconductor app note AN885:
http://www.national.com/an/AN/AN-885.pdf
There still remains an amazing amount of confusion over the
operation of the classic phase frequency detector. For example, one
poster in this thread claimed the pfd could enter a metastable
condition, which would cause errors in the loop. This is echoed in a
post on the SI-LIST:
http://www.freelists.org/archives/si-list/08-2003/msg00314.html
In actual operation, the classic pfd cannot enter a metastable
state. The latches or d-flops can only turn on when a clock pulse
arrives. They are turned off by the reset pulse, which has a width
of twice the prop delay around the path. This guarantees they will
both be reset properly.
Another possible confusion is shown in the datasheet for the Philips
HCT9046A chip:
http://www.philipslogic.com/products/hc/pdf/74hct9046a.pdf
On page 6, they claim that feeding a capacitor with a current source
eliminates the deadband in the phase detector. They show the
resulting performance in Fig. 11 on page 11.
The truth is the cmos current sources still have a turnon and
turnoff delay. If they are faster than the reset pulse from the pfd,
there will be no deadband. But just because it is a current source
feeding a cap does not guarantee this will be true. The prop delay
of the phase detector has to be taken into account.
So if the ic manufacturers can't get it right, it looks like the
confusion over the deadband problem will continue as a topic in the
newsgroup.
Hope this helps!
Best Wishes,
Mike Monett
Winfield Hill
>
> Thanks for the memories ;-)
Life is good. Memories are good.
Mike
> "The delay is selected to insure that both current sources are
> first turned fully on before they are turned off. This feature is
> necessary to eliminate dead-band whereby the phase detector does
> not respond properly to small phase errors (or time differences)
> between the two input signals to the phase detector."
It's not necessary to fully turn on _either_ current source, much less both
of them.
> Thus, adding delay to the feedback path can solve the deadband
> problem. This behavior is also described in the Maxim MAX9382 app
> note in the section "Eliminating Dead-Band Behavior"
>
> http://www.maxim-ic.com/appnotes.cfm/appnote_number/1130
This is classic. The author states, "One of the potential shortcomings of
the charge pump-based loop filter arrangement is the minimum pulse width
that the filter inputs can respond to. A typical phase detector output
condition at lock is a series of very short pulses on the "up" and "down"
outputs. If these pulses are too narrow for the loop filter to "see"
then the result will be a loop dead-band characteristic about zero phase."
First, the author defines a pulse width, that the filter can't see, then
shows what happens when the filter doesn't see it.
Second, we're talking about a PFD dead zone, not a charge pump or filter
dead zone. But forget that: even if we extend the argument to charge pumps
and loop filters, the argument is still garbage.
Third, to reset your flip-flops you have to generate positive outputs from
both flops, which have to propagate through an AND gate back to the reset
input. If the AND gate output is high, both inputs are high, and that means
both inputs to your charge pump are high, and that means the charge pump is
doing something. Unless you try really hard, you _can't_ make a reset pulse
so narrow that your charge pump won't respond.
Fourth, I challenge anyone to design a passive loop filter that can't see
an input.
> Another solution is to filter the pfd output pulses so the following
> integrator does not have to track fast pulses from the pfd. This
> approach is described in Jim's MC4044 data sheet in Figure 22 on
> page 6-30:
>
> http://www.analog-innovations.com/SED/MC4044_MC4344.pdf
>
> Here, the filter resistor is split in half and a small cap is added
> to ground. The error amplifier no longer has to respond to short
> pulses, and it can follow the low frequency variations without the
> penalty of deadband.
The small capacitor is generally added to reduce ripple. It is as much an
integrator as the large integrating capacitor - either they can both follow
the PFD output pulses or neither one can.
There _are_ potential issues with the circuit shown, but they have to do
with the op-amp, not the loop filter components.
> This solution would be essential when operating at very high clock
> frequencies. For example, OnSemi has phase/frequency detectors that
> operate beyond 2GHz, such as the 100EP40.
>
> Clearly a charge pump is not feasible at these frequencies. The same
> solution is shown in Fig. 11 on page 6 where a small ripple filter
> is used to remove the fast switching transients from the pfd. Here
> are two url's in case the first one doesn't work:
I fail to see why a charge pump is infeasible when an ECL flip-flop is. The
flip-flop is made from charge pumps; the only difference is that the
flip-flop charge pumps aren't driving a loop filter.
> Another solution that has been proposed is to add an offset to the
> phase detector to move the quiescent operating point away from zero.
> This can work, but it will increase the reference sideband spurs
> present in the vco output. An example is shown in Fig. 3 on page 2
> of the National Semiconductor app note AN885:
>
> http://www.national.com/an/AN/AN-885.pdf
At -78dBc, the spurs are unlikely to be due to forced offset, and the
National App-Note doesn't mention forced offset. I think their performance
is pretty damn good for a PFD _without_ any forced offset.
> In actual operation, the classic pfd cannot enter a metastable
> state.
Finally, we agree on something.
> The latches or d-flops can only turn on when a clock pulse
> arrives. They are turned off by the reset pulse, which has a width
> of twice the prop delay around the path. This guarantees they will
> both be reset properly.
Actually, it doesn't. Just wait until you've built one that doesn't.
-- Mike --
Bill Sloman
> Mike wrote:
>
> > On 25 May 2004 18:09:06 -0700, Deepthi wrote:
>
> >> I am trying to analyse the working of a conventional phase
> >> frequency detector(NAND based).I would like to know why the
> >> deadzone is high for it specially when the reset delay is
> >> large.Please could anyone help me out with it atleast an article.
>
> > There is no dead zone. I've posted my simulated results on abse -
> > if you don't get abse, here is the raw data - plot it on a log-log
> > plot. I've measured real PFDs in the past, and obtained similar
> > results (although I couldn't get down to 10fs in the lab). These
> > are not exotic circuits, and contain no cleverness.
<snip>
> Another possible confusion is shown in the datasheet for the Philips
> HCT9046A chip:
>
> http://www.philipslogic.com/products/hc/pdf/74hct9046a.pdf
>
> On page 6, they claim that feeding a capacitor with a current source
> eliminates the deadband in the phase detector. They show the
> resulting performance in Fig. 11 on page 11.
>
> The truth is the cmos current sources still have a turnon and
> turnoff delay. If they are faster than the reset pulse from the pfd,
> there will be no deadband. But just because it is a current source
> feeding a cap does not guarantee this will be true. The prop delay
> of the phase detector has to be taken into account.
>
> So if the ic manufacturers can't get it right, it looks like the
> confusion over the deadband problem will continue as a topic in the
> newsgroup.
You should have read a bit more of the Philips data sheet. Their
trick, as detailed on page 8 of the application note, very
specifically in the note on Fig.8 at the bottom of the page, is that
the postive and negative current sources are overlapped by about
15nsec, and their actual claim is that feeding a capacitor with their
pair of overlapped current sources eliminates the deadband, which does
sound consistent with your story.
Are you really claiming that Philips didn't got it right on the basis
of an over-hasty glance at their data sheet? Or do you have more
persuasive evidence, like some measurements on the 9046 in action?
According to Tom Bruhns, Agilent list the 74HCT9046 as one of their
approved parts, so it seems likely that it does what Philips claim.
-------
Bill Sloman, Nijmegen
Ian Buckner
"Spehro Pefhany" <spef...@interlogDOTyou.knowwhat> wrote in message
news:kqsbb05tm9qbhn2fh...@4ax.com...<snip >
> > Yep, 18 chock-filled pages.
> >
> > Hmm, what's chock anyway? Hmm, chokkefulle. Hmm. Nuts. Hmmmmm.
>
> 1 : a wedge or block for steadying a body (as a cask) and holding it
> motionless, for filling in an unwanted space, or for blocking the
> movement of a wheel
>
> 2 : a heavy metal casting (as on the bow or stern of a ship) with
two
> short horn-shaped arms curving inward between which ropes or hawsers
> may pass for mooring or towing.
>
>
>
> Best regards,
> Spehro Pefhany
I believe the origin for "chock-full" is when the "wedge" as in Spef's
definition 1 is used to hold shut, for example, the hatch on a ships
hold. If there are so many nuts in there that the chocks
have to be used to force the hatch cover closed.....
Regards
Ian
Winfield Hill
>
> Mike Monett wrote ...
Mike, I agree with Bill. After some thought, do you as well?
Mike Monett
Win, Bill,
Thanks for your posts. Sorry for the delay - Google news was down
recently but may be OK now.
Don't get me wrong - I'm not claiming the Philips part doesn't work.
But the datasheet does not offer a way to prove it.
Most large companies require a comprehensive incoming test procedure
when qualifying a part to ensure it meets requirements. But the key
parameters that guarantee zero deadband are not specified in the
datasheet, and Philips offers no tests to confirm it.
The "about 15nS" overlap is hardly a specification, and the
datasheet does not attempt to measure it. We might like to assume
the risetimes of the current pumps would be faster than the overlap
time, but these are not specified or measured.
One could construct a special test fixture to measure the phase
detector transfer curve and ensure it is linear through zero. But
the test is slow and costly, fairly difficult to implement, and does
not tell how close the chip is to failure.
What is needed is a way to measure the overlap time and compare it
to the current pump risetimes. If the risetimes are faster than the
overlap time, the phase detector will be linear through zero. The
difference between these two parameters tells how much margin is
available before failure.
It turns out there might be a way to get the needed information.
Fig. 19 on page 19 shows the 3-state enable and disable times for
PC2_OUT.
These tests are intended to measure the prop delays, but they can be
used instead to measure the risetime of each charge pump. The test
for tPZH also gives the risetime of the positive current pump, and
tPZL gives the risetime of the negative current pump.
However, the overlap time cannot be measured in this test since the
charge pump currents cancel at zero phase error.
Fortunately, the lock detect output, PCP_OUT on pin 1, can be used
to measure the overlap time at zero phase error. If needed, this
information could be plotted as a function of temperature and supply
voltage to ensure proper operation under all conditions.
So with some ingenuity and a bit of luck, it is possible to measure
the deadband performance of the chip after all. The tests are simple
enough that anyone could afford to do them. With care, it should be
possible to obtain a wealth of additional information, such as the
degree of balance between the current pumps, the phase offset at
zero error, and the amount of internal crosstalk in the chip.
Best Regards,
Mike
Mike Monett
> On Thu, 27 May 2004 22:30:49 -0400, Mike Monett wrote:
>
> > "The delay is selected to insure that both current sources are
> > first turned fully on before they are turned off. This feature is
> > necessary to eliminate dead-band whereby the phase detector does
> > not respond properly to small phase errors (or time differences)
> > between the two input signals to the phase detector."
>
> It's not necessary to fully turn on _either_ current source, much less both
> of them.
Mike,
There's lots of interesting things in your post, but perhaps it would
be better to take each item one at a time.
Can you give more info on your statement above? Any web-accessible
links with diagrams or other data?
Mike
Mike
Here's part of a post I made at Designer's Guide. The charge pump transfer
function is that of a diff pair: Iee/(1+exp(-v/Vt)). Feed the UP and DN
voltages into the diff pair, subtract the output currents, and integrate. I
assumed 100uA for Iee and 25mV for Vt. Similar results (although not so
easy to calculate) hold for CMOS diff pairs.
------
It's been pointed out that I refer to seconds as phase error. I assume that
an astute reader can perform the necessary conversion.
------
Consider the case of an ECL PFD with an RC response and a negative phase
error at the inputs. The UP output will rise to
Vp(-1+2(1-exp(-(Tw+Tp)/tau))) then decay with time constant tau. The DN
output will begin Tp later and will charge to Vp(-1+2(1-exp(-Tw/tau)))
before beginning to discharge. Tw is the time UP and DN are both on, tau is
the RC time constant, Tp is the phase error, and Vp is the peak output
voltage. This is a resonably good model for an ECL PFD.
By choosing Tw and Tp to be small values, the PFD output can be given any
desired peak amplitude. For example, choosing tau=1ns, Tw=300ps, and
Tp=100ps, the peak values of the UP and DN outputs are limited to
approximately -72mV. Assuming the thermal voltage of a diff pair, Vt, is
25mV, the diff pair in a charge pump input will only have switched 5.3% of
its current, yet the charge transferred is still linear.
Here are the results of a Mathcad model of these equations. For each Tp, I
integrate the charge pump output to get the total charge transferred to the
loop filter.
Tp (ns) Charge Transferred (fC)
--------- --------------------------
0.00001 0.00019364
0.00003 0.00058096
0.0001 0.001937
0.0003 0.005814
0.001 0.019
0.003 0.059
0.01 0.2
0.03 0.636
0.1 2.617
0.3 13.676
1 98.066
3 322.108
If you plot this data on a log-log plot, you'll find that it's remarkably
linear, even down at 10ps phase error, and even though only 5.3% of the
current is being switched at 10ps phase error. There's little point in
going to smaller phase errors, since the charge transferred at 10ps is only
1.2 electrons. I suppose an argument could be made that there's a dead zone
for phase errors that result in less than 1 electron transferred, but I
think that's different than what we're discussing here.
Some nonlinearity shows up for errors larger than 1ns, but that's a
different effect.
------
There was one response that referenced CMOS Fractional-N Synthesizers, by
DeMuer and Steyaert. They talk about a dead zone, but offer no circuit
details, and show a phase-error plot that is completely symmetrical about
zero. All in all, it doesn't make a very convincing case.
In any event, the point is that the charge-pump diff pairs are only
switching 5% of their current, not 100%, the charge transferred is still
linear, and there's no sign of a dead zone all the way down to one single
electron being transferred to the loop filter.
-- Mike --
Mike Monett
> On 6 Jun 2004 20:02:51 -0700, Mike Monett wrote:
>
> > Mike <mi...@nospam.com> wrote in message news:<1u61o2ish33nu$.1s0asz91...@40tude.net>...
> >> On Thu, 27 May 2004 22:30:49 -0400, Mike Monett wrote:
> >>
> >>> "The delay is selected to insure that both current sources are
> >>> first turned fully on before they are turned off. This feature is
> >>> necessary to eliminate dead-band whereby the phase detector does
> >>> not respond properly to small phase errors (or time differences)
> >>> between the two input signals to the phase detector."
> >>
> >> It's not necessary to fully turn on _either_ current source, much less both
> >> of them.
> >
> > Mike,
> >
> > There's lots of interesting things in your post, but perhaps it would
> > be better to take each item one at a time.
> >
> > Can you give more info on your statement above? Any web-accessible
> > links with diagrams or other data?
>
> Here's part of a post I made at Designer's Guide. The charge pump transfer
> function is that of a diff pair: Iee/(1+exp(-v/Vt)). Feed the UP and DN
> voltages into the diff pair, subtract the output currents, and integrate. I
> assumed 100uA for Iee and 25mV for Vt. Similar results (although not so
> easy to calculate) hold for CMOS diff pairs.
[...]
> -- Mike --
Mike, I'm having difficulty following your description. Do you have a
schematic and timing diagrams, perhaps a SPICE model? Are there
separate current pumps for each direction? How do you translate the
ECL output voltages to the levels needed to drive the current sources?
Mike
Bill Sloman
<snip>
Philips almost certainly has the necessary information, but the
details of the performance of the transistors and interconnections in
whatever fabrication process they are using at the moment to make the
9046 is the kind of proprietary information that they are not likely
to release. As far as I know, most IC manufacturers have extensive and
reliable simulation packages for their integrated circuit processes,
validated by detailed measurements on simple test circuits, and
probably by point measurements within more complicated circuits.
When I worked at Cambridge Instruments - 1982-1991 - I did a lot of
work on a couple of specialised stroboscopic electron microscopes
intended for making just this sort of measurement on unencapsulated
integrated circuits, in competition with the mechanical probes long
used to to the same sort of work.
------
Bill Sloman, Nijmegen
Mike
Not anything in a legally shareable form.
> Are there separate current pumps for each direction?
Yes.
> How do you translate the ECL output voltages to the levels needed to
> drive the current sources?
I don't, but this is an IC, so an ECL gate can have multiple output levels
(3 levels is common in a 5V process), each one diode drop lower than the
previous one. The charge pumps are two diff pairs, one up, one down. The up
output goes through a PNP or PFET current mirror and ties to the down
output. I'm assuming the mirror is perfect (for the purposes of
transferring charge, it's pretty close).
-- Mike --
Mike
> On 7 Jun 2004 03:36:53 -0700, Mike Monett wrote:
>> Mike, I'm having difficulty following your description. Do you have a
>> schematic and timing diagrams, perhaps a SPICE model?
Here's a Python program that does the calculations and reports the results.
You'll have to undo the word wrapping on some lines. If you aren't familiar
with Python, the main thing you need to know is that indentation is
critical: don't mess with it.
#
# Python script to simulate UP and DN PFD outputs into bipolar diff pairs.
# The UP and DN signals are RC exponentials with RC time constant tau.
#
from math import *
#
# Units. These are a convenient fiction: it's easier to read 150*mV than
150e-3.
#
V = 1
mV = 1.0e-3
mA = 1.0e-3
uA = 1.0e-6
ns = 1.0e-9
ps = 1.0e-12
fs = 1.0e-15
pC = 1.0e-12
fC = 1.0e-15
Vt = 25.0*mV # Thermal voltage
Vo = 150.0*mV # ECL single ended output level (output swings between
+/-Vo)
Iee = 100*uA # Diff pair tail currents
tstep = 10.0*fs # simulation time step
tstop = 10.0*ns # simulation stop time
tdly = 0.0*ns # time delay before start of phase error
twid = 0.3*ns # width of UP and DOWN if the phase error is zero
tau = 1.0*ns # ECL output time constant - the PFD outputs rise and
fall
# with this time constant
#
# Phase error (expressed as a time error)
#
terr = [ 10*fs, 30*fs, 100*fs, 300*fs, 1*ps, 3*ps, 10*ps, 30*ps, 100*ps,
300*ps, 1*ns ]
Qtot = [] # Total charge transferred
Kmax = floor(tstop/tstep)+1; # Number of steps in simulation
for tphi in terr:
Q = 0.0
time = 0.0
k = 0
print tphi,
while k < Kmax:
#
# Leading edge of the PFD output - total pulse width is twid + tphi
#
if time < tdly:
xp = 0.0
elif time < tdly + twid + tphi:
xp = 1.0 - exp(-(time-tdly)/tau)
else:
xp = (1.0 - exp(-(twid+tphi)/tau))*exp(-(time-tdly-twid-tphi)/tau)
Vp = Vo*(-1.0 + 2.0*xp)
#
# Trailing edge fo the PFD output - total pulse width is twid
#
if time < tdly + tphi:
xn = 0.0
elif time < tdly + twid + tphi:
xn = 1.0 - exp(-(time-tdly-tphi)/tau)
else:
xn = (1.0 - exp(-twid/tau))*exp(-(time-tdly-twid-tphi)/tau)
Vn = Vo*(-1.0 + 2.0*xn)
#
# Calculate the pump currents from the diff pairs
#
Ip = Iee/(1.0 + exp(-Vp/Vt)) # Up current
In = Iee/(1.0 + exp(-Vn/Vt)) # Down current
#
# Integrate the net current over time to find the total charge
transferred
# to the loop filter. The integration algorithm used is simple, but
the time
# step is small, so a more complex algorithm isn't necessary.
#
Q = Q + (Ip - In)*tstep
# Increment the iteration variables
k = k + 1
time = k * tstep
Qtot.append(Q) # Add the charge to the list
print Q
Mike Monett
> On Tue, 8 Jun 2004 07:17:15 -0700, Mike wrote:
>
> > On 7 Jun 2004 03:36:53 -0700, Mike Monett wrote:
>>> Mike, I'm having difficulty following your description. Do you
>>> have a schematic and timing diagrams, perhaps a SPICE model?
> Here's a Python program that does the calculations and reports the
> results.
Mike, thanks for posting the code. I'm not familiar with Python but
it seems clear and readable enough.
Also, I want to thank you for the very useful information you have
posted on phase noise, and for the numerous links you have provided
in your various postings. In particular, the ones by Lee and
Hajimiri on Oscillator Phase Noise were very useful and I had not
come across them before. And, thank you for the very important prior
art info you found on the Binary Sampler - that was very helpful.
The reason I mention this is I find your posts valuable, and don't
want you to think I am attacking you in any way. I've been thinking
about the problem of how a seemingly reliable pll can suddenly
experience 100% failure, and have come to some conclusions that may
differ from yours.
First, the mode of failure is very strange. How can a simple pfd
work in different applications for years, then suddenly go bad?
It doesn't seem possible that it can be caused by one of the latches
resetting too quickly, leaving the other one still active. The set
and reset are one of the fastest circuits in D-flops, and the
minimum pulse widths are among the shortest listed in the datasheet.
Also, as Camenzind shows in Chapter 5, the first principle of linear
design is to rely on the close matching of parameters in
semiconductors. (Thanks for the url, Jim)
http://www.arraydesign.com/download/CHPTR5.PDF
This means both flops should have similar reset times. When the
feedback path includes the prop delay of an added gate, the
resulting reset pulse width seems more than sufficient to guarantee
that both flops or latches will be reset.
Recall this circuit has been used for decades and millions of parts
have been shipped without problem. So why should it suddenly show up
in your product? If there were problems in resetting the latches, it
should have been there from the beginning.
One indication of the true problem might be that your code doesn't
seem to account for the prop delay and risetimes of the current
sources. In fact, it appears your code can produce no result other
than a straight line, regardless of how much deadband is atually
present in the circuit!
Perhaps this kind of analysis really needs to be done in SPICE,
which can do a better job handling the transients involved. An
example is shown in Fig. 6 of Johansson's "A Simple Precharged CMOS
Phase Frequency Detector", IEEE Journal of Solid-State Circuits,
Vol. 33, No. 2, February 1998. (Please Note - I do not necessarily
agree with anything else he says, but the SPICE simulations are
very nice:)
http://iroi.seu.edu.cn/jssc9899/33ssc98/33ssc02/pdf/33ssc02-johansson2.pdf
So I think your code mislead you into believing that deadband was
impossible in your circuit. Also, from your response, it appears you
do not have a dedicated tester to view the response of the pll to a
variable pulse. Without this simple test, you have no way to look at
the response of the latches and charge pumps and see how much margin
actually exists before deadband shows up.
Now here's my hypothesis. You had a small amount of deadband in your
circuit from the beginning, but with your typical use, it never
showed up. Perhaps the normal system jitter was sufficient to mask
the deadband.
However, the new customer required a faster lock time, which means
increased loop bandwidth. Perhaps the system noise was also better,
which gave reduced system jitter. Under the new conditions, the loop
developed a limit cycle oscillation, which can grow to be quite
large.
This may have misled you into believing there was a problem
resetting the latches. So you installed Jim's DualD-PFD circuit and
the problem went away:
http://www.analog-innovations.com/SED/DualD-PFD.pdf
It is true his circuit works as you have described. It is also true
that it adds two prop delays to the reset path, which increases the
time that both current pumps are turned on in each cycle. If this
exceeds the risetime of the current pumps, the deadband disappears.
I am confident if you remove Jim's circuit and simply add an
equivalent delay in the reset path, you will obtain a similar
result.
Does this hypothesis sound reasonable and does it fit the available
information?
Best Wishes
Mike
Mike Monett
> On Tue, 8 Jun 2004 07:17:15 -0700, Mike wrote:
>
>> On 7 Jun 2004 03:36:53 -0700, Mike Monett wrote:
>>> Mike, I'm having difficulty following your description. Do you
>>> have a schematic and timing diagrams, perhaps a SPICE model?
> Here's a Python program that does the calculations and reports the
> results.
Mike, thanks for posting the code. I'm not familiar with Python but
http://www.arraydesign.com/download/CHPTR5.PDF
nice:)
http://iroi.seu.edu.cn/jssc9899/33ssc98/33ssc02/pdf/33ssc02-johansson2.pdf
So I think your code mislead you into believing that deadband was
impossible in your circuit. Also, from your response, it appears you
do not have a dedicated tester to view the response of the pll to a
variable pulse. Without this simple test, you have no way to look at
the response of the latches and charge pumps and see how much margin
actually exists before deadband sets in.
Mike
> Mike <mi...@nospam.com> wrote in message news:<1a95aekr5j4sh$.1ikvkifedtcnb$.d...@40tude.net>...
>> On Tue, 8 Jun 2004 07:17:15 -0700, Mike wrote:
>>
>>> On 7 Jun 2004 03:36:53 -0700, Mike Monett wrote:
> First, the mode of failure is very strange. How can a simple pfd
> work in different applications for years, then suddenly go bad?
>
> It doesn't seem possible that it can be caused by one of the latches
> resetting too quickly, leaving the other one still active. The set
> and reset are one of the fastest circuits in D-flops, and the
> minimum pulse widths are among the shortest listed in the datasheet.
> Also, as Camenzind shows in Chapter 5, the first principle of linear
> design is to rely on the close matching of parameters in
> semiconductors. (Thanks for the url, Jim)
>
> This means both flops should have similar reset times. When the
> feedback path includes the prop delay of an added gate, the
> resulting reset pulse width seems more than sufficient to guarantee
> that both flops or latches will be reset.
> Recall this circuit has been used for decades and millions of parts
> have been shipped without problem. So why should it suddenly show up
> in your product? If there were problems in resetting the latches, it
> should have been there from the beginning.
> One indication of the true problem might be that your code doesn't
> seem to account for the prop delay and risetimes of the current
> sources. In fact, it appears your code can produce no result other
> than a straight line, regardless of how much deadband is atually
> present in the circuit!
>
> Perhaps this kind of analysis really needs to be done in SPICE,
> which can do a better job handling the transients involved. An
> example is shown in Fig. 6 of Johansson's "A Simple Precharged CMOS
> Phase Frequency Detector", IEEE Journal of Solid-State Circuits,
> Vol. 33, No. 2, February 1998. (Please Note - I do not necessarily
> agree with anything else he says, but the SPICE simulations are
> very nice:)
> So I think your code mislead you into believing that deadband was
> impossible in your circuit. Also, from your response, it appears you
> do not have a dedicated tester to view the response of the pll to a
> variable pulse. Without this simple test, you have no way to look at
> the response of the latches and charge pumps and see how much margin
> actually exists before deadband shows up.
> Now here's my hypothesis. You had a small amount of deadband in your
> circuit from the beginning, but with your typical use, it never
> showed up. Perhaps the normal system jitter was sufficient to mask
> the deadband.
>
> However, the new customer required a faster lock time, which means
> increased loop bandwidth. Perhaps the system noise was also better,
> which gave reduced system jitter. Under the new conditions, the loop
> developed a limit cycle oscillation, which can grow to be quite
> large.
>
> This may have misled you into believing there was a problem
> resetting the latches. So you installed Jim's DualD-PFD circuit and
> the problem went away:
> Does this hypothesis sound reasonable and does it fit the available
> information?
1. I've done the work in SPICE, and published the results previously in my
first post in this thread. I've also measured my PFDs in the lab, where my
measurement capability extended down to 100ps. No dead zone, ever.
2. Matching of nearby devices, especially small digital switching devices
and their load resistors, had a standard deviation on the order of around
1% at the time. Matching is good, but not perfect. That was all taken into
account when the gates were designed.
3. I did have a dedicated tester; it wouldn't have helped, but it wasn't
needed anyway. We could reproduce the error in the lab with no problem,
without a special tester. As far as measuring dead-zone is concerned, I've
measured a PFD in the lab down to 100ps error (the periods being compared
were 50ns), and measured no dead-zone.
4. It may not seem possible that a part could work for years then suddenly
fail, but it's happened to me on numerous occasions. In this case it was
because something in the customer's application changed, but not because
they changed the bandwidth.
5. The problem was there from the beginning. It was just outside the range
where the part was commonly used. When the commonly used range happened to
extend to the point where the problem could be seen, it was seen. As with
many IC problems, it was also process lot dependent, and didn't show up
until production began in earnest. Then, suddenly, every part in one lot
failed, and the next lot...
6. You've been assuming that the failure occurs at zero phase error, which
is incorrect: the phase error when the failure occurred was far from zero,
and is unrelated to dead-zone. The cause is well known to those of us who
worked on the problem, but I'm not giving away the answer here. I will
offer a clue: the flops are identical, but the reset path is not.
7. It's extremely obvious when a reset fails to occur, since it has the
effect of reversing the phase error, and the loop slips at least one cycle
before it recovers. The reason I thought Jim might have seen the same error
is that we didn't think of adding the SR flop until we had seen the
problem.
8. My program does ignore prop delay and rise time in the current sources.
Extending the solution I presented to include RC rise and fall times is not
terribly difficult (I've done that also), and it doesn't change the answer
- the charge transferred to the load is still linear down to very small
phase errors. Prop delays are irrelevant unless you can show that the
energy is going somewhere, and in the case of a diff pair, the only place
it has to go is to the output; it doesn't matter how long it takes to get
there. The intent of the code was to show that the charge pump diff pairs
do not need to fully switch, and the charge pump current does not need to
rise completely, to avoid a dead-zone or produce non-linearity.
9. Did you notice that Johansson's PFD has _increased_ gain around zero
phase error? I've seen that in some of the circuits I designed as well. In
Johansson's case it might be due to his pre-charged circuits, but it can
also result from certain charge pump mismatch effects (not device
mismatches). In that case, the effect is easy to prove mathematically.
10. Again, here are my SPICE results, on a real circuit. I've built this
one too, and since it forms the heart of an OC-48 synthesizer, a dead zone
would push the jitter out of spec very quickly. The jitter in this
synthesizer is a little over 1ps.
Jim Thompson
[snip]
>7. It's extremely obvious when a reset fails to occur, since it has the
>effect of reversing the phase error, and the loop slips at least one cycle
>before it recovers. The reason I thought Jim might have seen the same error
>is that we didn't think of adding the SR flop until we had seen the
>problem.
>
[snip]
>-- Mike --
I *have * observed reset failures, thus my R-S approach.
Besides the obvious delay, it works because reset occurs when *both*
Q's are high and doesn't release until *both* QN's go high.
I haven't observed a reset failure with this method, but (disclaimer
:) it might be able to happen.
Mike
> On Fri, 11 Jun 2004 22:54:05 -0700, Mike <mi...@nospam.com> wrote:
>
> [snip]
>>7. It's extremely obvious when a reset fails to occur, since it has the
>>effect of reversing the phase error, and the loop slips at least one cycle
>>before it recovers. The reason I thought Jim might have seen the same error
>>is that we didn't think of adding the SR flop until we had seen the
>>problem.
>>
> [snip]
>>-- Mike --
>
> I *have * observed reset failures, thus my R-S approach.
>
> Besides the obvious delay, it works because reset occurs when *both*
> Q's are high and doesn't release until *both* QN's go high.
>
> I haven't observed a reset failure with this method, but (disclaimer
> :) it might be able to happen.
We haven't seen a reset failure with the R-S approach either, and we've
pushed it pretty hard to try to make it fail. We had to abandon it once,
when the speed was too high to include the R-S flop. It never failed, but
having been bitten once, it left me nervous for years.
-- Mike --