resetting a filter

[John Larkin]

I have a cmos logic signal that I want to delay a few ns. So I figure
I'll just run it through a 2 or 3-pole Bessel lowpass filter into the
next gate. I'd like it to recover quickly, so I figure I could
discharge the cap/caps in the filter. I could do that with schottky
diodes, but a transistor would discharge them better.

How about this?

https://dl.dropbox.com/u/53724080/Circuits/Filter_Reset.JPG

(Of course, it leaves a little current circulating in the inductor.)

I'm not sure how well it will work, so of course I'll simulate it.

But what's interesting is that I think the transistor doesn't saturate
once it's discharged the cap. Ic goes to zero, so there's base current
but no steady-state c-b junction current. No saturation, right?


--

John Larkin Highland Technology Inc
www.highlandtechnology.com jlarkin at highlandtechnology dot com

Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom timing and laser controllers
Photonics and fiberoptic TTL data links
VME analog, thermocouple, LVDT, synchro, tachometer
Multichannel arbitrary waveform generators

[Phil Hobbs]

On 08/07/2012 12:55 PM, John Larkin wrote:
>
>
> I have a cmos logic signal that I want to delay a few ns. So I figure
> I'll just run it through a 2 or 3-pole Bessel lowpass filter into the
> next gate. I'd like it to recover quickly, so I figure I could
> discharge the cap/caps in the filter. I could do that with schottky
> diodes, but a transistor would discharge them better.
>
> How about this?
>
> https://dl.dropbox.com/u/53724080/Circuits/Filter_Reset.JPG
>
> (Of course, it leaves a little current circulating in the inductor.)
>
> I'm not sure how well it will work, so of course I'll simulate it.
>
> But what's interesting is that I think the transistor doesn't saturate
> once it's discharged the cap. Ic goes to zero, so there's base current
> but no steady-state c-b junction current. No saturation, right?
>
>

Saturation is about nonequilibrium charge density in the base region,
which shields out the E field in the junction. It's the collector
current that scavenges all the injected carriers from the base, so I
would think that your situation would have all the nasty charge storage
problems of recovery from saturation.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510
845-480-2058

hobbs at electrooptical dot net
http://electrooptical.net

[George Herold]

On Aug 7, 12:55 pm, John Larkin

<jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
> I have a cmos logic signal that I want to delay a few ns.

How about a little piece of coax? Or wind the pcb trace around the
board?

or lumped element delay?

George H.

So I figure
> I'll just run it through a 2 or 3-pole Bessel lowpass filter into the
> next gate. I'd like it to recover quickly, so I figure I could
> discharge the cap/caps in the filter. I could do that with schottky
> diodes, but a transistor would discharge them better.
>
> How about this?
>
> https://dl.dropbox.com/u/53724080/Circuits/Filter_Reset.JPG
>
> (Of course, it leaves a little current circulating in the inductor.)
>
> I'm not sure how well it will work, so of course I'll simulate it.
>
> But what's interesting is that I think the transistor doesn't saturate
> once it's discharged the cap. Ic goes to zero, so there's base current
> but no steady-state c-b junction current. No saturation, right?
>
> --
>

> John Larkin                  Highland Technology Incwww.highlandtechnology.com  jlarkin at highlandtechnology dot com

[amdx]

On 8/7/2012 1:00 PM, George Herold wrote:
> On Aug 7, 12:55 pm, John Larkin
> <jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
>> I have a cmos logic signal that I want to delay a few ns.
>
> How about a little piece of coax? Or wind the pcb trace around the
> board?
>
> or lumped element delay?
>
> George H.
>
> So I figure

Somewhere there is a famous video of a presentation by a older
female military officer (Navy?) where she holds her fingers about
12" apart and says that's about one nanosecond.

Ahh, I found a link, not the one I remember, but good.

Her name Grace Hopper.

http://www.youtube.com/watch?v=JEpsKnWZrJ8

Mikek

[George Herold]

Grin, yeah I was looking at an Ortec delay generator 425A the other
day.
http://www.ortec-online.com/download/425A.pdf

George H.

[Joe Chisolm]

On Tue, 07 Aug 2012 09:55:41 -0700, John Larkin wrote:

> I have a cmos logic signal that I want to delay a few ns. So I figure
> I'll just run it through a 2 or 3-pole Bessel lowpass filter into the
> next gate. I'd like it to recover quickly, so I figure I could discharge
> the cap/caps in the filter. I could do that with schottky diodes, but a
> transistor would discharge them better.
>
> How about this?
>
> https://dl.dropbox.com/u/53724080/Circuits/Filter_Reset.JPG
>
> (Of course, it leaves a little current circulating in the inductor.)
>
> I'm not sure how well it will work, so of course I'll simulate it.
>
> But what's interesting is that I think the transistor doesn't saturate
> once it's discharged the cap. Ic goes to zero, so there's base current
> but no steady-state c-b junction current. No saturation, right?

what is a "few"? 3, 6, 22? How accurate of a delay?

If it's less than 15 or so take a 74lvc04 running at 3.3 will give you
a tpd typical of 2.5ns per gate. Wire 2,4 or 6 to get 5, 10 or 15ns.

--
Chisolm
Republic of Texas

[John Larkin]

On Tue, 7 Aug 2012 11:00:34 -0700 (PDT), George Herold
<ghe...@teachspin.com> wrote:

>On Aug 7, 12:55�pm, John Larkin
><jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
>> I have a cmos logic signal that I want to delay a few ns.
>
>How about a little piece of coax?

It's hard to pick-and-place two feet of coax!

Or wind the pcb trace around the
>board?

That would take a couple feet of trace, and it's not tunable. The
board will be pretty small.

>
>or lumped element delay?

This *is* lumped element delay!



--

John Larkin Highland Technology, Inc

jlarkin at highlandtechnology dot com

http://www.highlandtechnology.com

Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators

Custom laser drivers and controllers

Photonics and fiberoptic TTL data links

VME thermocouple, LVDT, synchro acquisition and simulation

[John Larkin]

On Tue, 07 Aug 2012 13:09:59 -0400, Phil Hobbs
<pcdhSpamM...@electrooptical.net> wrote:

>On 08/07/2012 12:55 PM, John Larkin wrote:
>>
>>
>> I have a cmos logic signal that I want to delay a few ns. So I figure
>> I'll just run it through a 2 or 3-pole Bessel lowpass filter into the
>> next gate. I'd like it to recover quickly, so I figure I could
>> discharge the cap/caps in the filter. I could do that with schottky
>> diodes, but a transistor would discharge them better.
>>
>> How about this?
>>
>> https://dl.dropbox.com/u/53724080/Circuits/Filter_Reset.JPG
>>
>> (Of course, it leaves a little current circulating in the inductor.)
>>
>> I'm not sure how well it will work, so of course I'll simulate it.
>>
>> But what's interesting is that I think the transistor doesn't saturate
>> once it's discharged the cap. Ic goes to zero, so there's base current
>> but no steady-state c-b junction current. No saturation, right?
>>
>>
>
>Saturation is about nonequilibrium charge density in the base region,
>which shields out the E field in the junction. It's the collector
>current that scavenges all the injected carriers from the base, so I
>would think that your situation would have all the nasty charge storage
>problems of recovery from saturation.
>
>Cheers
>
>Phil Hobbs

Oh well, I guess I'll use diodes.

--

John Larkin Highland Technology, Inc

jlarkin at highlandtechnology dot com

http://www.highlandtechnology.com

Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators

Custom laser drivers and controllers

Photonics and fiberoptic TTL data links

[John S]

She is also the one who introduced "bug" into our language for a problem
in the equipment.

[John Larkin]

On Tue, 07 Aug 2012 14:09:37 -0500, Joe Chisolm
<jchi...@earthlink.net> wrote:

>On Tue, 07 Aug 2012 09:55:41 -0700, John Larkin wrote:
>
>> I have a cmos logic signal that I want to delay a few ns. So I figure
>> I'll just run it through a 2 or 3-pole Bessel lowpass filter into the
>> next gate. I'd like it to recover quickly, so I figure I could discharge
>> the cap/caps in the filter. I could do that with schottky diodes, but a
>> transistor would discharge them better.
>>
>> How about this?
>>
>> https://dl.dropbox.com/u/53724080/Circuits/Filter_Reset.JPG
>>
>> (Of course, it leaves a little current circulating in the inductor.)
>>
>> I'm not sure how well it will work, so of course I'll simulate it.
>>
>> But what's interesting is that I think the transistor doesn't saturate
>> once it's discharged the cap. Ic goes to zero, so there's base current
>> but no steady-state c-b junction current. No saturation, right?
>
>what is a "few"? 3, 6, 22?

3 maybe.

> How accurate of a delay?

10% or so would do, but I'd like it to be fairly stable with
temperature and I don't want to add much jitter.

>
>If it's less than 15 or so take a 74lvc04 running at 3.3 will give you
>a tpd typical of 2.5ns per gate. Wire 2,4 or 6 to get 5, 10 or 15ns.

It would be good if I could change parts values to tweak the delay to
sub-ns resolution. I can do that with an RLC circuit.

--

John Larkin Highland Technology, Inc

jlarkin at highlandtechnology dot com

http://www.highlandtechnology.com

Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators

Custom laser drivers and controllers

Photonics and fiberoptic TTL data links

[Jim Thompson]

On Tue, 07 Aug 2012 09:55:41 -0700, John Larkin

<jjla...@highNOTlandTHIStechnologyPART.com> wrote:

>
>
>I have a cmos logic signal that I want to delay a few ns. So I figure
>I'll just run it through a 2 or 3-pole Bessel lowpass filter into the
>next gate. I'd like it to recover quickly, so I figure I could
>discharge the cap/caps in the filter. I could do that with schottky
>diodes, but a transistor would discharge them better.
>
>How about this?
>
>https://dl.dropbox.com/u/53724080/Circuits/Filter_Reset.JPG
>
>(Of course, it leaves a little current circulating in the inductor.)
>
>I'm not sure how well it will work, so of course I'll simulate it.
>
>But what's interesting is that I think the transistor doesn't saturate
>once it's discharged the cap. Ic goes to zero, so there's base current
>but no steady-state c-b junction current. No saturation, right?

What does "recover quickly" mean? After a positive-going transition
how soon does a negative-going transition occur?

...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

[lang...@fonz.dk]

vary the supply voltage?

or maybe a single gate with a resistor in the supply? might make pull
up slower
than pull down

-Lasse

[mike]

On 8/7/2012 12:51 PM, John Larkin wrote:
> On Tue, 7 Aug 2012 11:00:34 -0700 (PDT), George Herold
> <ghe...@teachspin.com> wrote:
>
>> On Aug 7, 12:55 pm, John Larkin
>> <jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
>>> I have a cmos logic signal that I want to delay a few ns.
>>
>> How about a little piece of coax?
>
> It's hard to pick-and-place two feet of coax!
>
>
> Or wind the pcb trace around the
>> board?
>
> That would take a couple feet of trace, and it's not tunable. The
> board will be pretty small.
>
>>
>> or lumped element delay?
>
> This *is* lumped element delay!
>
>
>

Now, I'm really confused.
If coax would meet the electrical requirement, why do you need
to reset your filter???
Sounds like you want to shorten the pulse by delaying the front edge.

More info about the range of pulse rates and widths might be relevant.

[Phil Hobbs]

IIRC her notebook says something like "First actual bug found in logic
system", because there was a moth or something stuck in there. That
remark seems to show that the phrase "getting the bugs out" was already
in use.

[Bill Sloman]

On Aug 7, 9:51 pm, John Larkin <jlar...@highlandtechnology.com> wrote:
> On Tue, 7 Aug 2012 11:00:34 -0700 (PDT), George Herold
>

> <gher...@teachspin.com> wrote:
> >On Aug 7, 12:55 pm, John Larkin
> ><jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
> >> I have a cmos logic signal that I want to delay a few ns.
>
> >How about a little piece of coax?
>
> It's hard to pick-and-place two feet of coax!

Farnell in Europe is still selling Filotex 1.22mm OD 75R coax. You
could wind a metre or so of that onto a RM core former and place it
like any other component.

http://nl.farnell.com/nexans/157296/cable-coax-miniature-per-m/dp/3855302

Newark doesn't seem to stock it, so you'll have to go a different
distributor

> > or lumped element delay?
>
> This *is* lumped element delay!

Not if you are planning to use active parts to "reset" it (which seems
like a very bad idea).

--
Bill Sloman, Nijmegen

[John Larkin]

On Tue, 7 Aug 2012 15:23:43 -0700 (PDT), Bill Sloman
<bill....@ieee.org> wrote:

>On Aug 7, 9:51�pm, John Larkin <jlar...@highlandtechnology.com> wrote:
>> On Tue, 7 Aug 2012 11:00:34 -0700 (PDT), George Herold
>>
>> <gher...@teachspin.com> wrote:
>> >On Aug 7, 12:55 pm, John Larkin
>> ><jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
>> >> I have a cmos logic signal that I want to delay a few ns.
>>
>> >How about a little piece of coax?
>>
>> It's hard to pick-and-place two feet of coax!
>
>Farnell in Europe is still selling Filotex 1.22mm OD 75R coax. You
>could wind a metre or so of that onto a RM core former and place it
>like any other component.
>
>http://nl.farnell.com/nexans/157296/cable-coax-miniature-per-m/dp/3855302
>
>Newark doesn't seem to stock it, so you'll have to go a different
>distributor

That would more than fill up the entire volume of the instrument I
have in mind.

>
>> > or lumped element delay?
>>
>> This *is* lumped element delay!
>
>Not if you are planning to use active parts to "reset" it (which seems
>like a very bad idea).

Why is it a bad idea? It will certainly work, namely give me a delay
that resets quickly.

[Tim Williams]

Ancient problem, ancient solution. Just use a stupid RCD delay. (R || D) +
C, use a schottky if your V_IL is tight.

Tim

--
Deep Friar: a very philosophical monk.
Website: http://webpages.charter.net/dawill/tmoranwms

"John Larkin" <jjla...@highNOTlandTHIStechnologyPART.com> wrote in message
news:mmh2281i4eij8c0hh...@4ax.com...

[Jamie]

Tim Williams wrote:

> Ancient problem, ancient solution. Just use a stupid RCD delay. (R ||
> D) + C, use a schottky if your V_IL is tight.
>
> Tim
>

My thoughts exactly.

Proper selection of the DIODE and R type (not value) is key though.

Jamie

[k...@att.bizzzzzzzzzzzz]

Yes, Adm Grace used to hand out "nanoseconds" (a foot long piece of wire) when
she gave presentations. A former boss had one of hers.

[bloggs.fred...@gmail.com]

How do you figure there's no c-b current. The path from /Q thru b-c and back to Q looks like a forward biased c-b current path?

[John Larkin]

Yeah, there will be current in that direction, the opposite direction
from "normal" collector current. I guess that will load carriers into
the c-b junction and add turn-off delay.

A schottky diode discharges the filter pretty well, but I'd like to
kill it all the way ASAP, so it forgets a pulse as fast as possible
before the next one hits.


Version 4
SHEET 1 880 680
WIRE 112 -240 -16 -240
WIRE 240 -240 192 -240
WIRE 368 -240 320 -240
WIRE 464 -240 368 -240
WIRE 528 -240 464 -240
WIRE 368 -208 368 -240
WIRE 368 -112 368 -144
WIRE -16 -32 -16 -240
WIRE 16 -32 -16 -32
WIRE 80 -32 16 -32
WIRE 368 -32 144 -32
WIRE -16 144 -16 -32
WIRE 96 144 -16 144
WIRE 224 144 176 144
WIRE 368 144 368 -32
WIRE 368 144 304 144
WIRE 464 144 368 144
WIRE 512 144 464 144
WIRE -16 160 -16 144
WIRE 368 176 368 144
WIRE -16 272 -16 240
WIRE 368 272 368 240
FLAG -16 272 0
FLAG 368 272 0
FLAG 368 -112 0
FLAG 464 144 OUT
FLAG 464 -240 REF
FLAG 16 -32 IN
SYMBOL res 320 128 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 200
SYMBOL cap 352 176 R0
SYMATTR InstName C1
SYMATTR Value 10p
SYMBOL ind 80 160 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 330n
SYMBOL voltage -16 144 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
WINDOW 3 -441 -22 Left 2
SYMATTR InstName V1
SYMATTR Value PULSE(0 3.3 1n 400p 400p 5n 10n 2)
SYMBOL diode 144 -48 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D2
SYMATTR Value DID
SYMBOL ind 96 -224 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L2
SYMATTR Value 330n
SYMBOL res 336 -256 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 200
SYMBOL cap 352 -208 R0
SYMATTR InstName C2
SYMATTR Value 10p
TEXT 80 72 Left 2 !.tran 30n
TEXT -616 0 Left 2 !.model DID D(Vfwd=0.3 Ron=12 Roff=1G Cjo=0.2p)

[Bill Sloman]

On Aug 8, 12:41 am, John Larkin <jlar...@highlandtechnology.com>
wrote:
> On Tue, 7 Aug 2012 15:23:43 -0700 (PDT),BillSloman

>
>
>
>
>
>
>
>
>
> <bill.slo...@ieee.org> wrote:
> >On Aug 7, 9:51 pm, John Larkin <jlar...@highlandtechnology.com> wrote:
> >> On Tue, 7 Aug 2012 11:00:34 -0700 (PDT), George Herold
>
> >> <gher...@teachspin.com> wrote:
> >> >On Aug 7, 12:55 pm, John Larkin
> >> ><jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
> >> >> I have a cmos logic signal that I want to delay a few ns.
>
> >> >How about a little piece of coax?
>
> >> It's hard to pick-and-place two feet of coax!
>
> >Farnell in Europe is still selling Filotex 1.22mm OD 75R coax. You
> >could wind a metre or so of that onto a RM core former and place it
> >like any other component.
>

> >http://nl.farnell.com/nexans/157296/cable-coax-miniature-per-m/dp/385...

>
> >Newark doesn't seem to stock it, so you'll have to go a different
> >distributor
>
> That would more than fill up the entire volume of the instrument I
> have in mind.

Expand your mind, or start thinking about using a twisted pair of
0.1mm OD enamelled copper wire as your transmission line.

> >> > or lumped element delay?
>
> >> This *is* lumped element delay!
>
> >Not if you are planning to use active parts to "reset" it (which seems
> >like a very bad idea).
>
> Why is it a bad idea? It will certainly work, namely give me a delay
> that resets quickly.

The time delay that you get will vary a bit with delay from the reset,
or - to put it another way - the reset action will mess with the
action of the delay circuit for a few nanoseconds after it's removed.
A double-terminated transmission line will probably have a shorter
hangover.

--
Bill Sloman, Nijmegen

[Bill Sloman]

On Aug 8, 6:59 am, John Larkin

<jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
> On Tue, 7 Aug 2012 19:38:01 -0700 (PDT),
>

<snipped LTSpice model>

Who'd bother posting an LTSpice model of high frequency circuit where
the inductors didn't have any parallel capacitance - where you'd
expect about 1pF - nor the resistors either - though that would be
closer to 0.1pF?

--
Bill Sloman, Nijmegen

[George Herold]

On Aug 7, 3:51 pm, John Larkin <jlar...@highlandtechnology.com> wrote:
> On Tue, 7 Aug 2012 11:00:34 -0700 (PDT), George Herold
>

> <gher...@teachspin.com> wrote:
> >On Aug 7, 12:55 pm, John Larkin
> ><jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
> >> I have a cmos logic signal that I want to delay a few ns.
>
> >How about a little piece of coax?
>
> It's hard to pick-and-place two feet of coax!
>
>  Or wind the pcb trace around the
>
> >board?
>

> That would take a couple feet of trace, and it's not tunable. The
> board will be pretty small.

Hmm, how close could you space traces in a zig-zaggy pattern? You
could add some taps, or short out some of the loops, for fine tuning.
(But I guess that screws up the impedance, having some extra C
flapping around on the end of a trace.) Could you squeeze a few feet
of delay into a few square inches of PCB? With a multilayer board
could you have zig-zags top and bottom. Does changing the
transmission line impedance change the propigation velocity? (I'd not
be surprised if skinny little low C traces were faster.... but I just
don't know.)

George H.

>
>
>
> >or lumped element delay?
>
> This *is* lumped element delay!
>
> --
>
> John Larkin         Highland Technology, Inc
>

> jlarkin at highlandtechnology dot comhttp://www.highlandtechnology.com

[lang...@fonz.dk]

On Aug 8, 2:47 pm, George Herold <gher...@teachspin.com> wrote:
> On Aug 7, 3:51 pm, John Larkin <jlar...@highlandtechnology.com> wrote:
>
>
>
>
>
>
>
>
>
> > On Tue, 7 Aug 2012 11:00:34 -0700 (PDT), George Herold
>
> > <gher...@teachspin.com> wrote:
> > >On Aug 7, 12:55 pm, John Larkin
> > ><jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
> > >> I have a cmos logic signal that I want to delay a few ns.
>
> > >How about a little piece of coax?
>
> > It's hard to pick-and-place two feet of coax!
>
> >  Or wind the pcb trace around the
>
> > >board?
>
> > That would take a couple feet of trace, and it's not tunable. The
> > board will be pretty small.
>
> Hmm, how close could you space traces in a zig-zaggy pattern?  You
> could add some taps, or short out some of the loops, for fine tuning.
> (But I guess that screws up the impedance, having some extra C
> flapping around on the end of a trace.)  Could you squeeze a few feet
> of delay into a few square inches of PCB?   With a multilayer board
> could you have zig-zags top and bottom.  Does changing the
> transmission line impedance change the propigation velocity?  (I'd not
> be surprised if skinny little low C traces were faster.... but I just
> don't know.)
>
> George H.
>

http://palgong.kyungpook.ac.kr/~ysyoon/Pdf/TrnsLine.pdf

-Lasse

[Bill Sloman]

On Aug 8, 2:47 pm, George Herold <gher...@teachspin.com> wrote:
> On Aug 7, 3:51 pm, John Larkin <jlar...@highlandtechnology.com> wrote:
>
>
>
>
>
>
>
>
>
> > On Tue, 7 Aug 2012 11:00:34 -0700 (PDT), George Herold
>
> > <gher...@teachspin.com> wrote:
> > >On Aug 7, 12:55 pm, John Larkin
> > ><jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
> > >> I have a cmos logic signal that I want to delay a few ns.
>
> > >How about a little piece of coax?
>
> > It's hard to pick-and-place two feet of coax!
>
> >  Or wind the pcb trace around the
>
> > >board?
>
> > That would take a couple feet of trace, and it's not tunable. The
> > board will be pretty small.
>
> Hmm, how close could you space traces in a zig-zaggy pattern?  You
> could add some taps, or short out some of the loops, for fine tuning.
> (But I guess that screws up the impedance, having some extra C
> flapping around on the end of a trace.)  Could you squeeze a few feet
> of delay into a few square inches of PCB?   With a multilayer board
> could you have zig-zags top and bottom.  Does changing the

> transmission line impedance change the propagation velocity?

No, but buried tracks (strip-line) are non-dispersive, and the the
propagation delay is solely a function of the dielectric constant of
the board material, rather than a messy hybrid as it is with track on
the surface of the board (microstrip).

http://en.wikipedia.org/wiki/Microstrip

<snip>

--
Bill Sloman, Nijmegen

[John Larkin]

I would. That's because I design electronics and you don't.

When I build this - and I will - the actual waveforms will be nearly
identical to the sim, and it will work. This will be used in our fifth
laser driver design, since we started doing laser drivers.

Apologies for using the word "work" in your presence.

Oh, you are way over-guessing the capacitance of a 330 nH
surface-mount inductor. It will be more like 0.2 pF, small enough to
ignore here.

[John Larkin]

On Tue, 7 Aug 2012 23:26:32 -0700 (PDT), Bill Sloman
<bill....@ieee.org> wrote:

>On Aug 8, 12:41 am, John Larkin <jlar...@highlandtechnology.com>
>wrote:
>> On Tue, 7 Aug 2012 15:23:43 -0700 (PDT),BillSloman
>>
>>
>>
>>
>>
>>
>>
>>
>>
>> <bill.slo...@ieee.org> wrote:
>> >On Aug 7, 9:51 pm, John Larkin <jlar...@highlandtechnology.com> wrote:
>> >> On Tue, 7 Aug 2012 11:00:34 -0700 (PDT), George Herold
>>
>> >> <gher...@teachspin.com> wrote:
>> >> >On Aug 7, 12:55 pm, John Larkin
>> >> ><jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
>> >> >> I have a cmos logic signal that I want to delay a few ns.
>>
>> >> >How about a little piece of coax?
>>
>> >> It's hard to pick-and-place two feet of coax!
>>
>> >Farnell in Europe is still selling Filotex 1.22mm OD 75R coax. You
>> >could wind a metre or so of that onto a RM core former and place it
>> >like any other component.
>>
>> >http://nl.farnell.com/nexans/157296/cable-coax-miniature-per-m/dp/385...
>>
>> >Newark doesn't seem to stock it, so you'll have to go a different
>> >distributor
>>
>> That would more than fill up the entire volume of the instrument I
>> have in mind.
>
>Expand your mind, or start thinking about using a twisted pair of
>0.1mm OD enamelled copper wire as your transmission line.

Expand back into the days of hand-wired NIM boxes? Google "surface
mount" to see what's happening this millenium. Google "skin loss"
while you're at it.

My people can pick-and-place four parts in maybe 1% of the time it
would take to fab/strip/solder/pack away a twisted pair. What a mess
for production.

Apologies for using "production" in your presence.

>
>> >> > or lumped element delay?
>>
>> >> This *is* lumped element delay!
>>
>> >Not if you are planning to use active parts to "reset" it (which seems
>> >like a very bad idea).
>>
>> Why is it a bad idea? It will certainly work, namely give me a delay
>> that resets quickly.
>
>The time delay that you get will vary a bit with delay from the reset,
>or - to put it another way - the reset action will mess with the
>action of the delay circuit for a few nanoseconds after it's removed.
>A double-terminated transmission line will probably have a shorter
>hangover.

Adding the diode greatly reduces the variation in delay as a function
of rep-rate, which is what I'm going to do.

--

John Larkin Highland Technology Inc

www.highlandtechnology.com jlarkin at highlandtechnology dot com

Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators

Custom timing and laser controllers

Photonics and fiberoptic TTL data links

[Uwe Hercksen]

John Larkin schrieb:

>
> I have a cmos logic signal that I want to delay a few ns.

Hello,

what about using a delay line as a small part?
http://www.datadelay.com/datasheets/3d7444.pdf
http://www.datadelay.com/datasheets/1503.pdf

Bye

[Spehro Pefhany]

Susumu has some interesting thin film passive parts for that delay
range. Not particularly cheap.

[John Larkin]

On Wed, 8 Aug 2012 05:47:01 -0700 (PDT), George Herold
<ghe...@teachspin.com> wrote:

>On Aug 7, 3:51 pm, John Larkin <jlar...@highlandtechnology.com> wrote:
>> On Tue, 7 Aug 2012 11:00:34 -0700 (PDT), George Herold
>>
>> <gher...@teachspin.com> wrote:
>> >On Aug 7, 12:55 pm, John Larkin
>> ><jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
>> >> I have a cmos logic signal that I want to delay a few ns.
>>
>> >How about a little piece of coax?
>>
>> It's hard to pick-and-place two feet of coax!
>>
>>  Or wind the pcb trace around the
>>
>> >board?
>>
>
>> That would take a couple feet of trace, and it's not tunable. The
>> board will be pretty small.
>
>Hmm, how close could you space traces in a zig-zaggy pattern? You
>could add some taps, or short out some of the loops, for fine tuning.
>(But I guess that screws up the impedance, having some extra C
>flapping around on the end of a trace.) Could you squeeze a few feet
>of delay into a few square inches of PCB? With a multilayer board
>could you have zig-zags top and bottom. Does changing the
>transmission line impedance change the propigation velocity? (I'd not
>be surprised if skinny little low C traces were faster.... but I just
>don't know.)
>
>George H.

PCB surface area and layers are expensive, and nanoseconds of delay
use a lot of real estate. If you put the zigzags too close together,
you get sideways coupling that makes things ugly.

Lumped RLC parts pack a lot of delay into a tiny area, and you can
change them easily if required.

PCB traces make rotten delay lines. They are big, lossy, expensive,
and have terrible TCs.

Microstrip (surface lines) do change velocity as a function of
impedance. Lossless stripline (embedded) lines depend only on
dielectric constant, but skin-effect losses make their prop delay
complex in real life, too.

We sometimes zigzag a trace to equalize routing lengths in, say, a
really high speed differential pair. But serious length PCB delay
lines rarely make sense.

This board has a couple, near P1 and U5.

https://dl.dropbox.com/u/53724080/PCBs/T165_A3.jpg

--

John Larkin Highland Technology Inc

www.highlandtechnology.com jlarkin at highlandtechnology dot com

Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators

Custom timing and laser controllers

Photonics and fiberoptic TTL data links

[John Larkin]

On Wed, 08 Aug 2012 16:30:43 +0200, Uwe Hercksen
<herc...@mew.uni-erlangen.de> wrote:

>
>

The CMOS silicon delay lines that I've used had a lot of jitter and
bad TCs and were expensive. I can do an RLC in less area and for a
tenth the price.

The Micrel parts are quite good, but are expensive ECL power hogs.

http://www.micrel.com/page.do?page=product-info/skew_mgn.jsp

[Jim Thompson]

On Tue, 07 Aug 2012 13:04:37 -0700, Jim Thompson
<To-Email-Use-Th...@On-My-Web-Site.com> wrote:

>On Tue, 07 Aug 2012 09:55:41 -0700, John Larkin
><jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>
>>
>>
>>I have a cmos logic signal that I want to delay a few ns. So I figure
>>I'll just run it through a 2 or 3-pole Bessel lowpass filter into the
>>next gate. I'd like it to recover quickly, so I figure I could
>>discharge the cap/caps in the filter. I could do that with schottky
>>diodes, but a transistor would discharge them better.
>>
>>How about this?
>>
>>https://dl.dropbox.com/u/53724080/Circuits/Filter_Reset.JPG
>>
>>(Of course, it leaves a little current circulating in the inductor.)
>>
>>I'm not sure how well it will work, so of course I'll simulate it.
>>
>>But what's interesting is that I think the transistor doesn't saturate
>>once it's discharged the cap. Ic goes to zero, so there's base current
>>but no steady-state c-b junction current. No saturation, right?
>
>What does "recover quickly" mean? After a positive-going transition
>how soon does a negative-going transition occur?
>
> ...Jim Thompson

Haven't seen an answer to my question (above).

Also. What CMOS logic family?

[Phil Hobbs]

Oh, dear, the colours on that layout clash with, well, anything. ;)

[John Larkin]

I think it would make a great t-shirt.

Why don't we see t-shirts screened with PCB layouts? They are the true
art of modern times.

[George Herold]

On Aug 8, 11:42 am, John Larkin

<jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
> On Wed, 8 Aug 2012 05:47:01 -0700 (PDT), George Herold
>
>
>
>
>

> John Larkin                  Highland Technology Incwww.highlandtechnology.com  jlarkin at highlandtechnology dot com

>
> Precision electronic instrumentation
> Picosecond-resolution Digital Delay and Pulse generators
> Custom timing and laser controllers
> Photonics and fiberoptic TTL data links
> VME  analog, thermocouple, LVDT, synchro, tachometer

> Multichannel arbitrary waveform generators- Hide quoted text -
>
> - Show quoted text -

OK, thanks for the nice reply.

I'll chalk it up as another silly idea.

George H.

[John Larkin]

It's not silly; you just have to do the numbers for specific cases.
Usually, lumped components win over distributed ones, but that's not
always true. 100 ps delay might be reasonable for a pcb trace delay
line.

--

John Larkin Highland Technology Inc

www.highlandtechnology.com jlarkin at highlandtechnology dot com

[Charlie E.]

On Wed, 8 Aug 2012 05:47:01 -0700 (PDT), George Herold

<ghe...@teachspin.com> wrote:

>On Aug 7, 3:51 pm, John Larkin <jlar...@highlandtechnology.com> wrote:
>> On Tue, 7 Aug 2012 11:00:34 -0700 (PDT), George Herold
>>
>> <gher...@teachspin.com> wrote:
>> >On Aug 7, 12:55 pm, John Larkin
>> ><jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
>> >> I have a cmos logic signal that I want to delay a few ns.
>>
>> >How about a little piece of coax?
>>
>> It's hard to pick-and-place two feet of coax!
>>
>>  Or wind the pcb trace around the
>>
>> >board?
>>
>
>> That would take a couple feet of trace, and it's not tunable. The
>> board will be pretty small.
>
>Hmm, how close could you space traces in a zig-zaggy pattern? You
>could add some taps, or short out some of the loops, for fine tuning.
>(But I guess that screws up the impedance, having some extra C
>flapping around on the end of a trace.) Could you squeeze a few feet
>of delay into a few square inches of PCB? With a multilayer board
>could you have zig-zags top and bottom. Does changing the
>transmission line impedance change the propigation velocity? (I'd not
>be surprised if skinny little low C traces were faster.... but I just
>don't know.)
>
>George H.
>
>

I can almost see this little zig-zag pattern, with a bunch of ground
traces between to prevent coupling, and a series of SMT FETs at one
end to short out segment to allow programmable delay...

Charlie

[whit3rd]

On Tuesday, August 7, 2012 9:55:41 AM UTC-7, John Larkin wrote:
> I have a cmos logic signal that I want to delay a few ns. So I figure
>
> I'll just run it through a 2 or 3-pole Bessel lowpass filter into the
>

> next gate. I'd like it to recover quickly...

Keep it simple. A gate will give a delay, a Schmitt trigger
will give more (larger logic swing required). An R-C-Schmitt
trigger combination will give larger delays yet, but none will
delay a positive edge more than a negative edge (which seems
to be desired here...). You might use a S/R flipflop to receive the
Q-plus-delay and /Q outputs, if that's the intention.

Classically, a twisted-pair length of wire would be good, but
that's not a component that can be pick-n-place assembled
by a robot for you.

[bloggs.fred...@gmail.com]

WIRE 656 -240 320 -240
WIRE 752 -240 656 -240
WIRE 816 -240 752 -240
WIRE 656 -208 656 -240
WIRE 384 -144 256 -144
WIRE 416 -144 384 -144
WIRE 544 -144 496 -144
WIRE 544 -112 544 -144
WIRE 656 -112 656 -144
WIRE 256 -48 256 -144
WIRE 384 -48 384 -144

WIRE -16 -32 -16 -240
WIRE 16 -32 -16 -32

WIRE -16 96 -16 -32
WIRE 256 96 256 16
WIRE 256 96 -16 96
WIRE 384 96 384 16
WIRE 656 96 384 96
WIRE 656 144 656 96
WIRE 752 144 656 144
WIRE 800 144 752 144
WIRE -16 160 -16 96
WIRE 656 176 656 144
WIRE 256 208 256 96
WIRE 384 208 384 96

WIRE -16 272 -16 240

WIRE 656 272 656 240
WIRE 256 400 256 272
WIRE 384 400 384 272
WIRE 384 400 256 400
WIRE 448 400 384 400
WIRE 592 400 528 400
WIRE 592 432 592 400
FLAG -16 272 0
FLAG 656 272 0
FLAG 656 -112 0
FLAG 752 144 OUT
FLAG 752 -240 REF
FLAG 16 -32 IN
FLAG 544 -112 0
FLAG 592 432 0
SYMBOL cap 640 176 R0

SYMATTR InstName C1
SYMATTR Value 10p

SYMBOL voltage -16 144 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
WINDOW 3 -441 -22 Left 2

SYMATTR Value PULSE(0 3.3 1n 400p 400p 5n 10n 2)

SYMATTR InstName V1
SYMBOL diode 240 -48 R0

SYMATTR InstName D2
SYMATTR Value DID
SYMBOL ind 96 -224 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L2
SYMATTR Value 330n
SYMBOL res 336 -256 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 200

SYMBOL cap 640 -208 R0

SYMATTR InstName C2
SYMATTR Value 10p

SYMBOL diode 368 -48 R0
SYMATTR InstName D1
SYMATTR Value DID
SYMBOL diode 368 208 R0
SYMATTR InstName D3
SYMATTR Value DID
SYMBOL diode 240 208 R0
SYMATTR InstName D4
SYMATTR Value DID
SYMBOL current 496 -144 R90
WINDOW 0 -32 40 VBottom 2
WINDOW 3 32 40 VTop 2

WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2

SYMATTR InstName I1
SYMATTR Value 6m
SYMBOL current 448 400 R270
WINDOW 0 32 40 VTop 2
WINDOW 3 -32 40 VBottom 2

WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2

SYMATTR InstName I2
SYMATTR Value 18m
TEXT -288 -72 Left 2 !.tran 30n

[lang...@fonz.dk]

but you could pick-n-place some SMAs and just plug in a cable

-Lasse

[John Larkin]

On Wed, 08 Aug 2012 11:09:50 -0700, Charlie E. <edmo...@ieee.org>
wrote:

You really need a bunch of DPDT switches to swap segments in and out,
or else a bunch of hi-z taps into a multiplexer. It really gets messy,
electrically. Really.

[Bill Sloman]

On Aug 8, 4:07 pm, John Larkin

<jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
> On Wed, 8 Aug 2012 00:52:22 -0700 (PDT), Bill Sloman
>
>
>
>
>
>
>
>
>
> <bill.slo...@ieee.org> wrote:
> >On Aug 8, 6:59 am, John Larkin
> ><jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
> >> On Tue, 7 Aug 2012 19:38:01 -0700 (PDT),
>
> >> bloggs.fredbloggs.f...@gmail.com wrote:
> >> >On Tuesday, August 7, 2012 12:55:41 PM UTC-4, John Larkin wrote:
> >> >> I have a cmos logic signal that I want to delay a few ns. So I figure
>
> >> >> I'll just run it through a 2 or 3-pole Bessel lowpass filter into the
>
> >> >> next gate. I'd like it to recover quickly, so I figure I could
>
> >> >> discharge the cap/caps in the filter. I could do that with schottky
>
> >> >> diodes, but a transistor would discharge them better.
>
> >> >> How about this?
>
> >> >>https://dl.dropbox.com/u/53724080/Circuits/Filter_Reset.JPG
>
> >> >> (Of course, it leaves a little current circulating in the inductor.)
>
> >> >> I'm not sure how well it will work, so of course I'll simulate it.
>
> >> >> But what's interesting is that I think the transistor doesn't saturate
>
> >> >> once it's discharged the cap. Ic goes to zero, so there's base current
>
> >> >> but no steady-state c-b junction current. No saturation, right?
>
> >> >> --
>
> >> >> John Larkin Highland Technology Inc
>

> >> >>www.highlandtechnology.comjlarkin at highlandtechnology dot com

>
> >> >> Precision electronic instrumentation
>
> >> >> Picosecond-resolution Digital Delay and Pulse generators
>
> >> >> Custom timing and laser controllers
>
> >> >> Photonics and fiberoptic TTL data links
>
> >> >> VME analog, thermocouple, LVDT, synchro, tachometer
>
> >> >> Multichannel arbitrary waveform generators
>
> >> >How do you figure there's no c-b current. The path from /Q thru b-c and back to Q looks like a forward biased c-b current path?
>
> >> Yeah, there will be current in that direction, the opposite direction
> >> from "normal" collector current. I guess that will load carriers into
> >> the c-b junction and add turn-off delay.
>
> >> A schottky diode discharges the filter pretty well, but I'd like to
> >> kill it all the way ASAP, so it forgets a pulse as fast as possible
> >> before the next one hits.
>
> ><snipped LTSpice model>
>
> >Who'd bother posting an LTSpice model of high frequency circuit where
> >the inductors didn't have any parallel capacitance - where you'd
> >expect about 1pF - nor the resistors either - though that would be
> >closer to 0.1pF?
>
> I would. That's because I design electronics and you don't.

No, it's because you are a sloppy tinkerer who rarely thinks about
what he's doing.

> When I build this - and I will - the actual waveforms will be nearly
> identical to the sim, and it will work.

More often than not, and you won't tell us about it if it doesn't.

> This will be used in our fifth
> laser driver design, since we started doing laser drivers.
>
> Apologies for using the word "work" in your presence.

Yes, it does bring on waves of nostalgia. Maybe I'll be able to get
some work in Sydney, after we mover there in October ... my wife
thinks that I'm nuts to even think about it, but she hasn't read the
Sydney electronics jobs listings on the web, and wouldn't have been
able to make much sense of them if she had.

> Oh, you are way over-guessing the capacitance of a 330 nH
> surface-mount inductor. It will be more like 0.2 pF, small enough to
> ignore here.

So why didn't you plug it in? My "guess" was taken from the Spice
model of the Wurth 742 792 092 ferrite bead which is what I use for
lower frequency work. 3.6uH would be a bit big for your purposes - I
wasn't excited enough to check a real 330nH inductor. Now that you
have raised the ante I spent a minute finding one

http://www.farnell.com/datasheets/360247.pdf

and this one does come out at 0.25pF.

--
Bill Sloman, Nijmegen

[Bill Sloman]

If he objects to an RM core former, he's going to see two SMA
connectors as huge. There are smaller coax connectors, but they are
even more ruinously expensive, and can difficult to get hold of in
small quantities. SMB and SMC are a bit cheaper and a bit smaller, and
probably good enough for his frequencies, but not small enough nor
cheap enough for this kind of application.

--
Bill Sloman, Nijmegen

[Charlie E.]

yeah, fine at low frequencies, but that shorted segment is just a big
capacitor hanging on there unless you also switch it out...

[John Larkin]

You guessed 1 pF, which is off by about 5:1. 500% error is well within
my definition of "sloppy."

>
>> When I build this - and I will - the actual waveforms will be nearly
>> identical to the sim, and it will work.
>
>More often than not, and you won't tell us about it if it doesn't.
>
>> This will be used in our fifth
>> laser driver design, since we started doing laser drivers.
>>
>> Apologies for using the word "work" in your presence.
>
>Yes, it does bring on waves of nostalgia. Maybe I'll be able to get
>some work in Sydney, after we mover there in October ... my wife
>thinks that I'm nuts to even think about it, but she hasn't read the
>Sydney electronics jobs listings on the web, and wouldn't have been
>able to make much sense of them if she had.
>
>> Oh, you are way over-guessing the capacitance of a 330 nH
>> surface-mount inductor. It will be more like 0.2 pF, small enough to
>> ignore here.
>
>So why didn't you plug it in?

Because it wouldn't affect things enough to matter. I didn't include
the PCB parasitics, the capacitor ESR, the speed of light, or any of
that stuff either. They wouldn't matter. I included the things that
matter.

My "guess" was taken from the Spice
>model of the Wurth 742 792 092 ferrite bead which is what I use for
>lower frequency work.

Why use a ferrite bead - which is complex - when high-Q real inductors
are cheap? And why guess at all? Sloppy, sloppy.

3.6uH would be a bit big for your purposes - I
>wasn't excited enough to check a real 330nH inductor. Now that you
>have raised the ante I spent a minute finding one
>
>http://www.farnell.com/datasheets/360247.pdf
>
>and this one does come out at 0.25pF.

I'll be using an 0603, with a bit higher SRF.

--

John Larkin Highland Technology, Inc

jlarkin at highlandtechnology dot com

http://www.highlandtechnology.com

Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators

Custom laser drivers and controllers

Photonics and fiberoptic TTL data links

[John Larkin]

The SMAs will cost a couple of dollars each. The cable will cost $10
or so. The surface and volume requirements will be enormous. The
surfmount parts will cost about 35 cents, if I use the expensive
super-low-capacitance low-barrier Skyworks diode.

[Phil Hobbs]

A bit of an acquired taste, I think, like appreciating the beauty of a
flood in a candy factory.

[Jamie]

Did you factor in the special charge of the near by electron accelerator?

Jamie

[Bill Sloman]

On Aug 8, 11:07 pm, John Larkin <jlar...@highlandtechnology.com>
wrote:
> On Wed, 8 Aug 2012 12:48:18 -0700 (PDT),BillSloman

>
> <bill.slo...@ieee.org> wrote:
> >On Aug 8, 4:07 pm, John Larkin
> ><jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
> >> On Wed, 8 Aug 2012 00:52:22 -0700 (PDT),BillSloman
>
> >> <bill.slo...@ieee.org> wrote:
> >> >On Aug 8, 6:59 am, John Larkin
> >> ><jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
> >> >> On Tue, 7 Aug 2012 19:38:01 -0700 (PDT),
>
> >> >> bloggs.fredbloggs.f...@gmail.com wrote:
> >> >> >On Tuesday, August 7, 2012 12:55:41 PM UTC-4, John Larkin wrote:
> >> >> >> I have a cmos logic signal that I want to delay a few ns. So I figure
>
> >> >> >> I'll just run it through a 2 or 3-pole Bessel lowpass filter into the
>
> >> >> >> next gate. I'd like it to recover quickly, so I figure I could
>
> >> >> >> discharge the cap/caps in the filter. I could do that with schottky
>
> >> >> >> diodes, but a transistor would discharge them better.
>
> >> >> >> How about this?
>
> >> >> >>https://dl.dropbox.com/u/53724080/Circuits/Filter_Reset.JPG
>
> >> >> >> (Of course, it leaves a little current circulating in the inductor.)
>
> >> >> >> I'm not sure how well it will work, so of course I'll simulate it.
>
> >> >> >> But what's interesting is that I think the transistor doesn't saturate
>
> >> >> >> once it's discharged the cap. Ic goes to zero, so there's base current
>
> >> >> >> but no steady-state c-b junction current. No saturation, right?
>
> >> >> >> --
>
> >> >> >> John Larkin Highland Technology Inc
>

> >> >> >>www.highlandtechnology.comjlarkinat highlandtechnology dot com

>
> >> >> >> Precision electronic instrumentation
>
> >> >> >> Picosecond-resolution Digital Delay and Pulse generators
>
> >> >> >> Custom timing and laser controllers
>
> >> >> >> Photonics and fiberoptic TTL data links
>
> >> >> >> VME analog, thermocouple, LVDT, synchro, tachometer
>
> >> >> >> Multichannel arbitrary waveform generators
>
> >> >> >How do you figure there's no c-b current. The path from /Q thru b-c and back to Q looks like a forward biased c-b current path?
>
> >> >> Yeah, there will be current in that direction, the opposite direction
> >> >> from "normal" collector current. I guess that will load carriers into
> >> >> the c-b junction and add turn-off delay.
>
> >> >> A schottky diode discharges the filter pretty well, but I'd like to
> >> >> kill it all the way ASAP, so it forgets a pulse as fast as possible
> >> >> before the next one hits.
>
> >> ><snipped LTSpice model>
>
> >> >Who'd bother posting an LTSpice model of high frequency circuit where
> >> >the inductors didn't have any parallel capacitance - where you'd
> >> >expect about 1pF - nor the resistors either - though that would be
> >> >closer to 0.1pF?
>
> >> I would. That's because I design electronics and you don't.
>
> >No, it's because you are a sloppy tinkerer who rarely thinks about
> >what he's doing.
>
> You guessed 1 pF, which is off by about 5:1. 500% error is well within
> my definition of "sloppy."

I was making a point about your idea of what constitutes a simulation,
rather than saying anything about the circuit - I'd have used the
numbers from a real part (if I could find them) if I were actually
interested in the circuit.

>
> >> When I build this - and I will - the actual waveforms will be nearly
> >> identical to the sim, and it will work.
>
> >More often than not, and you won't tell us about it if it doesn't.
>
> >> This will be used in our fifth
> >> laser driver design, since we started doing laser drivers.
>
> >> Apologies for using the word "work" in your presence.
>
> >Yes, it does bring on waves of nostalgia. Maybe I'll be able to get
> >some work in Sydney, after we mover there in October ... my wife
> >thinks that I'm nuts to even think about it, but she hasn't read the
> >Sydney electronics jobs listings on the web, and wouldn't have been
> >able to make much sense of them if she had.
>
> >> Oh, you are way over-guessing the capacitance of a 330 nH
> >> surface-mount inductor. It will be more like 0.2 pF, small enough to
> >> ignore here.
>
> >So why didn't you plug it in?
>
> Because it wouldn't affect things enough to matter. I didn't include
> the PCB parasitics, the capacitor ESR, the speed of light, or any of
> that stuff either. They wouldn't matter. I included the things that
> matter.

The whole point about simulation to to cross-check your ideas of what
things matter; leaving out the parallel capacitance of an inductor is
never a good idea. Tagging stray capacitances to ground onto critical
lines can be a good idea, but if you don't even bother plugging in
inductor capacitance, it seems unlikely you'd ever be careful enough
to work out the stray capacitance of a trace (actually microstrip
line, but that's probably too high-falutin for you).

> >My "guess" was taken from the Spice
> >model of the Wurth 742 792 092 ferrite bead which is what I use for
> >lower frequency work.
>
> Why use a ferrite bead - which is complex - when high-Q real inductors
> are cheap? And why guess at all? Sloppy, sloppy.

Because - to echo your comment - the exact value wasn't relevant to
the point I was making, so a guess served the purpose. The choice of a
ferrite bead over a high-Q real inductor reflects the fact that a high-
Q resonance can be a real nuisance if it's at a frequency where the
circuit has gain - I've spent too much time shoe-horning damping
resistors into circuit to tame high frequency resonances (and
inconvenient peaking) to be inclined to use a high-Q inductor unless I
actually need to.

> >3.6uH would be a bit big for your purposes - I
> >wasn't excited enough to check a real 330nH inductor. Now that you
> >have raised the ante I spent a minute finding one
>
> >http://www.farnell.com/datasheets/360247.pdf
>
> >and this one does come out at 0.25pF.
>
> I'll be using an 0603, with a bit higher SRF.

Whatever.

--
Bill Sloman, Nijmegen

[Jamie]

Yeah, what John said. You see, over here, Obama hasn't taken our
freedom of selecting the type of circuit and components we want to use, yet.

Jamie.

[whit3rd]

On Wednesday, August 8, 2012 2:13:35 PM UTC-7, John Larkin wrote:
> On Wed, 8 Aug 2012 12:07:02 -0700 (PDT), "lang...@fonz.dk"
>
> <lang...@fonz.dk> wrote:
>
>
>
> >On 8 Aug., 20:21, whit3rd <whit...@gmail.com> wrote:
>
> >> On Tuesday, August 7, 2012 9:55:41 AM UTC-7, John Larkin wrote:
>
> >> > I have a cmos logic signal that I want to delay a few ns.
>

> >> Classically, a twisted-pair length of wire would be good, but
>
> >> that's not a component that can be pick-n-place assembled
>
> >> by a robot for you.
>
> >
>
> >but you could pick-n-place some SMAs and just plug in a cable

> The SMAs will cost a couple of dollars each. The cable will cost $10
>
> or so. The surface and volume requirements will be enormous.

Four wire-wrap posts and a few feet of twisted 30 gage wire makes more
sense than coaxial (if you have true/inverted signals available, it won't
even have much capacitive coupling to shield against). Volume requirement
is an issue, and that's where the shlockmeisters start trying to sell you
lumped-constant 'delay line' modules at high prices with long leadtimes.

[John Larkin]

It's fine to leave it out when I know that it doesn't matter.

Tagging stray capacitances to ground onto critical
>lines can be a good idea, but if you don't even bother plugging in
>inductor capacitance, it seems unlikely you'd ever be careful enough
>to work out the stray capacitance of a trace (actually microstrip
>line, but that's probably too high-falutin for you).

Moron. I design picosecond electronics that works. Microstrips,
striplines, CPW, angles, vias, serpentines, pours. The vast majority
of it works first time, rev A board, shippable and billable.

I recently posted my ATLC electromagnetic sims of an edge-launch SMA
connector transitioning to microstrip, but I suppose you weren't
interested enough to notice. The result was a nearly perfect TDR
match, and gorgeous 42 ps output edges. People are buying the box now.

You've putzed around with one low frequency LC oscillator for years,
and it still doesn't work. Your sim didn't seem to "tag stray
capacitances to ground" anywhere.

>
>> >My "guess" was taken from the Spice
>> >model of the Wurth 742 792 092 ferrite bead which is what I use for
>> >lower frequency work.
>>
>> Why use a ferrite bead - which is complex - when high-Q real inductors
>> are cheap? And why guess at all? Sloppy, sloppy.
>
>Because - to echo your comment - the exact value wasn't relevant to
>the point I was making, so a guess served the purpose.

So, now you sanction guessing. Thing is, you guessed wrong.

--

John Larkin Highland Technology, Inc

jlarkin at highlandtechnology dot com
http://www.highlandtechnology.com

Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators

Custom laser drivers and controllers

Photonics and fiberoptic TTL data links

[John Larkin]

The San Francisco Ballet School is just the other side of my wall. I
can hear them practising. All that spinning around does frame-drag my
more sensitive measurements.

--

John Larkin Highland Technology, Inc

jlarkin at highlandtechnology dot com
http://www.highlandtechnology.com

Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators

Custom laser drivers and controllers

Photonics and fiberoptic TTL data links

[Bill Sloman]

On Aug 9, 2:48 am, John Larkin <jlar...@highlandtechnology.com> wrote:
> On Wed, 8 Aug 2012 14:34:59 -0700 (PDT),BillSloman

Until it turns out to matter in a slightly - but critically -
different situation.

> >Tagging stray capacitances to ground onto critical
> >lines can be a good idea, but if you don't even bother plugging in
> >inductor capacitance, it seems unlikely you'd ever be careful enough
> >to work out the stray capacitance of a trace (actually microstrip
> >line, but that's probably too high-falutin for you).
>
> Moron. I design picosecond electronics that works. Microstrips,
> striplines, CPW, angles, vias, serpentines, pours. The vast majority
> of it works first time, rev A board, shippable and billable.

And I was doing that back in 1990. The stuff that didn't work first
time didn't work because the drafting office "knew" that the order of
the inner layers didn't matter, despite my having told them quite
explicitly that it did in the release notes. We didn't get to ship the
stuff, but it wasn't because it didn't work.

Back in 1990 we were pushing the state of the art. Twenty years later,
you are doing what every Tom, Dick and Harry should be able to do, if
they are moderately careful. Because you've now iterated through five
fairly similar designs, you are confident that you can afford to cut
corners, which isn't wise.

> I recently posted my ATLC electromagnetic sims of an edge-launch SMA
> connector transitioning to microstrip, but I suppose you weren't
> interested enough to notice. The result was a nearly perfect TDR
> match, and gorgeous 42 ps output edges. People are buying the box now.

We were producing a 500psec wide beam blanking pulse back in 1985,
when edge-launched SMA connectors were obscure items in manufacturer's
catalogues which you couldn't buy because of some paranoid US export
rule that basically said that if you weren't part of the US radar
community you were a Russian stooge trying to buy stuff to put into
Russian radars.

> You've putzed around with one low frequency LC oscillator for years,
> and it still doesn't work. Your sim didn't seem to "tag stray
> capacitances to ground" anywhere.

For a 16kHz oscillator?

> >> >My "guess" was taken from the Spice
> >> >model of the Wurth 742 792 092 ferrite bead which is what I use for
> >> >lower frequency work.
>
> >> Why use a ferrite bead - which is complex - when high-Q real inductors
> >> are cheap? And why guess at all? Sloppy, sloppy.
>
> >Because - to echo your comment - the exact value wasn't relevant to
> >the point I was making, so a guess served the purpose.

<the usual John Larkin unmarked snip of my explanation of why I prefer
ferrite beads to high-Q inductors in a lot of situations>

> So, now you sanction guessing. Thing is, you guessed wrong.

Since I was pointing out that you had effectively guessed zero, which
has to be wrong by an infinitely larger margin, you are hoist by your
own petard.

--
Bill Sloman, Nijmegen

[Bill Sloman]

On Aug 9, 12:23 am, whit3rd <whit...@gmail.com> wrote:
> On Wednesday, August 8, 2012 2:13:35 PM UTC-7, John Larkin wrote:

> > On Wed, 8 Aug 2012 12:07:02 -0700 (PDT), "langw...@fonz.dk"

>
> > <langw...@fonz.dk> wrote:
>
> > >On 8 Aug., 20:21, whit3rd <whit...@gmail.com> wrote:
>
> > >> On Tuesday, August 7, 2012 9:55:41 AM UTC-7, John Larkin wrote:
>
> > >> > I have a cmos logic signal that I want to delay a few ns.
>
> > >> Classically, a twisted-pair length of wire would be good, but
>
> > >> that's not a component that can be pick-n-place assembled
>
> > >> by a robot for you.
>
> > >but you could pick-n-place some SMAs and just plug in a cable
> > The SMAs will cost a couple of dollars each. The cable will cost $10
>
> > or so. The surface and volume requirements will be enormous.
>
> Four wire-wrap posts and a few feet of twisted 30 gage wire makes more
> sense than coaxial (if you have true/inverted signals available, it won't
> even have much capacitive coupling to shield against).   Volume requirement
> is an issue,  and that's where the shlockmeisters start trying to sell you
> lumped-constant 'delay line' modules at high prices with long leadtimes.

Why 30 gauge? 42 gauge (SWG) enamelled transformer wire makes equally
good (or bad) twisted pair, and is a whole lot less bulky - even with
thick enamel each wire is less than 0.15mm thick. Anything thinner and
I tend to break it when winding it, but professional transformer
winders can do a lot better.

--
Bill Sloman, Nijmegen

[John Larkin]

The high frequency response will be ghastly.

--

John Larkin Highland Technology Inc

www.highlandtechnology.com jlarkin at highlandtechnology dot com

Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators

Custom timing and laser controllers

Photonics and fiberoptic TTL data links

[Bill Sloman]

On Aug 9, 5:52 am, John Larkin

You really think so? Why? And define "high frequency".

--
Bill Sloman, Nijmegen

[Bill Sloman]

On Aug 9, 12:23 am, Jamie
<jamie_ka1lpa_not_valid_after_ka1l...@charter.net> wrote:
> BillSlomanwrote:

> >>>>>>>>www.highlandtechnology.comjlarkinathighlandtechnology dot com

> Yeah, what John said. You see, over here, Obama hasn't taken our
> freedom of selecting the type of circuit and components we want to use, yet.

Scarcely the point at issue. If you want to model an inductor, model
something that looks vaguely like a real inductor, not something with
zero parallel capacitance.

Nobody wants to prescribe which inductor John models, but he'd be
better off if his models were a little more realistic - this is
probably a slightly more subtle idea than you can process, but some of
the lurkers may get the message.

--
Bill Sloman, Nijmegen

[SoothSayer]

On Tue, 07 Aug 2012 18:19:50 -0400, Phil Hobbs
<pcdhSpamM...@electrooptical.net> wrote:

>John S wrote:
>>
>> On 8/7/2012 1:26 PM, amdx wrote:
>> > On 8/7/2012 1:00 PM, George Herold wrote:
>> >> On Aug 7, 12:55 pm, John Larkin

>> >> <jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
>> >>> I have a cmos logic signal that I want to delay a few ns.
>> >>

>> >> How about a little piece of coax? Or wind the pcb trace around the
>> >> board?
>> >>
>> >> or lumped element delay?
>> >>
>> >> George H.
>> >>
>> >> So I figure
>> >
>> > Somewhere there is a famous video of a presentation by a older
>> > female military officer (Navy?) where she holds her fingers about
>> > 12" apart and says that's about one nanosecond.
>> >
>> > Ahh, I found a link, not the one I remember, but good.
>> >
>> > Her name Grace Hopper.
>> >
>> > http://www.youtube.com/watch?v=JEpsKnWZrJ8
>> >
>> > Mikek
>> >
>>
>> She is also the one who introduced "bug" into our language for a problem
>> in the equipment.
>
>IIRC her notebook says something like "First actual bug found in logic
>system", because there was a moth or something stuck in there. That
>remark seems to show that the phrase "getting the bugs out" was already
>in use.
>
>Cheers
>
>Phil Hobbs

She did not come up with it.
She *may have* introduced its use in the industry, however. But the
remark itself makes it sound as if it was already in use, even at that
point.

[SoothSayer]

On Wed, 8 Aug 2012 05:47:01 -0700 (PDT), George Herold
<ghe...@teachspin.com> wrote:

>
>Hmm, how close could you space traces in a zig-zaggy pattern?

NONE of you idiots have paid attention to his space limitations or
remarks.

Let's end it. Using a LENGTH of trace to solve his problem is NOT
feasible, nor possible in his situation.

Even 16 layers of zig zags. So try a different slow ride.

[SoothSayer]

On Wed, 08 Aug 2012 08:42:46 -0700, John Larkin
<jjla...@highNOTlandTHIStechnologyPART.com> wrote:

>We sometimes zigzag a trace to equalize routing lengths in, say, a
>really high speed differential pair. But serious length PCB delay
>lines rarely make sense.

I'll bet you make nice, rounded hairpin turns instead of squared off 'zig
zags' too.

[SoothSayer]

On Wed, 08 Aug 2012 17:14:31 -0400, Phil Hobbs

I could do stand up,but the audience would all have to be engineers or
technically inclined, and the jokes would only work once, so I would
always need new material. It would be a failed career.

[George Herold]

On Aug 8, 4:37 pm, Charlie E. <edmond...@ieee.org> wrote:
> On Wed, 08 Aug 2012 12:11:19 -0700, John Larkin
>
>
>
>
>

> <jlar...@highlandtechnology.com> wrote:
> >On Wed, 08 Aug 2012 11:09:50 -0700, Charlie E. <edmond...@ieee.org>

> >wrote:
>
> >>On Wed, 8 Aug 2012 05:47:01 -0700 (PDT), George Herold

> capacitor hanging on there unless you also switch it out...- Hide quoted text -
>
> - Show quoted text -

I was thinking that you could terminate the end of the trace and the
tap with the 'right' impedance and get rid of most of the reflection.

<changing gears>

Say John, (If you don't mind that I drag this thread a bit further
away from your original question.) What's your take on the reflection
from 90 degree bends in the trace.

Here's a wiki link, scroll down a bit for the bend 'stuff'

http://en.wikipedia.org/wiki/Microstrip

I never done any controlled impedance trace designs, so consider me an
idiot. I can imagine that you get a tiny bit more C from the corner.
But does it make that much difference? (With ~100ps edges, the edge
is spread out over centimeters of trace length...) I've used
microwave plumbing (in the distant past) where the bend radius was
pretty close the the wavlength, and that never caused any 'significant
reflections' that I can recall.

Thanks,

George H.



<snip>

[Spehro Pefhany]

On Thu, 09 Aug 2012 06:04:28 -0700, SoothSayer
<SayS...@TheMonastery.org> wrote:

>On Wed, 8 Aug 2012 05:47:01 -0700 (PDT), George Herold
><ghe...@teachspin.com> wrote:
>
>>
>>Hmm, how close could you space traces in a zig-zaggy pattern?

Stripline conductors can be as close as a couple dielectric
thicknesses between conductor edges without too much crosstalk.

> NONE of you idiots have paid attention to his space limitations or
>remarks.
>
> Let's end it. Using a LENGTH of trace to solve his problem is NOT
>feasible, nor possible in his situation.

Getting a few ns of delay doesn't take up much area using stripline,
say at the edge of a board-- maybe 0.3in^2, and parts can be mounted
overtop a buried delay line.

However, the delay is probably not well controlled, it's not
adjustable and may not be stable enough, so it's probably unsuited for
John's application.

Hey, a microstrip delay could be adjusted by adding a dielectric on
top of the strip. Like having a plastic ID label that is stuck on the
zig-zag at different spots to tune it. Let's see the copiers figure
that one out!

[John Larkin]

I occasionally put a test trace on PCB layouts, a couple of SMA
connectors with a 50 ohm trace between them that tours all the layers.
With a 20 GHz TDR bandwidth, I can see the connector transitions,
vias, and what looks like the fiberglas weave, but I usually can't
resolve 90 degree bends. In theory, they do add a little extra
capacitance, and the fix is to clip the corners a little.

https://dl.dropbox.com/u/53724080/TDR/T240_Output_Match.JPG

I don't know if that one helped, but it did work pretty well. I did
use ATLC to model the edge-launch SMA connector, which was the hard
part on this one.

https://dl.dropbox.com/u/53724080/ATLC/DSC01527.JPG

https://dl.dropbox.com/u/53724080/ATLC/Edge%20Launch%20Connector_small.bmp

https://dl.dropbox.com/u/53724080/ATLC/E-field.jpg

Here's a test trace that includes angles and vias and crossing plane
splits. On the TDR, the vias are visible discontinuities but the
angles aren't.

https://dl.dropbox.com/u/53724080/TDR/Chimera_TDR/Bottom.jpg


Impedance matching matters more and more these days. Logic and FPGA
chips and things like cheap crystal oscillators often have sub-ns
edges, and LVDS type things get below 100 ps. Even a SPI clock can
mess up of it's not impedance controlled and terminated.

This EM stuff is fun, where the speed of light becomes very real.

If you nedd to know more about controlled impedance traces, ask
Sloman. I'm just a tinkerer.

--

John Larkin Highland Technology Inc

www.highlandtechnology.com jlarkin at highlandtechnology dot com

Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators

Custom timing and laser controllers

Photonics and fiberoptic TTL data links

[John Larkin]

Crazy talk. We design high-performance high-order filters and pulse
shaping networks all the time in our shop, and we worry about inductor
Q, but seldom about shunt capacitance. In my example, the inductor is
feeding a 10 pF load through a 200 ohm resistor, and it has a shunt
capacitance below 0.2 pF, and I'm just delaying a logic signal. Here,
neither inductor Q nor shunt capacitance matter, it's obvious that
neither matters, so why include them in the model?

I only model things that matter. It only takes a few seconds of
consideration to exclude the things that really, really don't matter.

You are so determined to act as an authority that you quit thinking.
Bad engineering practice. Go put another turn on your transformer.

--

John Larkin Highland Technology Inc

www.highlandtechnology.com jlarkin at highlandtechnology dot com

[John Larkin]

I'm after a 3 ns delay, several hundred MHz equivalent bandwidth, so
I'd need a couple of feet of that 42-ga twisted pair. Its rise at the
end would be a horrible drool thing, from skin losses, and the drool
tail would defeat my goal of having a delay that has minimal memory of
previous events. There would be reflections, too, because the pair
impedance would be a function of frequency, so there's no simple
resistive termination value. I have TDRd twisted pairs (but not 42
ga!) and these problems are real. Small diameter twisted pairs are
very lossy, much worse than coax. Even CAT6 is ugly in the time
domain, and needs a lot of equalization to send Ethernet data
reliably.

Not to mention it being a nightmare in production.

You don't know much about this stuff.

[John Larkin]

I've played with that. Just a plastic sticker doesn't do much. A piece
of single-side copperclad, copper up, on top of the trace works, but
of course does messy stuff if it's not over *all* of the trace. I
suppose you could use a metal slab, with spacing above the board
tweaked with setscrews.

Really, I used to do stuff like this, chunks of coax and exotic PCB
traces. Surface-mount lumped components are so much better.

LLNL did an arbitrary waveform generator that used reflections off a
transmission line to make waveforms. They machined a brass plate as
the line, one plate for each desired waveform; they looked sort of
like those Christmas-tree air fresheners. We replaced that with an
electronic ARB.

[Bill Sloman]

On Aug 9, 6:01 pm, John Larkin

> >> >>>>>>>>www.highlandtechnology.comjlarkinathighlandtechnologydot com

And you've got away with it so far.

> In my example, the inductor is
> feeding a 10 pF load through a 200 ohm resistor, and it has a shunt
> capacitance below 0.2 pF, and I'm just delaying a logic signal. Here,
> neither inductor Q nor shunt capacitance matter, it's obvious that
> neither matters, so why include them in the model?

Because it's relevant and easily accessible information. If the
circuit stops working a few years because purchasing has bought a
cheaper inductor with a different shunt capacitance, it's handy if you
can pull the original value out of the Spice model.

Trying to find the original data sheets for old parts is one of the
bits of the electronic engineer's job that I've not got any nostalgia
for.

> I only model things that matter.

That you think matter, at the time.

> It only takes a few seconds of
> consideration to exclude the things that really, really don't matter.

And even less to exclude things that might matter, if they changed.

> You are so determined to act as an authority that you quit thinking.

You can't recognise thinking when you get your nose rubbed in it. You
are in fact advocating not thinking about any aspect of a circuit that
isn't actually giving you a problem at the moment, as tinkerers are
prone to do. It's a habit that can get you into trouble from time to
time.

> Bad engineering practice.

You do seem to be an authority on that ...

> Go put another turn on your transformer.

Manyana.

--
Bill Sloman, Nijmegen

[Phil Hobbs]

Cool. I bet their jitter was even better than yours, though the
programming time would sure have stunk.

[John Larkin]

Don't know about the jitter; we run a couple ps RMS from an async
optical trigger. If their impedance was low and the reflection
amplitude low, they may have been worse. That air freshener is a big
antenna, too.

They did develop software that turned a waveform into an n/c machining
program.

[John Larkin]

Obviously. What an engineer does is a quick mental, or maybe
calculated, thing to determine if trace resistance, or pad
capacitance, or prop delay, or part parasitics, are within orders of
magnitude of making any difference. Sometimes you just know this from
instinct or experience, sometimes you have to actually stop and think
about it.

It would be insane to do full nonlinear EM analysis of a slow circuit,
or to include parasitics that won't change things enough to matter.
Engineering involves knowing or calculating what matters and what
doesn't... otherwise you'd never get anything done.

You, apparently, never get anything done.

>
>> It only takes a few seconds of
>> consideration to exclude the things that really, really don't matter.
>
>And even less to exclude things that might matter, if they changed.
>
>> You are so determined to act as an authority that you quit thinking.
>
>You can't recognise thinking when you get your nose rubbed in it. You
>are in fact advocating not thinking about any aspect of a circuit that
>isn't actually giving you a problem at the moment, as tinkerers are
>prone to do. It's a habit that can get you into trouble from time to
>time.
>
>> Bad engineering practice.
>
>You do seem to be an authority on that ...
>
>> Go put another turn on your transformer.
>
>Manyana.

Thousands of manyanas. I wonder if it will oscillate in your lifetime.

--

John Larkin Highland Technology Inc

www.highlandtechnology.com jlarkin at highlandtechnology dot com

[George Herold]

On Aug 9, 11:52 am, John Larkin

> https://dl.dropbox.com/u/53724080/ATLC/Edge%20Launch%20Connector_smal...
>

Wow, Hey your dropbox launched paint on my computer and stuck your
drawing in it.

> https://dl.dropbox.com/u/53724080/ATLC/E-field.jpg
>
> Here's a test trace that includes angles and vias and crossing plane
> splits. On the TDR, the vias are visible discontinuities but the
> angles aren't.
>
> https://dl.dropbox.com/u/53724080/TDR/Chimera_TDR/Bottom.jpg
>
> Impedance matching matters more and more these days. Logic and FPGA
> chips and things like cheap crystal oscillators often have sub-ns
> edges, and LVDS type things get below 100 ps. Even a SPI clock can
> mess up of it's not impedance controlled and terminated.
>
> This EM stuff is fun, where the speed of light becomes very real.

Thanks for the nice reply.

I had a “massive failure” in regards to impedance matching a few
weeks ago. We’re marketing some ultrasonic teaching equipment in the
US for a German company. They do a lot of medical applications, and I
was adding some more physicsie things to it. One idea was to make an
anti-reflection 1/4 wavelength plate to go between the transducer and
some piece of metal. (Like the AR coating in optics). The transducer
put out pulses at about 2 MHz, and had an acoustic impedance of about
3, brass has an impedance of 40 (in the same units) and that of
aluminum is about 10. (So close to the needed geometric mean.) I got
the correct thickness of Al for 2 MHz, and slapped a piece on each end
of a brass cylinder.
It didn’t do squat to the amplitude of the pulses. Though it did
change the phase around a bit.
The next day I finally realized that you can’t make a 1/4 wave plate
for a single pulse. (Duh!) Using a CW source it works great.

George H.

>
> If you nedd to know more about controlled impedance traces, ask
> Sloman. I'm just a tinkerer.
>
> --
>

> John Larkin                  Highland Technology Incwww.highlandtechnology.com  jlarkin at highlandtechnology dot com

>
> Precision electronic instrumentation
> Picosecond-resolution Digital Delay and Pulse generators
> Custom timing and laser controllers
> Photonics and fiberoptic TTL data links
> VME  analog, thermocouple, LVDT, synchro, tachometer

> Multichannel arbitrary waveform generators- Hide quoted text -

[John Larkin]

For some reason, TD&H don't do it.

Because you've now iterated through five
>fairly similar designs, you are confident that you can afford to cut
>corners, which isn't wise.
>
>> I recently posted my ATLC electromagnetic sims of an edge-launch SMA
>> connector transitioning to microstrip, but I suppose you weren't
>> interested enough to notice. The result was a nearly perfect TDR
>> match, and gorgeous 42 ps output edges. People are buying the box now.
>
>We were producing a 500psec wide beam blanking pulse back in 1985,
>when edge-launched SMA connectors were obscure items in manufacturer's
>catalogues which you couldn't buy because of some paranoid US export
>rule that basically said that if you weren't part of the US radar
>community you were a Russian stooge trying to buy stuff to put into
>Russian radars.

Official edge launch connectors are a convenience. But you can
butt-solder a flanged SMA to the edge of a PCB and get just as good
matching to microstrip.

>
>> You've putzed around with one low frequency LC oscillator for years,
>> and it still doesn't work. Your sim didn't seem to "tag stray
>> capacitances to ground" anywhere.
>
>For a 16kHz oscillator?

You chose to ignore the parasitics. So did I. You whine when I do it.

>
>> >> >My "guess" was taken from the Spice
>> >> >model of the Wurth 742 792 092 ferrite bead which is what I use for
>> >> >lower frequency work.
>>
>> >> Why use a ferrite bead - which is complex - when high-Q real inductors
>> >> are cheap? And why guess at all? Sloppy, sloppy.
>>
>> >Because - to echo your comment - the exact value wasn't relevant to
>> >the point I was making, so a guess served the purpose.
>
><the usual John Larkin unmarked snip of my explanation of why I prefer
>ferrite beads to high-Q inductors in a lot of situations>
>
>> So, now you sanction guessing. Thing is, you guessed wrong.
>
>Since I was pointing out that you had effectively guessed zero, which
>has to be wrong by an infinitely larger margin, you are hoist by your
>own petard.

Zero is a good value for accurate simulation of this circuit. 1 pF
isn't.

[John Larkin]

I don't get into trouble over simple stuff like RLC step response. I
don't think we've ever had an LC filter break. I sometimes get into
trouble because a transistor or a complex IC is inadequately
specified, or its Spice model is bad, things like that. But even then,
not very often.

You don't get in trouble because you don't do anything.

>
>> Bad engineering practice.
>
>You do seem to be an authority on that ...

Absolutely. I've seen a lot of bad designs, a few of my own. The
biggest design problem isn't things that don't work; it's the things
that don't sell.

--

John Larkin Highland Technology, Inc

jlarkin at highlandtechnology dot com

http://www.highlandtechnology.com

Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators

Custom laser drivers and controllers

Photonics and fiberoptic TTL data links

[Greegor]

http://www2.uregina.ca/yourblog/wp-content/uploads/2010/12/H96566k1.jpg

http://lh5.ggpht.com/raj.m.rao/SNZWX-SD6-I/AAAAAAAAD4I/7fXxH3qPBbs/bugl%5B4%5D.jpg

http://cs.calvin.edu/images/adams/graceHopper/hopper-finds-bug.jpg

http://www.blogcdn.com/marlothomas.aol.com/media/2011/03/first-computer-bug-586x169.jpg

http://americanhistory.si.edu/dynamic/images/collections_xlarge/92-13130_428px.jpg

http://www.gelauff.com/images/bug.jpg

I agree that the note in the log book implies the term
was in use before, but in video and live presentations
Grace did claim that the word usage originated there.

The line in the log book looks like it could
have been paranthetic and squeezed in later to
support their endless jokes after that.

> She *may have* introduced its use in the industry, however. But the
> remark itself makes it sound as if it was already in use, even at that
> point.

My favorite story from her lectures was the
part where during the war, she was asked
to calculate the cost in lives and resources
to take each island in the chain to Japan.
She did that, but also calculated the cost
of NOT taking every island along the way,
the risks of hopping OVER islands along the
chain. The result saved a considerable
number of US lives.

Grace herself claimed it started among their group.
Her reputation is one of exceptional honesty.

http://groups.google.com/group/sci.electronics.design/browse_frm/thread/1d8c7a653735e34a/8dd2045c9a4a3c0c?hl=en#8dd2045c9a4a3c0c

The origin of the computer bug

Although Hopper is often credited with having found the first bug, she
was always careful to mention when she recalled the story that she was
not present when the bug was actually found.
When she was involved with testing the Mark II Aiken Relay Calculator
at Harvard in 1947 – not 1945 as mentioned in many accounts of this
story – the machine malfunctioned. Upon investigation the operators
found a moth stuck at Relay #70, panel F. Using tweezers, the moth was
removed and taped to the computer log with the explanatory text “First
actual case of bug being found.” The story was put out that the
computer had been debugged and the term “debugging” had been added to
the computer world’s vocabulary. Hopper often said “From then on, when
anything went wrong with a computer, we said it had bugs in it." The
original logbook page, dated September 9 and with the moth still taped
to it, is located in the Naval History Center at the U.S. Naval
Surface Warfare Center in Dahlgren, Virginia.

[bloggs.fred...@gmail.com]

On Thursday, August 9, 2012 5:32:12 PM UTC-4, Greegor wrote:

>
> Grace did claim that the word usage originated there.

She's full of manure. T.A. Edison was using the term in published material as early as 1889.

>
> My favorite story from her lectures was the
>
> part where during the war, she was asked
>
> to calculate the cost in lives and resources
>
> to take each island in the chain to Japan.
>
> She did that, but also calculated the cost
>
> of NOT taking every island along the way,
>
> the risks of hopping OVER islands along the
>
> chain. The result saved a considerable
>
> number of US lives.

The wizened and delusional old senile sycophant fool is again full of manure:

"After World War I, the Versailles Treaty gave Japan a mandate over former German colonies in the western Pacific; specifically, the Mariana, Marshall, and Caroline Islands. If these islands were fortified, Japan could, in principle, deny the US access to its interests in the western Pacific. Therefore, in 1921, Lieutenant Colonel Earl Hancock Ellis of the US Marine Corps drafted "Plan 712, Advanced Base Operations in Micronesia," a plan for war against Japan which updated War Plan Orange by incorporating modern military technology (submarines, aircraft, etc.) and which again included an island-hopping strategy.[5] Shortly afterwards, a British-American reporter on naval affairs, Hector Charles Bywater, publicized the prospect of a Japanese-American war in his books Seapower in the Pacific (1923) and The Great Pacific War (1925), which detailed an island-hopping strategy. The books were read not only by Americans but by senior officers of the Japanese Imperial Navy,[6] who used "island-hopping" in their successful southeast Asia offensives in 1941 and 1942.[7]"

>
>
>
> is located in the Naval History Center at the U.S. Naval
>
> Surface Warfare Center in Dahlgren, Virginia.

The log book is in the Smithsonian and not some worn-out waste dump military museum. http://americanhistory.si.edu/collections/object.cfm?key=35&objkey=30

Get a clue, most history as recalled by military related people/activities is 100% manure.

[Jamie]

You know, I should read what I type more often, I meant to say spatial
charge.. but what ever..

Now if I could only figure out how to kill fruit flies coming from
some unknown place in my home? The climate has been bad here lately and
these little buggers are just loving my home. It has been suggested to
use a HV fly swatter near the source, well that would be fine, if I knew
where the source was...

Jamie

[Tim Williams]

"John Larkin" <jjla...@highNOTlandTHIStechnologyPART.com> wrote in message
news:dmn728954ba68aeqk...@4ax.com...

> and the drool
> tail would defeat my goal of having a delay that has minimal memory of
> previous events.

So use the RCD delay. You still haven't mentioned what's wrong with it.
Just not novel enough?

Tim

--
Deep Friar: a very philosophical monk.
Website: http://webpages.charter.net/dawill/tmoranwms

[John Larkin]

On Thu, 9 Aug 2012 17:45:23 -0500, "Tim Williams"
<tmor...@charter.net> wrote:

>"John Larkin" <jjla...@highNOTlandTHIStechnologyPART.com> wrote in message
>news:dmn728954ba68aeqk...@4ax.com...
>> and the drool
>> tail would defeat my goal of having a delay that has minimal memory of
>> previous events.
>
>So use the RCD delay. You still haven't mentioned what's wrong with it.
>Just not novel enough?
>
>Tim

The RLC can be critically damped, which makes it forget previous
events better. There's still the RC tail from the finite diode drop.

A better circuit would charge the cap from a current source, and then
quickly and completely discharge it. At these speeds, that might be a
PHEMT. I guess I could do that. The current source gets tricky with
only 5 volts available.

The RLC also has a faster slew rate around the logic threshold, which
makes for a more repeatable delay and less jitter. It's the first step
towards a lumped delay line.


This isn't real bad...

+V
|
|
R
|
|
logic in--------|<|-----+--------- logic out
|
|
C
|
|
gnd

It doesn't discharge to ground, but it does discharge to a repeatable
voltage, fast.

--

John Larkin Highland Technology, Inc

jlarkin at highlandtechnology dot com

http://www.highlandtechnology.com

Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators

Custom laser drivers and controllers

Photonics and fiberoptic TTL data links

[Bill Sloman]

On Aug 9, 6:56 pm, John Larkin

<jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
> On Thu, 9 Aug 2012 09:22:50 -0700 (PDT), Bill Sloman
>

> <bill.slo...@ieee.org> wrote:
> >On Aug 9, 6:01 pm, John Larkin
> ><jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
> >> On Thu, 9 Aug 2012 04:00:09 -0700 (PDT), Bill Sloman
>
> >> <bill.slo...@ieee.org> wrote:
> >> >On Aug 9, 12:23 am, Jamie
> >> ><jamie_ka1lpa_not_valid_after_ka1l...@charter.net> wrote:
> >> >> BillSlomanwrote:
> >> >> > On Aug 8, 11:07 pm, John Larkin <jlar...@highlandtechnology.com>
> >> >> > wrote:
>
> >> >> >>On Wed, 8 Aug 2012 12:48:18 -0700 (PDT),BillSloman
>
> >> >> >><bill.slo...@ieee.org> wrote:
>
> >> >> >>>On Aug 8, 4:07 pm, John Larkin
> >> >> >>><jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
>
> >> >> >>>>On Wed, 8 Aug 2012 00:52:22 -0700 (PDT),BillSloman
>
> >> >> >>>><bill.slo...@ieee.org> wrote:
>
> >> >> >>>>>On Aug 8, 6:59 am, John Larkin
> >> >> >>>>><jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
>
> >> >> >>>>>>On Tue, 7 Aug 2012 19:38:01 -0700 (PDT),
>
> >> >> >>>>>>bloggs.fredbloggs.f...@gmail.com wrote:
>
> >> >> >>>>>>>On Tuesday, August 7, 2012 12:55:41 PM UTC-4, John Larkin wrote:

<snip>

> >> I only model things that matter.
>
> >That you think matter, at the time.
>
> Obviously. What an engineer does is a quick mental, or maybe
> calculated, thing to determine if trace resistance, or pad
> capacitance, or prop delay, or part parasitics, are within orders of
> magnitude of making any difference. Sometimes you just know this from
> instinct or experience, sometimes you have to actually stop and think
> about it.

Yes, but ... When I was designing stuff for production, and we started
using simulation, it became obvious that the simulated schematic
really had to be the same schematic that we used for production
documentation; one of the incidental advantages of simulation is that
if you've made a drop-off on the schematic you are simulating, the
simulation doesn't work, and you want to exploit that as a form of
error-checking, the two documents have to be the same.

So stuff that "doesn't matter" in the simulation should still be
included in the schematic data base. It may not matter now, but ti may
matter when you have to go back through the documentation, years
later, to find out why the hardware you are producing doesn't meet
specification any more.

> It would be insane to do full nonlinear EM analysis of a slow circuit,

Obviously.

> or to include parasitics that won't change things enough to matter.

Much less insane - they document exactly what you thought you were
doing, and how you were doing it. That can be less obvious a few years
later.

> Engineering involves knowing or calculating what matters and what
> doesn't... otherwise you'd never get anything done.

Not just knowing and calculating, but also documenting - so you really
can build the same thing again and again.

> You, apparently, never get anything done.

I'm not getting much done at the moment, but nobody is paying me to do
stuff, or could give a shit when I get it done. When I was getting
paid, and other people were relying on me to get stuff done, I was a
lot more productive - unusually productive by U.K. standards, though
there were times when I wasn't producing what my manager though that I
ought to be producing (because he didn't know enough about what was
going on, and was unwilling to be educated).

> >> It only takes a few seconds of
> >> consideration to exclude the things that really, really don't matter.

And sometimes those few seconds aren't long enough to comprehend
everything that's actually going on. It's fine as long as you really
are excluding stuff that really doesn't matter, but when you get it
wrong it can be difficult to unblinker yourself and recognise that
something small isn't always negligible.

> >And even less to exclude things that might matter, if they changed.
>
> >> You are so determined to act as an authority that you quit thinking.
>
> >You can't recognise thinking when you get your nose rubbed in it. You
> >are in fact advocating not thinking about any aspect of a circuit that
> >isn't actually giving you a problem at the moment, as tinkerers are
> >prone to do. It's a habit that can get you into trouble from time to
> >time.
>
> >> Bad engineering practice.
>
> >You do seem to be an authority on that ...
>
> >> Go put another turn on your transformer.
>
> >Manyana.
>
> Thousands of manyanas. I wonder if it will oscillate in your lifetime.

Unsavoury rhetorical device. You couldn't care less if it's ever going
to work, but pretending to speculate about it gives you an opportunity
to say something unpleasant.

--
Bill Sloman, Nijmegen

[Bill Sloman]

On Aug 9, 10:12 pm, John Larkin <jlar...@highlandtechnology.com>
wrote:

> On Wed, 8 Aug 2012 20:04:11 -0700 (PDT), Bill Sloman
>

> <bill.slo...@ieee.org> wrote:
> >On Aug 9, 2:48 am, John Larkin <jlar...@highlandtechnology.com> wrote:
> >> On Wed, 8 Aug 2012 14:34:59 -0700 (PDT),BillSloman
>
> >> <bill.slo...@ieee.org> wrote:
> >> >On Aug 8, 11:07 pm, John Larkin <jlar...@highlandtechnology.com>
> >> >wrote:
> >> >> On Wed, 8 Aug 2012 12:48:18 -0700 (PDT),BillSloman
>
> >> >> <bill.slo...@ieee.org> wrote:
> >> >> >On Aug 8, 4:07 pm, John Larkin
> >> >> ><jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
> >> >> >> On Wed, 8 Aug 2012 00:52:22 -0700 (PDT),BillSloman
>
> >> >> >> <bill.slo...@ieee.org> wrote:
> >> >> >> >On Aug 8, 6:59 am, John Larkin
> >> >> >> ><jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
> >> >> >> >> On Tue, 7 Aug 2012 19:38:01 -0700 (PDT),
>
> >> >> >> >> bloggs.fredbloggs.f...@gmail.com wrote:
> >> >> >> >> >On Tuesday, August 7, 2012 12:55:41 PM UTC-4, John Larkin wrote:

<snip>

> >> Moron. I design picosecond electronics that works. Microstrips,
> >> striplines, CPW, angles, vias, serpentines, pours. The vast majority
> >> of it works first time, rev A board, shippable and billable.
>
> >And I was doing that back in 1990. The stuff that didn't work first
> >time didn't work because the drafting office "knew" that the order of
> >the inner layers didn't matter, despite my having told them quite
> >explicitly that it did in the release notes. We didn't get to ship the
> >stuff, but it wasn't because it didn't work.
>
> >Back in 1990 we were pushing the state of the art. Twenty years later,
> >you are doing what every Tom, Dick and Harry should be able to do, if
> >they are moderately careful.
>
> For some reason, TD&H don't do it.

They do, but they don't happen to be competing in your little niche
market, so you don't notice.

> >Because you've now iterated through five
> >fairly similar designs, you are confident that you can afford to cut
> >corners, which isn't wise.
>
> >> I recently posted my ATLC electromagnetic sims of an edge-launch SMA
> >> connector transitioning to microstrip, but I suppose you weren't
> >> interested enough to notice. The result was a nearly perfect TDR
> >> match, and gorgeous 42 ps output edges. People are buying the box now.
>
> >We were producing a 500psec wide beam blanking pulse back in 1985,
> >when edge-launched SMA connectors were obscure items in manufacturer's
> >catalogues which you couldn't buy because of some paranoid US export
> >rule that basically said that if you weren't part of the US radar
> >community you were a Russian stooge trying to buy stuff to put into
> >Russian radars.
>
> Official edge launch connectors are a convenience. But you can
> butt-solder a flanged SMA to the edge of a PCB and get just as good
> matching to microstrip.

Production get shirty about that sort of solution - not unreasonably.

> >> You've putzed around with one low frequency LC oscillator for years,
> >> and it still doesn't work. Your sim didn't seem to "tag stray
> >> capacitances to ground" anywhere.
>
> >For a 16kHz oscillator?
>
> You chose to ignore the parasitics. So did I. You whine when I do it.

I certainly don't ignore the parallel capacitance of my inductors - I
do rely on the regular LTSpice library model of my ferrite beads, but
when there isn't a built-in library model I put something together.

And I wasn't "whining about you ignoring parasitics" - the parallel
capacitance of an inductor determines the frequency range over which
it looks like an inductor. It's not a parasitic, but an absolutely
fundamental feature of the device, which you can only rarely get away
with setting to zero.

> >> >Because - to echo your comment - the exact value wasn't relevant to
> >> >the point I was making, so a guess served the purpose.
>
> ><the usual John Larkin unmarked snip of my explanation of why I prefer
> >ferrite beads to high-Q inductors in a lot of situations>
>
> >> So, now you sanction guessing. Thing is, you guessed wrong.
>
> >Since I was pointing out that you had effectively guessed zero, which
> >has to be wrong by an infinitely larger margin, you are hoist by your
> >own petard.
>
> Zero is a good value for accurate simulation of this circuit.

It's never good "for an accurate simulation" of any circuit. You may
have got away with it on this particular circuit, but all you are
saying its that you didn't need a particularly accurate simulation.

> 1 pF isn't.

It didn't make very much difference, so it can't be said to be any
worse than your mindless over-simplification.

--
Bill Sloman, Nijmegen

[Bill Sloman]

On Aug 9, 6:11 pm, John Larkin

<jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
> On Thu, 9 Aug 2012 01:37:09 -0700 (PDT), Bill Sloman
>

Enamel isn't a great dielectric. My experience went the other way. I
needed a transmission line transformer, and wound something small with
Filotex 55R 1,2mm OD coaxial cable. It worked, but it wasn't all that
cheap. As a reality check, I tried a twisted pair made with 38 swg
enamelled wire - mainly because the coil winding shop stocked both 38
swg with both red and green enamel (one was self-fluxing and one
wasn't (or something like that).

It worked just as well - because I had room for more twisted pair it
fell over at 150MHz rather than 500MHz but that was entirely due to
the extra length of the twisted pair winding, which put the low
frequency end down at about 50kHz, rather lower than fewer turns of
the Filotex could offer.

> Even CAT6 is ugly in the time domain, and needs a lot of equalization to send Ethernet data
> reliably.

When I was knowledgeable about Ethernet, back in 1980, it used proper
coax, and a single Ethernet might span a university campus. It's
changed a bit since then, and nobody has been paying me to keep up.

> Not to mention it being a nightmare in production.

Bifilar windings are a nightmare in production? Your production staff
can't be up to much.

> You don't know much about this stuff.

Enough to know that you are improvising.

--
Bill Sloman, Nijmegen

[Jim Thompson]

Got any open-drain parts?

...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

[Jon Kirwan]

On Thu, 9 Aug 2012 15:10:55 -0700 (PDT),
bloggs.fred...@gmail.com wrote:

>><snip>

>> is located in the Naval History Center at the U.S. Naval
>>
>> Surface Warfare Center in Dahlgren, Virginia.
>
> The log book is in the Smithsonian and not some worn-out
> waste dump military museum.
> http://americanhistory.si.edu/collections/object.cfm?key=35&objkey=30
>
> Get a clue, most history as recalled by military related
> people/activities is 100% manure.

Interesting. I'd no idea at all, either way. But a quick
search did turn this up:

http://www.history.navy.mil/photos/images/h96000/h96566kc.htm

It says, "In 1988, the log, with the moth still taped by the
entry, was in the Naval Surface Warfare Center Computer
Museum at Dahlgren, Virginia."

Perhaps the book was transferred in the intervening period.

Jon

[Jon Kirwan]

Yes, now I find this:

http://www.jamesshuggins.com/h/tek1/first_computer_bug.htm

Jon

[Tim Williams]

"John Larkin" <jla...@highlandtechnology.com> wrote in message
news:1ug828tevc5abtnh2...@4ax.com...

> This isn't real bad...
>
> +V
> |
> |
> R
> |
> |
> logic in--------|<|-----+--------- logic out
> |
> |
> C
> |
> |
> gnd
>
> It doesn't discharge to ground, but it does discharge to a repeatable
> voltage, fast.

R is usually put across the diode, then you point the diode in the direction
you want the delay.

[John Larkin]

I don't do that. I only simulate little snippets that I can't predict
the behavior of, like this little RLC thing. I never simulate whole
products. It takes too much time, isn't necessary, and the device
models are usually bad enough that the sim doesn't prove much.

We don't prototype, either. It's too complex and wastes time. We only
brassboard little snippets that we can't predict from data sheets or
past experience. We lay out real boards, formally release the docs to
production, and expect to be able to sell rev A.

>So stuff that "doesn't matter" in the simulation should still be
>included in the schematic data base. It may not matter now, but ti may
>matter when you have to go back through the documentation, years
>later, to find out why the hardware you are producing doesn't meet
>specification any more.
>
>
>> It would be insane to do full nonlinear EM analysis of a slow circuit,
>
>Obviously.
>
>> or to include parasitics that won't change things enough to matter.
>
>Much less insane - they document exactly what you thought you were
>doing, and how you were doing it. That can be less obvious a few years
>later.
>
>> Engineering involves knowing or calculating what matters and what
>> doesn't... otherwise you'd never get anything done.
>
>Not just knowing and calculating, but also documenting - so you really
>can build the same thing again and again.
>

That is production documentation. Entirely different.

When's the last time you said something pleasant?

--

John Larkin Highland Technology, Inc

jlarkin at highlandtechnology dot com

http://www.highlandtechnology.com

Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators

Custom laser drivers and controllers

Photonics and fiberoptic TTL data links

[John Larkin]

I'm not going to ask them to measure and twist and strip and solder 42
ga wire. It's under 3 mils in diameter, practically invisible. And
what do we do with a couple of feet of that, on a small PC board?

You've been winding one transformer for months, or years, and you're
still not done.

>
>> You don't know much about this stuff.
>
>Enough to know that you are improvising.

I'm designing electronics that works and sells, and you're not.

--

John Larkin Highland Technology, Inc

jlarkin at highlandtechnology dot com

http://www.highlandtechnology.com

Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators

Custom laser drivers and controllers

Photonics and fiberoptic TTL data links

[John Larkin]

On Thu, 9 Aug 2012 20:27:29 -0500, "Tim Williams"
<tmor...@charter.net> wrote:

>"John Larkin" <jla...@highlandtechnology.com> wrote in message
>news:1ug828tevc5abtnh2...@4ax.com...
>> This isn't real bad...
>>
>> +V
>> |
>> |
>> R
>> |
>> |
>> logic in--------|<|-----+--------- logic out
>> |
>> |
>> C
>> |
>> |
>> gnd
>>
>> It doesn't discharge to ground, but it does discharge to a repeatable
>> voltage, fast.
>
>R is usually put across the diode, then you point the diode in the direction
>you want the delay.

Usually? That causes the diode current to taper off to zero, which
extends the discharge tail. Keeping the diode current flowing keeps
the dynamic resistance low, which makes the discharge tau low.

[bloggs.fred...@gmail.com]

I gave you the link to the Smithsonian site which shows they have possession of it, assigned it an Object ID: 1994.0191.01, and have it on display there.
http://americanhistory.si.edu/collections/object.cfm?key=35&objkey=30
Note also on the same page "American engineers have been calling small flaws in machines "bugs" for over a century. Thomas Edison talked about bugs in electrical circuits in the 1870s." So the use of the term, bug, was three quarters of a century old by the time of Hopper incident. The terminology probably predates Edison by 100 years too- referring to any small hard to find component of a complex machine causing the entirety to malfunction.

[Bill Sloman]

On Aug 10, 3:38 am, John Larkin <jlar...@highlandtechnology.com>
wrote:
> On Thu, 9 Aug 2012 16:33:16 -0700 (PDT),BillSloman

>
>
>
>
>
>
>
>
>
> <bill.slo...@ieee.org> wrote:
> >On Aug 9, 6:56 pm, John Larkin
> ><jjlar...@highNOTlandTHIStechnologyPART.com> wrote:

> >> On Thu, 9 Aug 2012 09:22:50 -0700 (PDT),BillSloman

>
> >> <bill.slo...@ieee.org> wrote:
> >> >On Aug 9, 6:01 pm, John Larkin
> >> ><jjlar...@highNOTlandTHIStechnologyPART.com> wrote:

> >> >> On Thu, 9 Aug 2012 04:00:09 -0700 (PDT),BillSloman

More fool you.

> I only simulate little snippets that I can't predict

> the behaviour of, like this little RLC thing. I never simulate whole

> products. It takes too much time, isn't necessary, and the device
> models are usually bad enough that the sim doesn't prove much.

Hierachical circuit design lets you simulate snippets of a complete
(and consistent) circuit design. Having the sim run right may not
prove much, but it does prove that that part of the net-list hasn't
been corrupted by the wires getting hooked up wrong (which is the kind
of human error that happens often enough any automatic proof-reading
mechanism is very helpful).

> We don't prototype, either. It's too complex and wastes time.

That strikes me as sensible, particularly with fast circuits where the
actual printed circuit layout is a crucial part of the design. Again,
simulating a snippet with estimated track lengths, track inductances
and track capacitances provides a sanity check on the transfer of the
design into the documentation.

> We only
> brassboard little snippets that we can't predict from data sheets or
> past experience. We lay out real boards, formally release the docs to
> production, and expect to be able to sell rev A.

Everybody wants to sell the first example of whatever it is they are
producing. If your design process proceeds by such small increments
that you can do a "new" design in a fortnight you really ought to be
able to manage it most of the time.

>So stuff that "doesn't matter" in the simulation should still be

> >included in the schematic data base. It may not matter now, but it may

> >matter when you have to go back through the documentation, years
> >later, to find out why the hardware you are producing doesn't meet
> >specification any more.
>
> >> It would be insane to do full nonlinear EM analysis of a slow circuit,
>
> >Obviously.
>
> >> or to include parasitics that won't change things enough to matter.
>
> >Much less insane - they document exactly what you thought you were
> >doing, and how you were doing it. That can be less obvious a few years
> >later.
>
> >> Engineering involves knowing or calculating what matters and what
> >> doesn't... otherwise you'd never get anything done.
>
> >Not just knowing and calculating, but also documenting - so you really
> >can build the same thing again and again.
>
> That is production documentation. Entirely different.

It shouldn't be. Keeping them separate looses you a useful form of
"proof-reading" check.

> >> You, apparently, never get anything done.
>
> >I'm not getting much done at the moment, but nobody is paying me to do
> >stuff, or could give a shit when I get it done. When I was getting
> >paid, and other people were relying on me to get stuff done, I was a
> >lot more productive - unusually productive by U.K. standards, though

> >there were times when I wasn't producing what my manager thought that I

It must have been last week. Some nitwit claimed that I thought that I
was smarter than everybody else and I reminded them that there a few
posters here whom I do treat with considerable respect - Joerg comes
to mind, and Spehro Pefhany, amongst others.

More recently John Fields nailed krw for being the contemptible waste-
of-space that he's always been and I posted a brief congratulation.

--
Bill Sloman, Nijmegen

[Bill Sloman]

On Aug 10, 3:48 am, John Larkin <jlar...@highlandtechnology.com>
wrote:
> On Thu, 9 Aug 2012 17:16:10 -0700 (PDT),BillSloman

> >enamelled wire - mainly because the coil winding shop stocked 38

> >swg with both red and green enamel  (one was self-fluxing and one
> >wasn't (or something like that).
>
> >It worked just as well - because I had room for more twisted pair it
> >fell over at 150MHz rather than 500MHz but that was entirely due to
> >the extra length of the twisted pair winding, which put the low
> >frequency end down at about 50kHz, rather lower than fewer turns of
> >the Filotex could offer.
>
> >> Even CAT6 is ugly in the time domain, and needs a lot of equalization to send Ethernet data
> >> reliably.
>
> >When I was knowledgeable about Ethernet, back in 1980, it used proper
> >coax, and a single Ethernet might span a university campus. It's
> >changed a bit since then, and nobody has been paying me to keep up.
>
> >> Not to mention it being a nightmare in production.
>
> >Bifilar windings are a nightmare in production? Your production staff
> >can't be up to much.
>
> I'm not going to ask them to measure and twist and strip and solder 42
> ga wire. It's under 3 mils in diameter, practically invisible. And
> what do we do with a couple of feet of that, on a small PC board?

You wind it onto a small transformer coil former - I mentioned RM core
coil formers, and EP cores coil formers tend to be even more compact.
Here's the data sheet for the EP7 parts, which includes an surface-
mounting coil former.

http://www.farnell.com/datasheets/12366.pdf

People have been coping with 42 ga wire for years - it's not rocket
science. And the wire is perfectly visible under a binocular
microscope (which you've got to have for fine SMD work anyway)
although I can't remember ever having trouble seeing it (though I am
short-sighted and tended to take off my spectacles when I was working
on SMD boards).

> You've been winding one transformer for months, or years, and you're
> still not done.

I got the transformer and two different inductors wound a couple of
weeks ago. Finding someone who still has a small coil winding machine
did take about a week, but it all went quickly once I found a local
coil-winding firm. I still haven't got around to putting the double
screen on the transformer and over-winding it with the last - single-
layer - bifilar winding, but I will.

> >> You don't know much about this stuff.
>
> >Enough to know that you are improvising.
>
> I'm designing electronics that works and sells, and you're not.

Not at the moment. but I've quite done enough of it to know that you
aren't quite as "insanely good" at it as you like to think.

--
Bill Sloman, Nijmegen

[John Larkin]

That's insane. You're talking about a 42 gage twisted-pair delay line,
and you propose to wind it up, unshielded, onto a bobbin?

Try it and let us know how it works.

[k...@att.bizzzzzzzzzzzz]

He'll get right to it, after he finishes his oscillator.

[Jeff Liebermann]

On Fri, 10 Aug 2012 10:04:07 -0700, John Larkin
<jla...@highlandtechnology.com> wrote:

>>You wind it onto a small transformer coil former - I mentioned RM core
>>coil formers, and EP cores coil formers tend to be even more compact.
>>Here's the data sheet for the EP7 parts, which includes an surface-
>>mounting coil former.

>That's insane. You're talking about a 42 gage twisted-pair delay line,
>and you propose to wind it up, unshielded, onto a bobbin?

Do it thyself bifilar winding machine:
<http://photo.qip.ru/photo/iog.hotboxru/3518342/large/76321085.jpg>
I usually use two different insulation colors. There are plenty of
other plans and coil winding abominations found on the Internet.

Bifilar wire and trifler are commonly found in RF torid transformers,
double balanced mixers, power dividers/combiners, etc. The first time
I saw the insides of the cans, I was amazed that it could even be done
by humans. At the time, the tiny torid were made by MCL in Brooklyn,
New Yuck.

My guess(tm) is that the delay line would be simply wound flat onto a
long rod. It won't be very small, but it also won't leak signal
between multiple layers.

Some bifilar bonded wire suppliers:
<http://wires.co.uk/acatalog/bb_wire.html>
<http://www.mwswire.com/mfilar.htm>

>Try it and let us know how it works.

42AWG is difficult. At a former employer, we had a production small
RF coil winder that was worked with bifilar and trifilar wire. Then
it worked, it could spit out a months worth of production coils in a
few hours. When it didn't, we spend days trying to figure out why the
tiny wire was breaking. Much of the moving mechanism was devoted to
wire tension control.

However, if you don't like bifilar, maybe something like this:
<http://802.11junk.com/jeffl/crud/delay-line.jpg>
but that brings us back to where we started. You can buy passive
delay lines in a small package. Sigh.

--
Jeff Liebermann je...@cruzio.com
150 Felker St #D http://www.LearnByDestroying.com
Santa Cruz CA 95060 http://802.11junk.com
Skype: JeffLiebermann AE6KS 831-336-2558

[John Larkin]

On Fri, 10 Aug 2012 14:30:16 -0700, Jeff Liebermann <je...@cruzio.com>
wrote:

Everything considered, I'd rather pick-and-place a few cheap 0603
parts.

[Bill Sloman]

On 8/8/2012 4:14 PM, John Larkin wrote:
> On Tue, 7 Aug 2012 23:26:32 -0700 (PDT), Bill Sloman
> <bill....@ieee.org> wrote:
>
>> On Aug 8, 12:41 am, John Larkin <jlar...@highlandtechnology.com>
>> wrote:
>>> On Tue, 7 Aug 2012 15:23:43 -0700 (PDT),BillSloman
>>>
>>> <bill.slo...@ieee.org> wrote:

>>>> On Aug 7, 9:51 pm, John Larkin <jlar...@highlandtechnology.com> wrote:
>>>>> On Tue, 7 Aug 2012 11:00:34 -0700 (PDT), George Herold
>>>
>>>>> <gher...@teachspin.com> wrote:

>>>>>> On Aug 7, 12:55 pm, John Larkin

>>>>>> <jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
>>>>>>> I have a cmos logic signal that I want to delay a few ns.
>>>

>>>>>> How about a little piece of coax?
>>>
>>>>> It's hard to pick-and-place two feet of coax!
>>>

>>>> Farnell in Europe is still selling Filotex 1.22mm OD 75R coax. You
>>>> could wind a metre or so of that onto a RM core former and place it
>>>> like any other component.
>>>
>>>> http://nl.farnell.com/nexans/157296/cable-coax-miniature-per-m/dp/385...
>>>
>>>> Newark doesn't seem to stock it, so you'll have to go a different
>>>> distributor
>>>
>>> That would more than fill up the entire volume of the instrument I
>>> have in mind.
>>
>> Expand your mind, or start thinking about using a twisted pair of
>> 0.1mm OD enamelled copper wire as your transmission line.
>
> Expand back into the days of hand-wired NIM boxes? Google "surface
> mount" to see what's happening this millenium. Google "skin loss"
> while you're at it.

http://www.litz-wire.com/pdf%20files/Round_Litz_Recommended_Operating_Frequency_28-48_AWG_R3.07.09.2010.pdf

Even 48 awg is only recommended for 1.4MHz to 2.8MHz

Skin loss doesn't stop transmission lines from working as delay lines -
it just makes them a bit lossier

> My people can pick-and-place four parts in maybe 1% of the time it
> would take to fab/strip/solder/pack away a twisted pair. What a mess
> for production.

Wind the twisted pair onto a surface mount EP core coil former. I've
already posted a URL to the EP7 part. The EP13 part - CSHS-EP13-1S-10P-T
- may be a bit big for you, but see

http://www.ferroxcube.com/prod/assets/ep13.pdf

> Apologies for using "production" in your presence.

You don't seem to know much about what's possible in a serious
production environment. Your clowns may not be able to wind 43 swg
twisted pair onto a EP former, but you should be able to find a
sub-contractor who could do it for you, and then your laughable excuse
for a production facility should be able to reflow the surface mount
former onto your printed circuit board.

<snip>

--
Bill Sloman, Nijmegen

[Bill Sloman]

On 8/10/2012 7:04 PM, John Larkin wrote:
> On Fri, 10 Aug 2012 01:41:39 -0700 (PDT), Bill Sloman
> <bill....@ieee.org> wrote:
>
>> On Aug 10, 3:48 am, John Larkin <jlar...@highlandtechnology.com>
>> wrote:
>>> On Thu, 9 Aug 2012 17:16:10 -0700 (PDT),BillSloman
>>>
>>> <bill.slo...@ieee.org> wrote:
>>>> On Aug 9, 6:11 pm, John Larkin
>>>> <jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
>>>>> On Thu, 9 Aug 2012 01:37:09 -0700 (PDT),BillSloman
>>>
>>>>> <bill.slo...@ieee.org> wrote:
>>>>>> On Aug 9, 5:52 am, John Larkin
>>>>>> <jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
>>>>>>> On Wed, 8 Aug 2012 20:12:55 -0700 (PDT),BillSloman
>>>
>>>>>>> <bill.slo...@ieee.org> wrote:
>>>>>>>> On Aug 9, 12:23 am, whit3rd <whit...@gmail.com> wrote:
>>>>>>>>> On Wednesday, August 8, 2012 2:13:35 PM UTC-7, John Larkin wrote:
>>>>>>>>>> On Wed, 8 Aug 2012 12:07:02 -0700 (PDT), "langw...@fonz.dk"
>>>
>>>>>>>>>> <langw...@fonz.dk> wrote:
>>>
>>>>>>>>>>> On 8 Aug., 20:21, whit3rd <whit...@gmail.com> wrote:
>>>
>>>>>>>>>>>> On Tuesday, August 7, 2012 9:55:41 AM UTC-7, John Larkin wrote:

<snip>

>>>>> Not to mention it being a nightmare in production.
>>>
>>>> Bifilar windings are a nightmare in production? Your production staff
>>>> can't be up to much.
>>>
>>> I'm not going to ask them to measure and twist and strip and solder 42
>>> ga wire. It's under 3 mils in diameter, practically invisible. And
>>> what do we do with a couple of feet of that, on a small PC board?
>>
>> You wind it onto a small transformer coil former - I mentioned RM core
>> coil formers, and EP cores coil formers tend to be even more compact.
>> Here's the data sheet for the EP7 parts, which includes an surface-
>> mounting coil former.
>
> That's insane. You're talking about a 42 gage twisted-pair delay line,
> and you propose to wind it up, unshielded, onto a bobbin?

Why not? Did you miss the undergraduate lecture where they told you that
twisted pair transmission lines don't generate significant external fields?

Each twist does have an external field, but they alternate in sign and
cancel pretty effectively.

> Try it and let us know how it works.

I haven't got the test gear. My transmission line transformer worked
fine using exactly that construction.

--
Bill Sloman, Nijmegen