Building a clock out of a PLD
Eric Inazaki
be really nice if I could use some of the otherwise unused gates (along
with a cap and a couple of resistors) to generate the clock. Is this
a bad idea, doomed to failure or is this sort of thing done all the
time? With respect to timing circuits in general, can PLDs be used in
place of discreet logic gates? In this particular case I'm using a
Lattice ispLSI1016E.
thanks,
eric
Jim Granville
>
> I have a PLD circuit which requires a clock signal. I'm thinking it'd
> be really nice if I could use some of the otherwise unused gates (along
> with a cap and a couple of resistors) to generate the clock.
> Is this a bad idea, doomed to failure or is this sort of thing done all the
> time?
Somewhere in-between :-)
Low Frequency RC oscillators, of 2/3 terminal design, are impractical
in
CPLD due to lack of pin hysteresis.
For low Freq sources, we use HEF4541, available in SO14.
For medium Freq, a TinyLogic single gate makes a good osc source.
You can quite safely build a 3 terminal OSC, (for higher precision),
using an external TinyLogic gate and a PLD 'gate'.
These solutions also keep the Icc down.
At higher freqs, > appx 5MHz, it is possible to construct 2/3 terminal
osc, with care. You need to do your own margin testing.
Better may be to removce the R's and C's entirely:
We have designed completely buried oscillators in the ATMEL
ATF150X family of cpld, using a chain of foldbacks.
I am not used to Lattice, but the Atmel devices have an option for a
single inverter in the 'corner of a macrocell', that can be used for
simple tasks, without loosing the whole macrocell.
The foldback delay is 2.8nS/5.5nS for low/High power MC switch, so
the lowest Freq from a single block OSC of 15 foldbacks in series,
is 6MHz and 12MHz.
This will of course vary with Vcc, Temperature and Process changes, but
many designs do not care too much about the clock freq.
You can also chain these Foldback's as delay lines.
> With respect to timing circuits in general, can PLDs be used in
> place of discreet logic gates?
If you mean RC timing, like 4528, 4093, 40106, HC14, then no.
If you mean counter chains, like 4060/4040 then yes.
> In this particular case I'm using a
> Lattice ispLSI1016E.
>
> thanks,
> eric
======= 80x51 Tools & PLD IP Specialists =========
= http://www.DesignTools.co.nz
Eric Inazaki
<jim.gr...@designtools.co.nz> wrote:
> Eric Inazaki wrote:
> >
> > I have a PLD circuit which requires a clock signal. I'm thinking it'd
> > be really nice if I could use some of the otherwise unused gates (along
> > with a cap and a couple of resistors) to generate the clock.
> > Is this a bad idea, doomed to failure or is this sort of thing done all the
> > time?
>
> Somewhere in-between :-)
I'm looking to do something in the few to few-tens of kHz. Would you
consider that to be at the low end of the scale?
The circuit I have in mind has an inverter whose output is the clk
signal. This output also feeds a resistor (R1). The other end of
R1 is connected to a cap (C) and another resistor (R2). The other
end of R2 goes to the input of a buffer. The buffer's output, the
inverter's input and the other leg of C are all tied together. (I
know, pictures would be a big help.) BTW, is this what you mean by
3 terminal design?
>
> Low Frequency RC oscillators, of 2/3 terminal design, are impractical
> in
> CPLD due to lack of pin hysteresis.
Ouch, that could be a problem. I should go look through my data sheets.
I don't suppose there are any PLDs that have Schmitt trigger inputs
(either configurable, or hard wired)?
> For low Freq sources, we use HEF4541, available in SO14.
> For medium Freq, a TinyLogic single gate makes a good osc source.
> You can quite safely build a 3 terminal OSC, (for higher precision),
> using an external TinyLogic gate and a PLD 'gate'.
>
> These solutions also keep the Icc down.
>
For my purposes, if I can't do the PLD thing I'll probably just break
out a 555. I only need 2kHz or so and accuracy and stability are pretty
much non-issues (or so I hope).
> At higher freqs, > appx 5MHz, it is possible to construct 2/3 terminal
> osc, with care. You need to do your own margin testing.
>
> Better may be to removce the R's and C's entirely:
>
> We have designed completely buried oscillators in the ATMEL
> ATF150X family of cpld, using a chain of foldbacks.
>
Any chance you could point me towards an app note, text reference
or sample circuits?
>
> > With respect to timing circuits in general, can PLDs be used in
> > place of discreet logic gates?
>
> If you mean RC timing, like 4528, 4093, 40106, HC14, then no.
> If you mean counter chains, like 4060/4040 then yes.
>
>
I'm thinking either a delayed monostable or a straight delay.
The delay and pulse width would be on the order of few to tens
of microseconds.
> ======= 80x51 Tools & PLD IP Specialists =========
> = http://www.DesignTools.co.nz
Thanks for all the input, you've given me quite a bit to chew on.
I've actually just started doing things w/ PLDs. PLDs rock, especially
these isp types.
eric
Maki
You only need resistor between in and out an cap between input and gnd.
Rest of the buffers You can tie in parallel so you can have more power on
the output.
This config works fine to approx. 1Mhz with 5V Vcc.
And less number of components comparing with 555 design.
Regards
M.
--
Veselic Mladen
Laboratorija Sigma
ECO Izenjering
Eric Inazaki <pen...@deadbeat.edu> wrote in message
news:140820012044292591%pen...@deadbeat.edu...
Jim Granville
>
> In article <3B79C3...@designtools.co.nz>, Jim Granville
> <jim.gr...@designtools.co.nz> wrote:
>
> I'm looking to do something in the few to few-tens of kHz. Would you
> consider that to be at the low end of the scale?
>
> The circuit I have in mind has an inverter whose output is the clk
> signal. This output also feeds a resistor (R1). The other end of
> R1 is connected to a cap (C) and another resistor (R2). The other
> end of R2 goes to the input of a buffer. The buffer's output, the
> inverter's input and the other leg of C are all tied together. (I
> know, pictures would be a big help.) BTW, is this what you mean by
> 3 terminal design?
Yes. When building this from non Hyst elements, the NonInverter (CAP)
stage should go first, then the inverter (Resistor) stage.
That way, regenerative feedback comes first, then the slower RC -ve
feedback
can come later.
> > For low Freq sources, we use HEF4541, available in SO14.
> > For medium Freq, a TinyLogic single gate makes a good osc source.
> > You can quite safely build a 3 terminal OSC, (for higher precision),
> > using an external TinyLogic gate and a PLD 'gate'.
> >
> > These solutions also keep the Icc down.
> >
>
> For my purposes, if I can't do the PLD thing I'll probably just break
> out a 555. I only need 2kHz or so and accuracy and stability are pretty
> much non-issues (or so I hope).
CMOS 555's are also a good solution - higher Icc than a 4541/40106, but
fewer pins..
>
> > At higher freqs, > appx 5MHz, it is possible to construct 2/3 terminal
> > osc, with care. You need to do your own margin testing.
> >
> > Better may be to removce the R's and C's entirely:
> >
> > We have designed completely buried oscillators in the ATMEL
> > ATF150X family of cpld, using a chain of foldbacks.
> >
>
> Any chance you could point me towards an app note, text reference
> or sample circuits?
I've put an example on our web:
http://www.designtools.co.nz/lcd32ser.zip
This is a LCD serial interface driver, and has a chain of
foldbacks as a delay line, used for a Latch+XOR to drive a
LCD backplane, using a ATF1502ASL.
>
> >
> > > With respect to timing circuits in general, can PLDs be used in
> > > place of discreet logic gates?
> >
> > If you mean RC timing, like 4528, 4093, 40106, HC14, then no.
> > If you mean counter chains, like 4060/4040 then yes.
> >
> >
>
> I'm thinking either a delayed monostable or a straight delay.
> The delay and pulse width would be on the order of few to tens
> of microseconds.
For this scale, consider a monostable-counter, using the buried
Foldback
OSC, and a triggered saturating counter - you'll get zero external
components, and a time resolution of ~166nS
- jg
luigi funes
Eric Inazaki ha scritto nel messaggio
<140820011643075782%pen...@deadbeat.edu>...
>With respect to timing circuits in general, can PLDs be used in
>place of discreet logic gates? In this particular case I'm using a
>Lattice ispLSI1016E.
In my esperience, yes.
I did oscillators just with Lattice 1K and 2K CPLD series.
You have to configure a macrocell as a simple inverter and
connect the input and the output to two adjacent pins.
Internally you connect the macrocell output to the clock lines.
Externally, you connect input and output with a resistor
and the input with a capacitor to ground.
This works in a very wide frequency range, also shorting input
and output directly and without any capacitor to obtain
easily 100-200 MHz!
Unfortunately this kind of oscillator is unreliable as it is unstable
and sensitive to noise, so you have to use it with caution.
Luigi
Ken Smith
I've done this with other types of PLDs. You need to make 2 inverters in
the PAL. The non-inverted output connects to the input via a capacitor,
or a resistor and capacitor in series. The inverting output connects via
a resistor to the input. It is the same circuit you make from a CMOS
logic gate. You take the clock from the second inverter's output.
In article <140820011643075782%pen...@deadbeat.edu>,
--
--
kens...@rahul.net forging knowledge
Eric Inazaki
you running?
Thanks,
eric
Martin Rice
I've used a two-inverter circuit oscillator, using gates inside a
Coolrunner (Xilinx) PLD. The circuit goes:
inverter between nodes A and B
inverter between nodes B and C
100nF between C and A
10k between A and B
I got nice square waves at B and C; exponential decay at A, 1.7ms
period.
Unfortunately, the signal generated was useless as a clock for further
circuits inside the CPLD! Not sure why... the square waves had nice
clean edges. I guess the chip didn't like the slow edges at A. I
think your inverter/buffer circuit would have the same problem since
there is an exponential decay waveform at the input to the buffer.
BTW, I think your circuit would work (in non-CPLD implementation) if
you replace R2 with short.
I ended up using 555. R from output to threshold/trigger;
C from threshold/trigger to GND. Gives nice output. Rarely seen this
simple circuit published. Only drawback I know is that output doesn't
go rail to rail for bipolar version (but does for CMOS).
Have fun.
Jim Granville
>
> Eric Inazaki <pen...@deadbeat.edu> wrote in message news:<140820011643075782%pen...@deadbeat.edu>...
> > I have a PLD circuit which requires a clock signal. I'm thinking it'd
> > be really nice if I could use some of the otherwise unused gates (along
> > with a cap and a couple of resistors) to generate the clock. Is this
> > a bad idea, doomed to failure or is this sort of thing done all the
> > time? With respect to timing circuits in general, can PLDs be used in
> > place of discreet logic gates? In this particular case I'm using a
> > Lattice ispLSI1016E.
> >
> > thanks,
> > eric
>
> I've used a two-inverter circuit oscillator, using gates inside a
> Coolrunner (Xilinx) PLD. The circuit goes:
> inverter between nodes A and B
> inverter between nodes B and C
> 100nF between C and A
> 10k between A and B
>
> I got nice square waves at B and C; exponential decay at A, 1.7ms
> period.
>
> Unfortunately, the signal generated was useless as a clock for further
> circuits inside the CPLD! Not sure why... the square waves had nice
> clean edges. I guess the chip didn't like the slow edges at A. I
> think your inverter/buffer circuit would have the same problem since
> there is an exponential decay waveform at the input to the buffer.
What looks 'clean' to even a 100Mhz Scope may not be a clean-enough
clock signal, especially if it comes from a slow-slew oscillator!
> BTW, I think your circuit would work (in non-CPLD implementation) if
> you replace R2 with short.
The second R is not needed for timing, what it does is provide
overdrive
protection, and also improves stability.
Without it, you try and drive nominally 50% beyond the rails on the
RC node.
We have used 1R, and two equal C's to avoid both the overdrive,
and the very 'sensistive' node that an R.R.C oscillator gives.
But you take a hit in absolute tolerance, as C's are lower tolerance
than R's.
A good challenge for students, is to get them to design a LR oscillator
!
> I ended up using 555. R from output to threshold/trigger;
> C from threshold/trigger to GND. Gives nice output. Rarely seen this
> simple circuit published.
Probably because of
a) The nasty loads often seen on 555 lash-ups :-)
b) The Bipolar 555's did not go rail-rail on the output
so Freq tolerance is not as good.
You are right tho, a single RC two terminal config works,
( same as HC14/40106 circuit) and well with a CMOS version
- which are just ~25c.
Because C555's are 'everywhere', they are a better education/prototype
choice than TinyLogic, but I have seen designers swear they will never
ship anything with a 555 in it :-)
> Only drawback I know is that output doesn't
> go rail to rail for bipolar version (but does for CMOS).
-jg
Ben Franchuk
I would just use the good old fashioned Schmitt triggers.
--
Standard Disclaimer : 97% speculation 2% bad grammar 1% facts.
"Pre-historic Cpu's" http://www.jetnet.ab.ca/users/bfranchuk
Now with schematics.
Ken Smith
Eric Inazaki <eina...@mac.com> wrote:
>Do you recall what kind of PLD you used? Also, what frequency were
>you running?
In one case is was a T.I. TICPAL22V10Z running at about 5KHz.
In another case it was an I.C.T. 7024 running at about 100KHz
I've also made XTAL oscillators using PALs a the inverter.
Ken Smith
Martin Rice <jmr...@ntlworld.com> wrote:
[.. RC oscillator on Cool runner...]
>Unfortunately, the signal generated was useless as a clock for further
>circuits inside the CPLD! Not sure why... the square waves had nice
>clean edges. I guess the chip didn't like the slow edges at A.
There are some funnies in the Cool-Runner that I doubt have ever been
documented. If you use it for a XTAL oscillator, it is best to use up
another whole cell just to buffer the signal going to the clock pin. I
think the transistors in the input circuits respond up to the GHz range to
funnies on the edge.
>I ended up using 555. R from output to threshold/trigger;
>C from threshold/trigger to GND. Gives nice output. Rarely seen this
>simple circuit published. Only drawback I know is that output doesn't
>go rail to rail for bipolar version (but does for CMOS).
The output of the LM555 can have cross over distortion on it. If
you use Pin 7 (I think) the open collector transistor driving a resistor
makes quite a nice logic signal.
Andy Peters <andy [@] exponentmedia
> Because C555's are 'everywhere', they are a better education/prototype
> choice than TinyLogic, but I have seen designers swear they will never
> ship anything with a 555 in it :-)
Jim,
The main reason for not shipping something with a 555 in it is because
you've got to trim each and every one. And once you trim it, how do you
know that it stays trimmed in the field?
--andy