Delta Sigma ADC and clock noise
Vladimir Vassilevsky
Could you suggest a reading about the effects of clock jitter in
delta-sigma ADCs ? How does it affect SNR, THD, IMD, SFDR ? For some
reason, this practical aspect is not mentioned in the ADC datasheets and
manuals; the typical phrase is "good quality low jitter clock should be
provided", whatever it means.
It shouldn't be too difficult to figure out the numbers by hand; however
I am pretty sure there must be a closed form solution already.
Vladimir Vassilevsky
DSP and Mixed Signal Design Consultant
http://www.abvolt.com
David L. Jones
> Hello all,
>
> Could you suggest a reading about the effects of clock jitter in
> delta-sigma ADCs ? How does it affect SNR, THD, IMD, SFDR ? For some
> reason, this practical aspect is not mentioned in the ADC datasheets
> and manuals; the typical phrase is "good quality low jitter clock
> should be provided", whatever it means.
If they don't specify it then you can probably take it as given, that any
half decent clock oscillator will meet the spec.
But it would would probably make interesting reading, sorry, I don't have
any links.
I've worked on some high end low bandwidth delta-sigma devices that do
specify it, and the figure was around 1ns IIRC. But the device was
advertised as having a "jitter tolerant" architecture.
Dave.
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Tony
>Vladimir Vassilevsky wrote:
>> Hello all,
>>
>> Could you suggest a reading about the effects of clock jitter in
>> delta-sigma ADCs ? How does it affect SNR, THD, IMD, SFDR ? For some
>> reason, this practical aspect is not mentioned in the ADC datasheets
>> and manuals; the typical phrase is "good quality low jitter clock
>> should be provided", whatever it means.
>
>If they don't specify it then you can probably take it as given, that any
>half decent clock oscillator will meet the spec.
>But it would would probably make interesting reading, sorry, I don't have
>any links.
>
>I've worked on some high end low bandwidth delta-sigma devices that do
>specify it, and the figure was around 1ns IIRC. But the device was
>advertised as having a "jitter tolerant" architecture.
>
>Dave.
This interests me too, so please correct my errors - For, say, 100 dB SNR, clock jitter
noise (re the modulator sampling time) is rolled off by the modulator filter. So
practically, with 1 ns jitter into a 4th order SDADC we would need Fs to be no more than
50 MHz or so. allowing a final sampling rate of 1MHz or so. Yes? No?
Tony