24Hz to 60Hz PLL?
Chris
the loop would be a 60Hz square wave. Any CMOS level chips that would
be good for this? I understand that I would need to divide by a
decimal value of 2.5 for the loop.
Thanks,
Chris Maness
Spehro Pefhany
You could phase lock the 24Hz (movie frame rate?) to a 120Hz VCO
divided by 5, and divide the 120Hz by 2 to get 60Hz.
Jon Slaughter
The lcm of 24 and 60 is 120. This suggests the best you'll get is 5/2 if
looking for exactness. i.e., 5*24 = 120 = 2*60
tm
"Spehro Pefhany" <spef...@interlogDOTyou.knowwhat> wrote in message
news:eilbn5pphbtca65k6...@4ax.com...
Or divide the 24 Hz by 2 and lock a 60 Hz PLL to the 12 Hz by a divide by 5.
Same thing but your soln. has higher frequencies so smaller caps.
John Larkin
<christoph...@gmail.com> wrote:
CD or HC 4046, with a slow loop. Divide 24 by 2 and divide 60 by five
and lock at 12 Hz. There's some old IC (7490?) that will do both
divides for you.
John
Chris
wrote:
> On Fri, 12 Feb 2010 14:14:04 -0800 (PST), Chris
>
> >I need to make a PLL that slaves to a 24Hz square wave. The output of
> >the loop would be a 60Hz square wave. Any CMOS level chips that would
> >be good for this? I understand that I would need to divide by a
> >decimal value of 2.5 for the loop.
>
> >Thanks,
> >Chris Maness
>
> You could phase lock the 24Hz (movie frame rate?) to a 120Hz VCO
> divided by 5, and divide the 120Hz by 2 to get 60Hz.
That sounds better than trying to find a divide by 2.5. What chips
would suggest to accomplish the divide by 5? Are there complete PLL
chips that can be programed to divide by an odd number?
Yes, it is a 1 pulse/frame to pilot tone converter. Similar to:
http://www.webtfg.com/sync11.htm
However, this is not primarily intended to have a record level sine
wave out like "The Film Group" unit. I need a full 12V swing as an
input to a perforated tape deck for the sync motor in the unit.
Ideally I could have a lower level output to a digital recorder. This
could in turn be amplified upon playback and fed back to the
perforated tape deck. This would "resolve" the speed variations from
the camera. When the film is played back referenced to a crystal, it
would be synced to the film once the film has been scanned in to a
frame accurate telecine.
Thanks,
Chris Maness
Vladimir Vassilevsky
Chris wrote:
Use a PIC.
Lock on 24 Hz by input capture, generate 60 Hz by output compare. Do all
PLL logic in software. There will be a jitter of +/-1 timer clock,
however this will be much better then suggested analog solutions.
Vladimir Vassilevsky
DSP and Mixed Signal Design Consultant
http://www.abvolt.com
Jim Thompson
Low frequency PLL's often present competing needs for fast lock and
low jitter. So I've always been fond of this approach which "jerk"
locks an "oscillator" created with a shift-register and a stable clock
(dating back to 1983, where I had to extract data from a floppy whose
orientation and physical acceleration were PITA)....
http://analog-innovations.com/SED/FloppyDataExtractor.pdf
...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
Chris
Here is what I have so far:
Looking at the CD4046b data sheet, it looks like the most straight
forward design would be a Camera --> NE555 (to lengthen the 5ms pulse
from the camera to 21ms for real square wave. I am not sure if this
would be needed by the comparator)--> CD4046 (With an Divide by N
CD4059 dividing by 5)-->CD4060 ( Signal Out from Q2 would be divide by
2).
I already have a bunch of CD4060's from my last project. I also have
some NE556's. Seems very easy.
Thanks,
Chris Maness
Fred Bartoli
PLLs a those low frequencies are real slow if you need some 'jitter
free' output.
Square waves have only odd harmonics. You could square up your 24 Hz,
apply it to a narrow 120Hz BPF, then divide by two.
--
Thanks,
Fred.
Vladimir Vassilevsky
Jim Thompson wrote:
> On Fri, 12 Feb 2010 17:31:20 -0500, Spehro Pefhany
> <spef...@interlogDOTyou.knowwhat> wrote:
>
>
>>On Fri, 12 Feb 2010 14:14:04 -0800 (PST), Chris
>><christoph...@gmail.com> wrote:
>>
>>
>>>I need to make a PLL that slaves to a 24Hz square wave. The output of
>>>the loop would be a 60Hz square wave. Any CMOS level chips that would
>>>be good for this? I understand that I would need to divide by a
>>>decimal value of 2.5 for the loop.
>>>
>>>Thanks,
>>>Chris Maness
>>
>>You could phase lock the 24Hz (movie frame rate?) to a 120Hz VCO
>>divided by 5, and divide the 120Hz by 2 to get 60Hz.
>
>
> Low frequency PLL's often present competing needs for fast lock and
> low jitter.
Just another reason for doing it in the software. You can achieve an
approximate lock just in one period and then fine tune it as accurate
and low jittery as you need.
> So I've always been fond of this approach which "jerk"
> locks an "oscillator" created with a shift-register and a stable clock
> (dating back to 1983, where I had to extract data from a floppy whose
> orientation and physical acceleration were PITA)....
>
> http://analog-innovations.com/SED/FloppyDataExtractor.pdf
I have to synchronize different clocks to GPS 1Hz output to the accuracy
of 1e-9 or so...
Tim Wescott
Yup, except that you don't need the 555 if you're using a digital in --
for that you want to use the 3-state phase/frequency comparator in the
4046, which is edge sensitive anyway.
Martin Riddle
"Vladimir Vassilevsky" <nos...@nowhere.com> wrote in message
news:UqOdnWHSjYZDQOjW...@giganews.com...
Hi Vladimir, Is there good reading references for doing a software PLL
anywhere.
So far in my casual searches, I've found very little on a software
implementation.
Cheers
Spehro Pefhany
As JL suggested, the 74HC390 (modern dual version of the old 7490 with
power pins in the normal positions) will give you both divide by 2 and
5, with half a chip left over.
>I already have a bunch of CD4060's from my last project. I also have
>some NE556's. Seems very easy.
>
>Thanks,
>Chris Maness
Best regards,
Spehro Pefhany
--
"it's the network..." "The Journey is the reward"
sp...@interlog.com Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog Info for designers: http://www.speff.com
Tim Wescott
No, but here you go. This will be a complete document, with
introduction, discussion, analysis, and a conclusion:
Making digital PLLs in software is fun and easy (introduction).
They're just like hardware PLL's (discussion)
except where they're different (analysis).
But they're easy, if you think hard. So go do it! (conclusion).
Was that too terse?
Martin Riddle
"Tim Wescott" <t...@seemywebsite.com> wrote in message
news:r6ydnaZqRLr2aOjW...@web-ster.com...
Sort of. Thanks
Cheers
MooseFET
How accurate is the 24Hz?
How good does the 60Hz need to be?
You can take a crystal and divide it down to make the 60Hz and
then make the counters get reset at a 12Hz rate to force it to
be in step.
An HC4046 will lock in just a couple of cycles if you use the
edge operated phase comparator. You can multiply up to several
hundred Hz to make the component values for the oscillator more
reasonable.
MooseFET
> "Spehro Pefhany" <speffS...@interlogDOTyou.knowwhat> wrote in message
In PLLs it is better to multiply up first then down.
MooseFET
> Chris wrote:
> > I need to make a PLL that slaves to a 24Hz square wave. The output of
> > the loop would be a 60Hz square wave. Any CMOS level chips that would
> > be good for this? I understand that I would need to divide by a
> > decimal value of 2.5 for the loop.
>
> Use a PIC.
>
[ducks]
Jon Slaughter
A simple and straightforward method:
for(i = 0; i < N; i++)
if ((i + k) % M == 0) recompute k, toggle clock;
Choose N, k, M appropriately. The loop is synched to the first clock. This
method only works when increasing the clock speed but has a similar method
for the opposite case. If N can be appropriately chosen then k can be set to
0.
Robert Baer
Chris
> Chris a écrit :
The 24Hz is square. What would I use for a BP filter at such a LF
without having a very large inductor?
Chris
Fred Bartoli
> On Feb 12, 3:21 pm, Fred Bartoli <" "> wrote:
Make that an active filter. Only Rs and Cs, and at that low frequency,
any opamp will nicely do.
--
Thanks,
Fred.
Chris
By dividing in the loop -- you are multiplying by 5. That is what I
meant. The sum effect of the dividing is multiplying.
How much jitter would the combo that I put together have? I can
accept a lock time of a few cycles, I can accept jitter if it only
effects the pulse width and it is not too bad.
As far as the PIC, I have not programmed one before, and I have no
clue on where to start. I can do basic, and some bash script, but I
have never used anything like assembler. I was hoping to order a few
chips from digikey, wire them together, and be done with it. If using
a PIC is fairly easy for a n00b, then I would be willing to look into
it.
Thanks,
Chris
Vladimir Vassilevsky
Personally I despise PICs. However PIC became a generic word for any
small microcontroller. Once a customer asked me if I work with PIC
controllers made by AVR company.
Jim Thompson
Caution: At such low frequencies, capacitor dissipation can play a
critical role in screwing up active filter performance.
Clear back in the early '70's, while designing telephone filters I
discovered you can negate dissipation factor by making your
integrators such...
http://analog-innovations.com/SED/StateVariableFilter(P+1).pdf
Paste rather than just click, Agent doesn't like parentheses in a URL.
I don't know about the behavior of other readers.
Vladimir Vassilevsky
Martin Riddle wrote:
> "Vladimir Vassilevsky" <nos...@nowhere.com> wrote in message
> news:UqOdnWHSjYZDQOjW...@giganews.com...
>
>>
>>Chris wrote:
>>
>>
>>>I need to make a PLL that slaves to a 24Hz square wave. The output
>>>of
>>>the loop would be a 60Hz square wave. Any CMOS level chips that
>>>would
>>>be good for this? I understand that I would need to divide by a
>>>decimal value of 2.5 for the loop.
>>
>>Use a PIC.
>>
>>Lock on 24 Hz by input capture, generate 60 Hz by output compare. Do
>>all PLL logic in software. There will be a jitter of +/-1 timer clock,
>>however this will be much better then suggested analog solutions.
>>
> Hi Vladimir, Is there good reading references for doing a software PLL
> anywhere.
> So far in my casual searches, I've found very little on a software
> implementation.
If you go to a local univercity library, there is a whole shelf of books
on the matter of digital PLLs and phase synchronization. They all talk
about essentially the same things and they seem to be retellings of each
other. I really can't recommend a particular one.
As for the OP's problem, it is VERY simple.
1. Estimate the phase of 24 Hz from input capture readings.
2. Multiply the phase by 2.5 modulo period.
3. Find the difference between this phase and the phase of 60 Hz.
4. Apply this difference to the frequency of 60 Hz through a filter.
Here we go. Takes 20 lines of code or so.
MooseFET
> MooseFET wrote:
> > On Feb 12, 3:01 pm, Vladimir Vassilevsky <nos...@nowhere.com> wrote:
>
> >>Chris wrote:
>
> >>>I need to make a PLL that slaves to a 24Hz square wave. The output of
> >>>the loop would be a 60Hz square wave. Any CMOS level chips that would
> >>>be good for this? I understand that I would need to divide by a
> >>>decimal value of 2.5 for the loop.
>
> >>Use a PIC.
>
> > No, the 8051 is the right processor for this.
>
> Personally I despise PICs. However PIC became a generic word for any
> small microcontroller. Once a customer asked me if I work with PIC
> controllers made by AVR company.
The PIC isn't all that bad. It is just a little weirder than it
needed
to be. I think part of it is because they did'nt think through the
step
to the next larger size.
When they designed the assembler for it, they compounded the
weirdness.
Given what it can do, a assembler that took expressions like:
A += Variable
Variable += A
would have made it easier to read.
Chris
Well the reason I am straying away from the MCU idea is that I really
want to just finish the project. I am doing it in my spare time. If
I could program it in about the same amount of time it would take me
to put together the aforementioned list of parts, then I am all ears.
However, never having messed around with programing a chip before, I
am thinking this could take another couple of dozen hours to
accomplish the task (factoring in a learning curve).
However, if you guys think that the signal from my design would be too
jittery to be useful than I guess I don't have a choice, but to take
the MCU route.
Thanks,
Chris
whit3rd
<jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
> On Fri, 12 Feb 2010 14:14:04 -0800 (PST), Chris
>
> >I need to make a PLL that slaves to a 24Hz square wave. The output of
> >the loop would be a 60Hz square wave.
> CD or HC 4046, with a slow loop. Divide 24 by 2 and divide 60 by five
> and lock at 12 Hz.
Right chip, but the best strategy is to lock a high frequency to a
multiple
of the 24 Hz, NOT to lock at 12 Hz. The loop filter works better at
the highest frequency, and the noise pickup would improve if
you went higher than that. Then, divide 240 by 4 to get the 60 Hz,
and by five then by two to get the 24 Hz for the phase comparison.
The 'divide by two' on each branch guarantees accurate 50% duty cycle,
many
counters have asymmetric outputs.
John Larkin
wrote:
The input only furnishes information 24 times a second (48 if you can
use both edges) so it doesn't much matter what the oscillator
frequency is. The VCO could be 60KHz and the loop dynamics wouldn't be
any better.
Granted, 24 is twice as good as 12. So you could run the VCO at 120,
and then divide by 5 to get 24 for the pll, and also divide by 2 to
get the 60.
The phase:frequency detector in the 4046 is edge sensitive, so duty
cycle doesn't matter if you use that one.
John
Jim Thompson
John's last paragraph is absolutely correct... Ron Treadway and I
designed it to be that way :-P
BobW
"Jim Thompson" <To-Email-Use-Th...@My-Web-Site.com> wrote in
message news:ofaen5hs1erom244n...@4ax.com...
Really?
I loved the 4046 and used it in several designs.
Bob
--
== All google group posts are automatically deleted due to spam ==
Jim Thompson
The 4046 is actually a CMOS translation and copy, merging my MC4024
VCM and Ron's and my MC4044 PFD, both done originally in TTL (around
1968). The MC4024 was good up to around 30MHz (it was really PECL
with a translator to TTL ;-)
Later there were actual PECL releases: MC1658 VCM, and MC12040 PFD.
Then there's also my MC1648 tank-type VCO... no longer made :-( Though
I designed an improved replica on a custom ASIC just this last year.
One of my original OpAmps, the MC1530/31, designed in 1963, is still
being manufactured (by Lansdale)... made for 47 years now ;-)
Phil Hobbs
So how come you put that stupid deadband in there? ;)
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal
ElectroOptical Innovations
55 Orchard Rd
Briarcliff Manor NY 10510
845-480-2058
hobbs at electrooptical dot net
http://electrooptical.net
Jim Thompson
That's a mismatched delay issue. Later versions have that "fixed" by
overlapping the U/D outputs.
Phil Hobbs
Sort of hard to fix when the pulse goes completely away--with a given
slew rate, there's some range in which both the height and width of the
pulse depend on the phase error--which produces a flat spot in the
V(phi) curve. Or do the fixed versions pulse high, pulse low, and then
go tri-state at zero phase error? That would still give some ripple,
but that's a big improvement over deadbands.
Any part numbers with the fixed version? That caused me grief as a
youth, till I realized I could just use a resistor to ground to move the
set point a bit away from phi=0.
Thanks
Robert Baer
MooseFET
Since you only need to work over a very narrow range, you can use a
crystal
in the VCO part of the PLL. If you hunt among the frequencies you can
get
from digikey, I think you will easily find one that you can pull onto
a
power of two times 60Hz. A very simple flip-flop based phase detector
can
get a low jitter correction signal. A slightly more complex on based
on some
tristating can get you even lower.
Enable the circuit output just before the "expected" rise of the 24Hz
Follow the 24Hz input until after the "expected" rise.
The "expected" value is a small number of clock cycles of the crystal.
This can either be picked by the designer or learned by the circuit
by decrementing the width until it just brackets the rise or
incrementing
if the rise goes outside the expected band.
This method has the noise rejection characteristics of the XOR method
for the case where there is a small noise in the input. It doesn't
have
a gain change as you go through the perfectly aligned case. This
means
that you can use a more extreme filter than the flip-flop case
normally
allows.
>
> Thanks,
> Chris
Jim Thompson
<pcdhSpamM...@electrooptical.net> wrote:
>On 2/13/2010 9:08 PM, Jim Thompson wrote:
>> On Sat, 13 Feb 2010 20:36:35 -0500, Phil Hobbs
>> <pcdhSpamM...@electrooptical.net> wrote:
>>
>>> On 2/13/2010 5:39 PM, Jim Thompson wrote:
>>>> On Sat, 13 Feb 2010 14:16:57 -0800, John Larkin
>>>> <jjla...@highNOTlandTHIStechnologyPART.com> wrote:
[snip]
>>>>
>>>> John's last paragraph is absolutely correct... Ron Treadway and I
>>>> designed it to be that way :-P
>>>>
>>>> ...Jim Thompson
>>>
>>> So how come you put that stupid deadband in there? ;)
>>>
>>> Cheers
>>>
>>> Phil Hobbs
>>
>> That's a mismatched delay issue. Later versions have that "fixed" by
>> overlapping the U/D outputs.
>>
>> ...Jim Thompson
>
>Sort of hard to fix when the pulse goes completely away--with a given
>slew rate, there's some range in which both the height and width of the
>pulse depend on the phase error--which produces a flat spot in the
>V(phi) curve. Or do the fixed versions pulse high, pulse low, and then
>go tri-state at zero phase error? That would still give some ripple,
>but that's a big improvement over deadbands.
The "fixed" version output current pulses of a minimum width.
>
>Any part numbers with the fixed version? That caused me grief as a
>youth, till I realized I could just use a resistor to ground to move the
>set point a bit away from phi=0.
AFAIK only in custom ASIC's.
>
>Thanks
>
>Phil Hobbs
Ban
"Phil Hobbs" <pcdhSpamM...@electrooptical.net> schrieb im Newsbeitrag
news:4B776A87...@electrooptical.net...
I use the Philips HC7046A which has real current sources and no deadband.
ciao Ban
Michael A. Terrell
Vladimir Vassilevsky wrote:
>
> Just another reason for doing it in the software. You can achieve an
> approximate lock just in one period and then fine tune it as accurate
> and low jittery as you need.
Only if you don't know how to do it without a microprocessor. PLLs
were around long before using your method. The ones we built for deep
space telemetry had TTL inputs for the dividers, but they could be
programmed with anything from a diode array to thumb wheel switches long
before a microprocessor was cheap enough.
We achieved a very low phase noise in the output without using your
method, with extremely low reference frequency leak through. The
settling time was quite good, as well. the same methods worked well at
lower frequencies, as well. Since he only wants one ratio, there is no
need to go to your extreme overkill.
--
Greed is the root of all eBay.
Jim Thompson
When I demonstrated (~1968) my first analog PLL (for aircraft ADF)
pulling out a signal completely buried in noise, none other than
Gardner himself said it couldn't be working :-)
For the OP, since he has a "square" source of 24Hz, I'd simply use a
PFD, a VCO at ~120Hz, DIV5 as feedback, DIV2 from VCO to get 60Hz.
Jim Thompson
<To-Email-Use-Th...@My-Web-Site.com> wrote:
>On Sun, 14 Feb 2010 14:15:42 -0500, "Michael A. Terrell"
><mike.t...@earthlink.net> wrote:
>
>>
>>Vladimir Vassilevsky wrote:
>>>
>>> Just another reason for doing it in the software. You can achieve an
>>> approximate lock just in one period and then fine tune it as accurate
>>> and low jittery as you need.
>>
>>
>> Only if you don't know how to do it without a microprocessor. PLLs
>>were around long before using your method. The ones we built for deep
>>space telemetry had TTL inputs for the dividers, but they could be
>>programmed with anything from a diode array to thumb wheel switches long
>>before a microprocessor was cheap enough.
>>
>> We achieved a very low phase noise in the output without using your
>>method, with extremely low reference frequency leak through. The
>>settling time was quite good, as well. the same methods worked well at
>>lower frequencies, as well. Since he only wants one ratio, there is no
>>need to go to your extreme overkill.
>
>When I demonstrated (~1968) my first analog PLL (for aircraft ADF)
>pulling out a signal completely buried in noise, none other than
>Gardner himself said it couldn't be working :-)
>
>For the OP, since he has a "square" source of 24Hz, I'd simply use a
>PFD, a VCO at ~120Hz, DIV5 as feedback, DIV2 from VCO to get 60Hz.
>
> ...Jim Thompson
Elaborating: Those suggesting harmonic filtering...
3rd Harmonic of 24Hz is 72Hz
5th Harmonic of 24Hz is 120Hz
Not an easy filtering job to keep the 3rd from "wobbulating"
everything ;-)
Tim Wescott
> On Sun, 14 Feb 2010 14:15:42 -0500, "Michael A. Terrell"
> <mike.t...@earthlink.net> wrote:
>
>
>>Vladimir Vassilevsky wrote:
>>>
>>> Just another reason for doing it in the software. You can achieve an
>>> approximate lock just in one period and then fine tune it as accurate
>>> and low jittery as you need.
>>
>>
>> Only if you don't know how to do it without a microprocessor. PLLs
>>were around long before using your method. The ones we built for deep
>>space telemetry had TTL inputs for the dividers, but they could be
>>programmed with anything from a diode array to thumb wheel switches long
>>before a microprocessor was cheap enough.
>>
>> We achieved a very low phase noise in the output without using your
>>method, with extremely low reference frequency leak through. The
>>settling time was quite good, as well. the same methods worked well at
>>lower frequencies, as well. Since he only wants one ratio, there is no
>>need to go to your extreme overkill.
>
> When I demonstrated (~1968) my first analog PLL (for aircraft ADF)
> pulling out a signal completely buried in noise, none other than Gardner
> himself said it couldn't be working :-)
>
> For the OP, since he has a "square" source of 24Hz, I'd simply use a
> PFD, a VCO at ~120Hz, DIV5 as feedback, DIV2 from VCO to get 60Hz.
>
> ...Jim Thompson
These days the least PCB space way to do this may well be with a digital
PLL in a microprocessor -- if this is _all_ you're doing you can do it
with _just_ a PIC in an SO-8 or smaller package; doing this in analog
without a dedicated chip will take at least two 14- or 16-pin chips (4046
and a 74xx counter), plus a small handful of resistors and some not-too-
small caps.
But one wants to choose something that is known to work, and fits with
the OP's abilities and situation. In a product I'd probably do it with a
micro; for a one-off I'd probably do it the 'analog' way.
Chris
percent. I doubt that I would be able to push or pull and xtal that
far off of it's designed freq.
Chris
Chris
I was waiting for some feedback on how stable my original design would
be. Since the comparator of my chip is edge detecting, I won't need
the NE555 (thanks for that tip). Some of the post recommend going the
micro processor rout because at that low frequency it would take a
little while for the loop to settle down. This delay is completely
acceptable as it takes about 5 seconds for the flywheel in the tape
deck to get up to speed, and the audio is real fluttery before that
happens. This would require me to pre-role the deck by a few seconds
if I was not planning on slating the scene. If I am slating I can
wait till the loop locks, and slate the camera/tape when lock is
achieved. I can add an LED for an indication of lock.
How much jitter can I expect? Does this jitter just effect pulse
width, or does it effect frequency?
Here is my original design:
Looking at the CD4046b data sheet, it looks like the most straight
forward design would be a Camera --> CD4046 (With an Divide by N
CD4059 dividing by 5)-->CD4060 ( Signal Out from Q2 would be divide by
2).
I already have a bunch of CD4060's from my last project. I also have
some NE556's. Seems very easy.
Thanks,
Chris Maness
MooseFET
For a few % I suggest an LC oscillator. The same ideas still apply.
The advantage of LC over RC is that it is naturally more stable so
you need a smaller range on the correction.
>
> Chris
Michael A. Terrell
Microdyne was still using a second source version of the MC4044 ten
years ago. We were having trouble getting a good supply, but i couldn't
convince them to switch to the 4046. The 'Engineer' responsible for
supporting older designs insisted it couldn't be used, because it was
too slow. He wouldn't look at the 20 year old drawings, and wouldn't
admit that the PLL only had to lock to a 100 KHz reference.
Jim Thompson
I have no idea who made the 4046 copy originally, but they blundered
several features :-(
JosephKK
>
>
>Jim Thompson wrote:
>
>> On Fri, 12 Feb 2010 17:31:20 -0500, Spehro Pefhany
>> <spef...@interlogDOTyou.knowwhat> wrote:
>>
>>
>>>On Fri, 12 Feb 2010 14:14:04 -0800 (PST), Chris
>>><christoph...@gmail.com> wrote:
>>>
>>>
>>>>I need to make a PLL that slaves to a 24Hz square wave. The output of
>>>>the loop would be a 60Hz square wave. Any CMOS level chips that would
>>>>be good for this? I understand that I would need to divide by a
>>>>decimal value of 2.5 for the loop.
>>>>
>>>>Thanks,
>>>>Chris Maness
>>>
>>>You could phase lock the 24Hz (movie frame rate?) to a 120Hz VCO
>>>divided by 5, and divide the 120Hz by 2 to get 60Hz.
>>
>>
>> Low frequency PLL's often present competing needs for fast lock and
>> low jitter.
>
>Just another reason for doing it in the software. You can achieve an
>approximate lock just in one period and then fine tune it as accurate
>and low jittery as you need.
>
>> So I've always been fond of this approach which "jerk"
>> locks an "oscillator" created with a shift-register and a stable clock
>> (dating back to 1983, where I had to extract data from a floppy whose
>> orientation and physical acceleration were PITA)....
>>
>> http://analog-innovations.com/SED/FloppyDataExtractor.pdf
>
>I have to synchronize different clocks to GPS 1Hz output to the accuracy
>of 1e-9 or so...
>
>Vladimir Vassilevsky
>DSP and Mixed Signal Design Consultant
>http://www.abvolt.com
I have always found it mind sposhing anti-clever to use (or even generate)
a 1 pps signal from GPS receivers.
JosephKK
Not so hard with a VCO at 240 Hz, divide by 10 with symmetrical output
74hc90, and divide by four 74hc74 (for 60 Hz) and cd4046 for vco.
Jim Thompson
Trivial with a PLL... not so trivial when suggesting a harmonic game.
JosephKK
>On Feb 12, 3:21 pm, Fred Bartoli <" "> wrote:
>> Chris a écrit :
>>
>> > I need to make a PLL that slaves to a 24Hz square wave. The output of
>> > the loop would be a 60Hz square wave. Any CMOS level chips that would
>> > be good for this? I understand that I would need to divide by a
>> > decimal value of 2.5 for the loop.
>>
>> PLLs a those low frequencies are real slow if you need some 'jitter
>> free' output.
>>
>> Square waves have only odd harmonics. You could square up your 24 Hz,
>> apply it to a narrow 120Hz BPF, then divide by two.
>>
>> --
>> Thanks,
>> Fred.
>
>The 24Hz is square. What would I use for a BP filter at such a LF
>without having a very large inductor?
>
>Chris
Even the likes of myself have done that with RC filters.
You might want to use good op-amps (low noise, low bias current) though.
Chris
I am noticing there seems to be many ways to skin a cat ;o)
I will order the chips for the PLL as this seems to be the most
straight foreword way, and proto it on my solderless bread board. If
it does not work, I am only out of a couple of bucks and wiser for the
experience.
Thanks Guys, I will report back.
Chris Maness
MooseFET
Making the filter have a notch at the 3rd harmonic and a peak at the
5th is
easier than trying to make just a peak at 5th that excludes the 3rd
well
enough.
A second notch at the 7th harmonic may be needed.
If you want to stay in the semi-digital mode a little longer, you can
make some oneshot like circuits that construct this:
...---................---........---.............
---......----------......--------......----------
......---..........---..............---..........
With just two RCs, you can make the 5th harmonic much larger than the
other
components. This replaces one of the pole pairs in the filter with
some
oneshots.
Michael A. Terrell
Jim Thompson wrote:
>
> Michael A. Terrell wrote:
> >
> > Microdyne was still using a second source version of the MC4044 ten
> >years ago. We were having trouble getting a good supply, but i couldn't
> >convince them to switch to the 4046. The 'Engineer' responsible for
> >supporting older designs insisted it couldn't be used, because it was
> >too slow. He wouldn't look at the 20 year old drawings, and wouldn't
> >admit that the PLL only had to lock to a 100 KHz reference.
>
> I have no idea who made the 4046 copy originally, but they blundered
> several features :-(
Wasn't that designed by, or for RCA in the early '70s? I know
someone who worked for RCA at that time, but he was at the fab.
Jim Thompson
I think you're right, Michael. "CD"4046 seems to be the very first
moniker.
I've not actually tried the current 74HC4046 version but, were it done
right, with today's processing, it could be a screamer.
Phil Hobbs
> On Thu, 18 Feb 2010 10:22:36 -0500, "Michael A. Terrell"
> <mike.t...@earthlink.net> wrote:
>
>>
>> Jim Thompson wrote:
>>>
>>> Michael A. Terrell wrote:
>>>>
>>>> Microdyne was still using a second source version of the MC4044 ten
>>>> years ago. We were having trouble getting a good supply, but i couldn't
>>>> convince them to switch to the 4046. The 'Engineer' responsible for
>>>> supporting older designs insisted it couldn't be used, because it was
>>>> too slow. He wouldn't look at the 20 year old drawings, and wouldn't
>>>> admit that the PLL only had to lock to a 100 KHz reference.
>>>
>>> I have no idea who made the 4046 copy originally, but they blundered
>>> several features :-(
>>
>>
>> Wasn't that designed by, or for RCA in the early '70s? I know
>> someone who worked for RCA at that time, but he was at the fab.
>
> I think you're right, Michael. "CD"4046 seems to be the very first
> moniker.
>
> I've not actually tried the current 74HC4046 version but, were it done
> right, with today's processing, it could be a screamer.
>
> ...Jim Thompson
The PD is okay, though it still has the deadband, but they screwed up
the VCO--it craps out at low voltage. No more 100:1 or 1000:1 VCO ranges.
Cheers
John Larkin
The HC4046s I've used have about a 7 ns deadband. Annoying.
We've done some nice phase/frequency detectors in FPGAs. Rather than
try to make the outputs do charge pumping, we bring out separate
hard-CMOS UP and DOWN pulses, and use outboard schottky
diodes+resistors into the analog stuff. The whole charge pump concept
is a tad flakey, in my opinion.
I also like single flipflop bang-bang detection for narrowband loops.
No deadband, and loop gain is infinite!
John
Jim Thompson
If you implement the "charge pump" current mirrors on-chip, as I
regularly do in my ASIC designs, it becomes a non-issue.
Phil Hobbs
It does have the potentially useful feature that the reference ripple
goes away when you're exactly in phase. Might be sort of nice to do the
+- pulse thing with some minimum width value for both pulses, and use a
fast RC lowpass plus an analog switch to get rid of the up-down bumps
when you're near lock. Maybe use the lock detector to control the
switch--keep it closed when you're out of lock, and open it briefly to
get rid of the barump-bump when you're in lock.
The problem is always how much extra phase shift you can tolerate inside
the loop, and the VCO already contributes 90 degrees, which doesn't help.
>
> I also like single flipflop bang-bang detection for narrowband loops.
> No deadband, and loop gain is infinite!
A few nasty metastability issues, though--same as using D-flops for
mixers in offset loops. I learned my lesson about that in 1982, when I
was an astronomer masquerading as an EE.
MooseFET
If you are going for low noise, you really want the added stage of
logic
clean up that you get by doing the converting to analog outside the
chip.
>
> I also like single flipflop bang-bang detection for narrowband loops.
> No deadband, and loop gain is infinite!
It really isn't infinite. On the 74HC74 it is less than infinite
because
the set up time to cause the output to toggle is longer than the setup
to cause it to be the same. I don't recall how big the effect is but
it
is a small nonzero value. Perhaps with a different flip-flop it is
greater
than infinity and so it averages out.
Also a simple tri-state gate that you only enable while the carry out
of
the counter chain is true works as a nice sort of phase detector. It
is
a little like a no dead band version of the 2 flip-flop on in that for
most of the cycle, the filter capacitor has no current.
John Larkin
The bang-bang loops that I've done were EclipsLite ECL. The EL51 flop
seems to have a little setup/hold hysteresis, roughly 1 picosecond,
but that doesn't bother a relatively narrowbend loop, like locking a
VCXO to some external reference. It's hard to beat a
differential-input flipflop bang-bang detector when you want to hold a
couple of picoseconds absolute timing longterm.
Any jitter in the reference or the VCO smears out the transfer
function of the bangbang pd, making it effectively finite gain. I do
the loop math based on some assumption of some jitter.
John
Ban
>>>>> Jim Thompson wrote:
>> The HC4046s I've used have about a 7 ns deadband. Annoying.
>>
>> We've done some nice phase/frequency detectors in FPGAs. Rather than
>> try to make the outputs do charge pumping, we bring out separate
>> hard-CMOS UP and DOWN pulses, and use outboard schottky
>> diodes+resistors into the analog stuff. The whole charge pump concept
>> is a tad flakey, in my opinion.
>>
>> I also like single flipflop bang-bang detection for narrowband loops.
>> No deadband, and loop gain is infinite!
>>
>> John
>>
>
> If you implement the "charge pump" current mirrors on-chip, as I
> regularly do in my ASIC designs, it becomes a non-issue.
>
It has been done already many years ago
http://ics.nxp.com/products/hc/datasheet/74hc7046a.pdf
ciao Ban
MooseFET
Yes, you have to do that partly because doing math with infinite
values
is a lot harder.
In all digital stuff, I have used the change in state of the flip-flop
to provide the real part to make the loop stable. Basically what I
did was:
INC/DEC
! ----------------!
----- ! ! ----- !AND>----Gain one
Signal-----!D Q!----+--+----!D Q! --!
--!> ! --!> ! !
! ----- ! ! Q/!--
! !
NCO/M-- Clock
The Number Controlled Oscillator is just a divide by N counter where
the few bottom bits of N are controlled by the upper bits of another
counter that is hooked to the INC/DEC control. The "Gain One" signal
causes the NCO to increment by 2 on the next clock cycle. This some
of the phase lag making the system stable. Without it the output
wobbles either side of the correct value. instead of quickly and
randomly jittering. The wobble makes a lot of low frequency noise
in the output.
Jim Thompson
Of course "It has been done already many years ago". I invented dirt.
Also much of modern PLL technology.
Michael A. Terrell
Jim Thompson wrote:
>
> On Fri, 19 Feb 2010 08:01:31 +0100, "Ban" <ban...@web.de> wrote:
>
> >Jim Thompson wrote:
> >>>>>> Jim Thompson wrote:
> >>> The HC4046s I've used have about a 7 ns deadband. Annoying.
> >>>
> >>> We've done some nice phase/frequency detectors in FPGAs. Rather than
> >>> try to make the outputs do charge pumping, we bring out separate
> >>> hard-CMOS UP and DOWN pulses, and use outboard schottky
> >>> diodes+resistors into the analog stuff. The whole charge pump concept
> >>> is a tad flakey, in my opinion.
> >>>
> >>> I also like single flipflop bang-bang detection for narrowband loops.
> >>> No deadband, and loop gain is infinite!
> >>>
> >>> John
> >>>
> >>
> >> If you implement the "charge pump" current mirrors on-chip, as I
> >> regularly do in my ASIC designs, it becomes a non-issue.
> >>
> >
> >It has been done already many years ago
> >http://ics.nxp.com/products/hc/datasheet/74hc7046a.pdf
> >ciao Ban
> >
>
> Of course "It has been done already many years ago". I invented dirt.
> Also much of modern PLL technology.
Come on, Jim. We all know that the dirt was just a byproduct of you
doing your designs with chisels, on stone tablets. ;-)
Jim Thompson
By 1967-68, when I was doing PLL, we already had quadrille pads.
However we didn't yet have calculators... except for giant Philco
on-desk machines bigger than today's towers ;-)
Bitrex
Wouldn't the purchasing office spring for something like a Friden
EC-130? Delay line memory, a sexy CRT display, and only $2200 in 1964
dollars...
Michael A. Terrell
Jim Thompson wrote:
>
> By 1967-68, when I was doing PLL, we already had quadrille pads.
> However we didn't yet have calculators... except for giant Philco
> on-desk machines bigger than today's towers ;-)
I went to a mall in Dothan, Alabama in 1972 or 73 while I was
stationed at Ft. Rucker. The mall had two levels. The one at ground
level was full, but the underground level only had one store, and all it
sold was calculators. I wondered for years how long it lasted. :)
krw
I'm surprised they didn't have "The Scotch Tape Store" or "Spatula
City". ;-)
Jim Thompson
The boards for those were made (and installed) by Philco-Ford, Santa
Clara. When I did my short stint at P-F in 1968 (I left Motorola with
John Welty), I convinced them to dump it... they were, in essence,
shipping $1K with each unit :-(
In August 1968 the politicians who didn't like Welty decided to close
that division. The asked me how I'd like to go to Blue Bell. I
replied, "How'd you like to kiss my ass?" Really. So I called Walt
Seelbach (Mr. MECL) at Motorola and went straight back, to ultimately
work on PLL's.
The one and only time I left Arizona :-(
Michael A. Terrell
No, just $400 to $600 calculators and over 50 storefronts that were
still vacant.
Greegor
> MooseFET wrote:
> > On Feb 12, 3:01 pm, Vladimir Vassilevsky <nos...@nowhere.com> wrote:
>
> >>Chris wrote:
>
> >>>I need to make aPLLthat slaves to a24Hzsquare wave. The output of
> >>>the loop would be a60Hzsquare wave. Any CMOS level chips that would
> >>>be good for this? I understand that I would need to divide by a
> >>>decimal value of 2.5 for the loop.
>
>
> > No, the 8051 is the right processor for this.
>
> Personally I despise PICs. However PIC became a generic word for any
> small microcontroller. Once a customer asked me if I work with PIC
> controllers made by AVR company.
AVR?
Is that one of the Z80 compatible chips the Chinese
use to run MP/3 players, cameras etc?
I'd like to see 8 bit CP/M running on one and
starting with an MP/3 player with flash
memory, USB and an LCD for cheap would
make it more interesting.
See the CP/M usenet group.
Jan Panteltje
<gree...@gmail.com> wrote in
<7c4ed12c-c24b-41e0...@g11g2000yqe.googlegroups.com>:
You could then run my CP/M clone on it too, if it supports Z80 instructions:
http://panteltje.com/panteltje/z80/system14/index.html
But I do not think AVR knows about LDIR?
LD (IX-12), value?
hehe
linnix
> On Feb 13, 10:20 am, Vladimir Vassilevsky <nos...@nowhere.com> wrote:
>
>
>
> > MooseFET wrote:
> > > On Feb 12, 3:01 pm, Vladimir Vassilevsky <nos...@nowhere.com> wrote:
>
> > >>Chris wrote:
>
> > >>>I need to make aPLLthat slaves to a24Hzsquare wave. The output of
> > >>>the loop would be a60Hzsquare wave. Any CMOS level chips that would
> > >>>be good for this? I understand that I would need to divide by a
> > >>>decimal value of 2.5 for the loop.
>
> > >>Use a PIC.
>
> > > No, the 8051 is the right processor for this.
>
> > Personally I despise PICs. However PIC became a generic word for any
> > small microcontroller. Once a customer asked me if I work with PIC
> > controllers made by AVR company.
>
> AVR?
Yes, they are made by Norwegian Chinese and headquartered in San Jose
Chinatown. Chinese is a genetic term for hard working technical
people.
> Is that one of the Z80 compatible chips the Chinese
> use to run MP/3 players, cameras etc?
Good enough to control and power the ASICs.
> I'd like to see 8 bit CP/M running on one and
> starting with an MP/3 player with flash
> memory, USB and an LCD for cheap would
> make it more interesting.
Can CP/M runs in 4 to 8K RAM? Oh, wait. AVR can't run from RAM.
Chris
My parts came today. I tried my design, and it locks solid on the
right frequency finally. The new loop filter is awesome. Kudos to
Helmut for his damped loop filter. Also, my NE555 debounce circuit
fixed the frequency error problem. Yaaaah!
@Jan I will be trying your design next and see how it compares to mine
in lock time.
Thanks All
Chris Maness